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From: Chee, Tien Fong <tien.fong.chee@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 3/9] spl : socfpga: Implement fpga bitstream loading with socfpga loadfs
Date: Tue, 27 Nov 2018 08:55:51 +0000	[thread overview]
Message-ID: <1543308951.10323.17.camel@intel.com> (raw)
In-Reply-To: <8de13770-2e60-38c4-2cb4-ac175f2534d5@denx.de>

On Mon, 2018-11-26 at 12:20 +0100, Marek Vasut wrote:
> On 11/26/2018 11:10 AM, Chee, Tien Fong wrote:
> > 
> > On Fri, 2018-11-23 at 13:31 +0100, Marek Vasut wrote:
> > > 
> > > On 11/23/2018 10:51 AM, Chee, Tien Fong wrote:
> > > > 
> > > > 
> > > > On Wed, 2018-11-21 at 15:19 +0100, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 11/21/2018 11:41 AM, tien.fong.chee at intel.com wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > > 
> > > > > > Add support for loading FPGA bitstream to get DDR up
> > > > > > running
> > > > > > before
> > > > > > U-Boot is loaded into DDR. Boot device initialization,
> > > > > > generic
> > > > > > firmware
> > > > > > loader and SPL FAT support are required for this whole
> > > > > > mechanism to
> > > > > > work.
> > > > > > 
> > > > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > > ---
> > > > > >  arch/arm/mach-socfpga/spl_a10.c |   49
> > > > > > ++++++++++++++++++++++++++++++++++++++-
> > > > > >  common/spl/spl_mmc.c            |    2 +-
> > > > > >  include/mmc.h                   |    1 +
> > > > > >  3 files changed, 50 insertions(+), 2 deletions(-)
> > > > > > 
> > > > > > diff --git a/arch/arm/mach-socfpga/spl_a10.c
> > > > > > b/arch/arm/mach-
> > > > > > socfpga/spl_a10.c
> > > > > > index 3ea64f7..67a4fac 100644
> > > > > > --- a/arch/arm/mach-socfpga/spl_a10.c
> > > > > > +++ b/arch/arm/mach-socfpga/spl_a10.c
> > > > > > @@ -1,6 +1,6 @@
> > > > > >  // SPDX-License-Identifier: GPL-2.0+
> > > > > >  /*
> > > > > > - *  Copyright (C) 2012 Altera Corporation <www.altera.com>
> > > > > > + *  Copyright (C) 2012-2018 Altera Corporation <www.altera
> > > > > > .com
> > > > > > > 
> > > > > > > 
> > > > > >   */
> > > > > >  
> > > > > >  #include <common.h>
> > > > > > @@ -23,6 +23,10 @@
> > > > > >  #include <fdtdec.h>
> > > > > >  #include <watchdog.h>
> > > > > >  #include <asm/arch/pinmux.h>
> > > > > > +#include <asm/arch/fpga_manager.h>
> > > > > > +#include <mmc.h>
> > > > > > +
> > > > > > +#define RBF	0
> > > > > >  
> > > > > >  DECLARE_GLOBAL_DATA_PTR;
> > > > > >  
> > > > > > @@ -73,6 +77,49 @@ void spl_board_init(void)
> > > > > >  	WATCHDOG_RESET();
> > > > > >  
> > > > > >  	arch_early_init_r();
> > > > > > +
> > > > > > +	/* If the full FPGA is already loaded, ie.from
> > > > > > EPCQ,
> > > > > > config fpga pins */
> > > > > > +	if (is_fpgamgr_user_mode()) {
> > > > > > +		config_pins(gd->fdt_blob, "shared");
> > > > > > +		config_pins(gd->fdt_blob, "fpga");
> > > > > > +	} else if (!is_fpgamgr_early_user_mode()) {
> > > > > > +		/* Program IOSSM(early IO release) or full
> > > > > > FPGA */
> > > > > > +		fpga_fs_info fpga_fsinfo;
> > > > > > +		char buf[16 * 1024]
> > > > > > __aligned(ARCH_DMA_MINALIGN);
> > > > > > +		struct spl_boot_device bootdev;
> > > > > > +		int len = 0;
> > > > > > +
> > > > > > +		bootdev.boot_device = spl_boot_device();
> > > > > > +
> > > > > > +		/* Init MMC driver before reading FPGA
> > > > > > bitstream
> > > > > > from flash */
> > > > > > +		if (bootdev.boot_device ==
> > > > > > BOOT_DEVICE_MMC1) {
> > > > > > +			struct mmc *mmc = NULL;
> > > > > > +			int err = 0;
> > > > > > +
> > > > > > +			err = spl_mmc_find_device(&mmc,
> > > > > > bootdev.boot_device);
> > > > > > +			if (err)
> > > > > > +				return;
> > > > > > +
> > > > > > +			err = mmc_init(mmc);
> > > > > I thought all this backend specific stuff would be hidden in
> > > > > the
> > > > > FW
> > > > > loader.
> > > > The backend supported by FW loader is up to generic file system
> > > > interface layer. flash driver init is expected done by SPL/U-
> > > > Boot
> > > > common init sequence framwork or user. Unfortunately, fw loader
> > > > need to
> > > > access flash before init sequence.
> > > This is actually accessing eMMC though , not flash . If we need
> > > this
> > > huge boilerplate code every time we use the FW loader, than the
> > > FW
> > > loader needs fixing. I can understand the spl_boot_device() being
> > > outside of the FW loader, but not the mmc_init() and co.
> > I can explore the posibility of adding the flash int mechanism into
> > the
> > fm loader probe function.
> What do you mean by "flash int" ? Note that we're talking about eMMC
> here, not flash. Unless you mean "backend init" by all that, in which
> case that'd only make sense, thanks.
I means backend init such as MMC, and NAND driver init.
> 

  reply	other threads:[~2018-11-27  8:55 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-21 10:41 [U-Boot] [PATCH 0/9] Add support for loading FPGA bitstream tien.fong.chee at intel.com
2018-11-21 10:41 ` [U-Boot] [PATCH 1/9] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10 tien.fong.chee at intel.com
2018-11-21 14:11   ` Marek Vasut
2018-11-23  9:19     ` Chee, Tien Fong
2018-11-23 12:23       ` Marek Vasut
2018-11-26  9:44         ` Chee, Tien Fong
2018-11-26 11:15           ` Marek Vasut
2018-11-27  8:45             ` Chee, Tien Fong
2018-11-27 12:07               ` Marek Vasut
2018-11-28 14:49                 ` Chee, Tien Fong
2018-11-28 15:10                   ` Marek Vasut
2018-11-28 15:36                     ` Chee, Tien Fong
2018-11-28 16:17                     ` Chee, Tien Fong
2018-11-28 17:55                       ` Marek Vasut
2018-12-14  8:07                         ` Chee, Tien Fong
2018-11-21 10:41 ` [U-Boot] [PATCH 2/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading tien.fong.chee at intel.com
2018-11-21 14:18   ` Marek Vasut
2018-11-23  9:43     ` Chee, Tien Fong
2018-11-23 12:28       ` Marek Vasut
2018-11-26 10:09         ` Chee, Tien Fong
2018-11-26 11:18           ` Marek Vasut
2018-11-27  8:54             ` Chee, Tien Fong
2018-11-27 12:08               ` Marek Vasut
2018-11-28 14:53                 ` Chee, Tien Fong
2018-11-28 15:11                   ` Marek Vasut
2018-11-21 10:41 ` [U-Boot] [PATCH 3/9] spl : socfpga: Implement fpga bitstream loading with socfpga loadfs tien.fong.chee at intel.com
2018-11-21 14:19   ` Marek Vasut
2018-11-23  9:51     ` Chee, Tien Fong
2018-11-23 12:31       ` Marek Vasut
2018-11-26 10:10         ` Chee, Tien Fong
2018-11-26 11:20           ` Marek Vasut
2018-11-27  8:55             ` Chee, Tien Fong [this message]
2018-11-27 12:08               ` Marek Vasut
2018-11-21 10:41 ` [U-Boot] [PATCH 4/9] ARM: socfpga: Bundle U-Boot fitImage into SFP on Arria10 tien.fong.chee at intel.com
2018-11-21 14:21   ` Marek Vasut
2018-11-23  9:54     ` Chee, Tien Fong
2018-11-23 12:40       ` Marek Vasut
2018-11-26 10:30         ` Chee, Tien Fong
2018-11-26 11:22           ` Marek Vasut
2018-11-27  9:00             ` Chee, Tien Fong
2018-11-27 12:09               ` Marek Vasut
2018-11-28 14:43                 ` Chee, Tien Fong
2018-11-28 15:11                   ` Marek Vasut
2018-11-21 10:41 ` [U-Boot] [PATCH 5/9] ARM: socfpga: Add SPL fitImage config match tien.fong.chee at intel.com
2018-11-21 14:21   ` Marek Vasut
2018-11-23 10:05     ` Chee, Tien Fong
2018-11-23 12:34       ` Marek Vasut
2018-11-26 10:11         ` Chee, Tien Fong
2018-11-21 10:41 ` [U-Boot] [PATCH 6/9] ARM: socfpga: Set default DTB address on A10 tien.fong.chee at intel.com
2018-11-21 14:22   ` Marek Vasut
2018-11-23 10:10     ` Chee, Tien Fong
2018-11-23 12:39       ` Marek Vasut
2018-11-21 10:41 ` [U-Boot] [PATCH 7/9] ARM: socfpga: Use custom header target buffer in SPL tien.fong.chee at intel.com
2018-11-21 10:41 ` [U-Boot] [PATCH 8/9] ARM: socfpga: Add default fitImage for Arria10 SoCDK tien.fong.chee at intel.com
2018-11-21 10:41 ` [U-Boot] [PATCH 9/9] ARM: socfpga: Synchronize the configuration for A10 SoCDK tien.fong.chee at intel.com

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