From: Trent Piepho <tpiepho@impinj.com>
To: "robin.murphy@arm.com" <robin.murphy@arm.com>,
"stefan@agner.ch" <stefan@agner.ch>,
"hongxing.zhu@nxp.com" <hongxing.zhu@nxp.com>,
"l.stach@pengutronix.de" <l.stach@pengutronix.de>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
"festevam@gmail.com" <festevam@gmail.com>,
"andrew.smirnov@gmail.com" <andrew.smirnov@gmail.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"leonard.crestez@nxp.com" <leonard.crestez@nxp.com>
Subject: Re: [PATCH] pci: imx6: support kernels built in Thumb-2 mode
Date: Wed, 28 Nov 2018 18:56:18 +0000 [thread overview]
Message-ID: <1543431377.18519.94.camel@impinj.com> (raw)
In-Reply-To: <ff476784-b79e-18bf-5870-4365c8377deb@arm.com>
On Wed, 2018-11-28 at 16:16 +0000, Robin Murphy wrote:
>
> >
> > +static int imx6q_pcie_abort_handler_thumb2(unsigned long addr,
> > + unsigned int fsr, struct pt_regs *regs)
> > +{
> > + unsigned long pc = instruction_pointer(regs);
> > + unsigned long instr = *(unsigned long *)pc;
> > + unsigned long thumb2_instr = __mem_to_opcode_thumb16(instr);
> > + int reg = thumb2_instr & 7;
> > +
> > + if (!__opcode_is_thumb16(instr & 0x0000ffffUL))
> > + return 1;
>
> There are plenty of 32-bit Thumb encodings of various LDR/STR variants,
> and I doubt we can guarantee that the offset, target register, and/or
> addressing mode for a config space access will *always* suit the
> (relatively limited) 16-bit ones.
It might be the case that PLD/PLI, 32-bit thumb2 instructions, could
trigger an abort too.
WARNING: multiple messages have this Message-ID (diff)
From: tpiepho@impinj.com (Trent Piepho)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] pci: imx6: support kernels built in Thumb-2 mode
Date: Wed, 28 Nov 2018 18:56:18 +0000 [thread overview]
Message-ID: <1543431377.18519.94.camel@impinj.com> (raw)
In-Reply-To: <ff476784-b79e-18bf-5870-4365c8377deb@arm.com>
On Wed, 2018-11-28 at 16:16 +0000, Robin Murphy wrote:
>
> >
> > +static int imx6q_pcie_abort_handler_thumb2(unsigned long addr,
> > + unsigned int fsr, struct pt_regs *regs)
> > +{
> > + unsigned long pc = instruction_pointer(regs);
> > + unsigned long instr = *(unsigned long *)pc;
> > + unsigned long thumb2_instr = __mem_to_opcode_thumb16(instr);
> > + int reg = thumb2_instr & 7;
> > +
> > + if (!__opcode_is_thumb16(instr & 0x0000ffffUL))
> > + return 1;
>
> There are plenty of 32-bit Thumb encodings of various LDR/STR variants,
> and I doubt we can guarantee that the offset, target register, and/or
> addressing mode for a config space access will *always* suit the
> (relatively limited) 16-bit ones.
It might be the case that PLD/PLI, 32-bit thumb2 instructions, could
trigger an abort too.
next prev parent reply other threads:[~2018-11-28 18:56 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-28 13:25 [PATCH] pci: imx6: support kernels built in Thumb-2 mode Stefan Agner
2018-11-28 13:25 ` Stefan Agner
2018-11-28 16:16 ` Robin Murphy
2018-11-28 16:16 ` Robin Murphy
2018-11-28 17:53 ` Stefan Agner
2018-11-28 17:53 ` Stefan Agner
2018-11-28 19:35 ` Robin Murphy
2018-11-28 19:35 ` Robin Murphy
2018-11-29 9:54 ` Stefan Agner
2018-11-29 9:54 ` Stefan Agner
2018-11-28 18:56 ` Trent Piepho [this message]
2018-11-28 18:56 ` Trent Piepho
2018-11-28 19:52 ` Robin Murphy
2018-11-28 19:52 ` Robin Murphy
2018-11-28 20:00 ` Trent Piepho
2018-11-28 20:00 ` Trent Piepho
2018-11-28 18:01 ` Russell King - ARM Linux
2018-11-28 18:01 ` Russell King - ARM Linux
2018-11-29 9:47 ` Stefan Agner
2018-11-29 9:47 ` Stefan Agner
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