* [PATCH linux dev-5.2 v2 1/4] i2c: Aspeed: Add AST2600 compatible
2019-09-13 16:15 [PATCH linux dev-5.2 v2 0/4] Aspeed: I2C: Add support for AST2600 Eddie James
@ 2019-09-13 16:15 ` Eddie James
2019-09-13 16:15 ` [PATCH linux dev-5.2 v2 2/4] i2c: Aspeed: Avoid invalid resource warning for byte mode Eddie James
` (2 subsequent siblings)
3 siblings, 0 replies; 10+ messages in thread
From: Eddie James @ 2019-09-13 16:15 UTC (permalink / raw)
To: openbmc; +Cc: joel, andrew, Eddie James
The driver default behavior works with the AST2600. We need a new
compatible though to make sure the driver doesn't enable AST2400 or
AST2500 behavior.
Signed-off-by: Eddie James <eajames@linux.ibm.com>
---
drivers/i2c/busses/i2c-aspeed.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/i2c/busses/i2c-aspeed.c b/drivers/i2c/busses/i2c-aspeed.c
index 8931792..1943977 100644
--- a/drivers/i2c/busses/i2c-aspeed.c
+++ b/drivers/i2c/busses/i2c-aspeed.c
@@ -1274,6 +1274,10 @@ static int aspeed_i2c_reset(struct aspeed_i2c_bus *bus)
.compatible = "aspeed,ast2500-i2c-bus",
.data = aspeed_i2c_25xx_get_clk_reg_val,
},
+ {
+ .compatible = "aspeed,ast2600-i2c-bus",
+ .data = aspeed_i2c_25xx_get_clk_reg_val,
+ },
{ },
};
MODULE_DEVICE_TABLE(of, aspeed_i2c_bus_of_table);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH linux dev-5.2 v2 2/4] i2c: Aspeed: Avoid invalid resource warning for byte mode
2019-09-13 16:15 [PATCH linux dev-5.2 v2 0/4] Aspeed: I2C: Add support for AST2600 Eddie James
2019-09-13 16:15 ` [PATCH linux dev-5.2 v2 1/4] i2c: Aspeed: Add AST2600 compatible Eddie James
@ 2019-09-13 16:15 ` Eddie James
2019-09-13 16:15 ` [PATCH linux dev-5.2 v2 3/4] ARM: dts: Aspeed: ast2600: Add I2C busses Eddie James
2019-09-13 16:15 ` [PATCH linux dev-5.2 v2 4/4] ARM: dts: Aspeed: Tacoma: Enable " Eddie James
3 siblings, 0 replies; 10+ messages in thread
From: Eddie James @ 2019-09-13 16:15 UTC (permalink / raw)
To: openbmc; +Cc: joel, andrew, Eddie James
If the Aspeed I2C busses don't have the buffer memory specified in the
devicetree, the probe function will throw a warning for non-AST2500
SOCs. This is unnecessary and confusing since operating in byte mode
is perfectly valid. Avoid this by checking the resource pointer before
attempting to map it.
Signed-off-by: Eddie James <eajames@linux.ibm.com>
---
drivers/i2c/busses/i2c-aspeed.c | 24 +++++++++++++-----------
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/drivers/i2c/busses/i2c-aspeed.c b/drivers/i2c/busses/i2c-aspeed.c
index 1943977..464c86a 100644
--- a/drivers/i2c/busses/i2c-aspeed.c
+++ b/drivers/i2c/busses/i2c-aspeed.c
@@ -1393,17 +1393,19 @@ static int aspeed_i2c_probe_bus(struct platform_device *pdev)
struct resource *res = platform_get_resource(pdev,
IORESOURCE_MEM, 1);
- bus->buf_base = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(bus->buf_base) || resource_size(res) < 2) {
- bus->buf_base = NULL;
- } else {
- bus->buf_size = resource_size(res);
- if (of_device_is_compatible(pdev->dev.of_node,
- "aspeed,ast2400-i2c-bus")) {
- bus->buf_page = ((res->start >> 8) &
- GENMASK(3, 0)) - 8;
- bus->buf_offset = (res->start >> 2) &
- ASPEED_I2CD_BUF_OFFSET_MASK;
+ if (res) {
+ bus->buf_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(bus->buf_base) || resource_size(res) < 2) {
+ bus->buf_base = NULL;
+ } else {
+ bus->buf_size = resource_size(res);
+ if (of_device_is_compatible(pdev->dev.of_node,
+ "aspeed,ast2400-i2c-bus")) {
+ bus->buf_page = ((res->start >> 8) &
+ GENMASK(3, 0)) - 8;
+ bus->buf_offset = (res->start >> 2) &
+ ASPEED_I2CD_BUF_OFFSET_MASK;
+ }
}
}
}
--
1.8.3.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH linux dev-5.2 v2 3/4] ARM: dts: Aspeed: ast2600: Add I2C busses
2019-09-13 16:15 [PATCH linux dev-5.2 v2 0/4] Aspeed: I2C: Add support for AST2600 Eddie James
2019-09-13 16:15 ` [PATCH linux dev-5.2 v2 1/4] i2c: Aspeed: Add AST2600 compatible Eddie James
2019-09-13 16:15 ` [PATCH linux dev-5.2 v2 2/4] i2c: Aspeed: Avoid invalid resource warning for byte mode Eddie James
@ 2019-09-13 16:15 ` Eddie James
2019-09-18 10:18 ` Cédric Le Goater
2019-09-13 16:15 ` [PATCH linux dev-5.2 v2 4/4] ARM: dts: Aspeed: Tacoma: Enable " Eddie James
3 siblings, 1 reply; 10+ messages in thread
From: Eddie James @ 2019-09-13 16:15 UTC (permalink / raw)
To: openbmc; +Cc: joel, andrew, Eddie James
Add all the I2C busses to the AST2600 dtsi and set their required
properties.
Signed-off-by: Eddie James <eajames@linux.ibm.com>
---
arch/arm/boot/dts/aspeed-g6.dtsi | 272 +++++++++++++++++++++++++++++++++++++++
1 file changed, 272 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index f3edcff..916503a 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -12,6 +12,22 @@
interrupt-parent = <&gic>;
aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c7;
+ i2c8 = &i2c8;
+ i2c9 = &i2c9;
+ i2c10 = &i2c10;
+ i2c11 = &i2c11;
+ i2c12 = &i2c12;
+ i2c13 = &i2c13;
+ i2c14 = &i2c14;
+ i2c15 = &i2c15;
serial4 = &uart5;
};
@@ -281,6 +297,262 @@
};
};
+ i2c0: i2c-bus@1e78a080 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+
+ reg = <0x1e78a080 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB1>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ bus-frequency = <100000>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ status = "disabled";
+ };
+
+ i2c1: i2c-bus@1e78a100 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+
+ reg = <0x1e78a100 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB1>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ bus-frequency = <100000>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2_default>;
+ status = "disabled";
+ };
+
+ i2c2: i2c-bus@1e78a180 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+
+ reg = <0x1e78a180 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB1>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ bus-frequency = <100000>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3_default>;
+ status = "disabled";
+ };
+
+ i2c3: i2c-bus@1e78a200 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+
+ reg = <0x1e78a200 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB1>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ bus-frequency = <100000>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4_default>;
+ status = "disabled";
+ };
+
+ i2c4: i2c-bus@1e78a280 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+
+ reg = <0x1e78a280 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB1>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ bus-frequency = <100000>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c5_default>;
+ status = "disabled";
+ };
+
+ i2c5: i2c-bus@1e78a300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+
+ reg = <0x1e78a300 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB1>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ bus-frequency = <100000>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c6_default>;
+ status = "disabled";
+ };
+
+ i2c6: i2c-bus@1e78a380 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+
+ reg = <0x1e78a380 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB1>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ bus-frequency = <100000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c7_default>;
+ status = "disabled";
+ };
+
+ i2c7: i2c-bus@1e78a400 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+
+ reg = <0x1e78a400 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB1>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ bus-frequency = <100000>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c8_default>;
+ status = "disabled";
+ };
+
+ i2c8: i2c-bus@1e78a480 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+
+ reg = <0x1e78a480 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB1>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ bus-frequency = <100000>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c9_default>;
+ status = "disabled";
+ };
+
+ i2c9: i2c-bus@1e78a500 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+
+ reg = <0x1e78a500 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB1>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ bus-frequency = <100000>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c10_default>;
+ status = "disabled";
+ };
+
+ i2c10: i2c-bus@1e78a580 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+
+ reg = <0x1e78a580 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB1>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ bus-frequency = <100000>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c11_default>;
+ status = "disabled";
+ };
+
+ i2c11: i2c-bus@1e78a600 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+
+ reg = <0x1e78a600 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB1>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ bus-frequency = <100000>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c12_default>;
+ status = "disabled";
+ };
+
+ i2c12: i2c-bus@1e78a680 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+
+ reg = <0x1e78a680 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB1>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ bus-frequency = <100000>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c13_default>;
+ status = "disabled";
+ };
+
+ i2c13: i2c-bus@1e78a700 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+
+ reg = <0x1e78a700 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB1>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ bus-frequency = <100000>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c14_default>;
+ status = "disabled";
+ };
+
+ i2c14: i2c-bus@1e78a780 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+
+ reg = <0x1e78a780 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB1>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ bus-frequency = <100000>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c15_default>;
+ status = "disabled";
+ };
+
+ i2c15: i2c-bus@1e78a800 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+
+ reg = <0x1e78a800 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB1>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ bus-frequency = <100000>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c16_default>;
+ status = "disabled";
+ };
+
fsim0: fsi@1e79b000 {
compatible = "aspeed,ast2600-fsi-master", "fsi-master";
reg = <0x1e79b000 0x94>;
--
1.8.3.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH linux dev-5.2 v2 3/4] ARM: dts: Aspeed: ast2600: Add I2C busses
2019-09-13 16:15 ` [PATCH linux dev-5.2 v2 3/4] ARM: dts: Aspeed: ast2600: Add I2C busses Eddie James
@ 2019-09-18 10:18 ` Cédric Le Goater
2019-09-18 14:53 ` Eddie James
0 siblings, 1 reply; 10+ messages in thread
From: Cédric Le Goater @ 2019-09-18 10:18 UTC (permalink / raw)
To: Eddie James, openbmc; +Cc: andrew, Joel Stanley
On 13/09/2019 18:15, Eddie James wrote:
> Add all the I2C busses to the AST2600 dtsi and set their required
> properties.
>
The DT defines an interrupt per I2C bus but this is not how the I2C
driver operates. It still uses the old mode from the Aspeed AST2500.
C.
> Signed-off-by: Eddie James <eajames@linux.ibm.com>
> ---
> arch/arm/boot/dts/aspeed-g6.dtsi | 272 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 272 insertions(+)
>
> diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
> index f3edcff..916503a 100644
> --- a/arch/arm/boot/dts/aspeed-g6.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g6.dtsi
> @@ -12,6 +12,22 @@
> interrupt-parent = <&gic>;
>
> aliases {
> + i2c0 = &i2c0;
> + i2c1 = &i2c1;
> + i2c2 = &i2c2;
> + i2c3 = &i2c3;
> + i2c4 = &i2c4;
> + i2c5 = &i2c5;
> + i2c6 = &i2c6;
> + i2c7 = &i2c7;
> + i2c8 = &i2c8;
> + i2c9 = &i2c9;
> + i2c10 = &i2c10;
> + i2c11 = &i2c11;
> + i2c12 = &i2c12;
> + i2c13 = &i2c13;
> + i2c14 = &i2c14;
> + i2c15 = &i2c15;
> serial4 = &uart5;
> };
>
> @@ -281,6 +297,262 @@
> };
> };
>
> + i2c0: i2c-bus@1e78a080 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + #interrupt-cells = <1>;
> +
> + reg = <0x1e78a080 0x80>;
> + compatible = "aspeed,ast2600-i2c-bus";
> + clocks = <&syscon ASPEED_CLK_APB1>;
> + resets = <&syscon ASPEED_RESET_I2C>;
> + bus-frequency = <100000>;
> + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c1_default>;
> + status = "disabled";
> + };
> +
> + i2c1: i2c-bus@1e78a100 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + #interrupt-cells = <1>;
> +
> + reg = <0x1e78a100 0x80>;
> + compatible = "aspeed,ast2600-i2c-bus";
> + clocks = <&syscon ASPEED_CLK_APB1>;
> + resets = <&syscon ASPEED_RESET_I2C>;
> + bus-frequency = <100000>;
> + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c2_default>;
> + status = "disabled";
> + };
> +
> + i2c2: i2c-bus@1e78a180 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + #interrupt-cells = <1>;
> +
> + reg = <0x1e78a180 0x80>;
> + compatible = "aspeed,ast2600-i2c-bus";
> + clocks = <&syscon ASPEED_CLK_APB1>;
> + resets = <&syscon ASPEED_RESET_I2C>;
> + bus-frequency = <100000>;
> + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c3_default>;
> + status = "disabled";
> + };
> +
> + i2c3: i2c-bus@1e78a200 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + #interrupt-cells = <1>;
> +
> + reg = <0x1e78a200 0x80>;
> + compatible = "aspeed,ast2600-i2c-bus";
> + clocks = <&syscon ASPEED_CLK_APB1>;
> + resets = <&syscon ASPEED_RESET_I2C>;
> + bus-frequency = <100000>;
> + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c4_default>;
> + status = "disabled";
> + };
> +
> + i2c4: i2c-bus@1e78a280 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + #interrupt-cells = <1>;
> +
> + reg = <0x1e78a280 0x80>;
> + compatible = "aspeed,ast2600-i2c-bus";
> + clocks = <&syscon ASPEED_CLK_APB1>;
> + resets = <&syscon ASPEED_RESET_I2C>;
> + bus-frequency = <100000>;
> + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c5_default>;
> + status = "disabled";
> + };
> +
> + i2c5: i2c-bus@1e78a300 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + #interrupt-cells = <1>;
> +
> + reg = <0x1e78a300 0x80>;
> + compatible = "aspeed,ast2600-i2c-bus";
> + clocks = <&syscon ASPEED_CLK_APB1>;
> + resets = <&syscon ASPEED_RESET_I2C>;
> + bus-frequency = <100000>;
> + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c6_default>;
> + status = "disabled";
> + };
> +
> + i2c6: i2c-bus@1e78a380 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + #interrupt-cells = <1>;
> +
> + reg = <0x1e78a380 0x80>;
> + compatible = "aspeed,ast2600-i2c-bus";
> + clocks = <&syscon ASPEED_CLK_APB1>;
> + resets = <&syscon ASPEED_RESET_I2C>;
> + bus-frequency = <100000>;
> + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c7_default>;
> + status = "disabled";
> + };
> +
> + i2c7: i2c-bus@1e78a400 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + #interrupt-cells = <1>;
> +
> + reg = <0x1e78a400 0x80>;
> + compatible = "aspeed,ast2600-i2c-bus";
> + clocks = <&syscon ASPEED_CLK_APB1>;
> + resets = <&syscon ASPEED_RESET_I2C>;
> + bus-frequency = <100000>;
> + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c8_default>;
> + status = "disabled";
> + };
> +
> + i2c8: i2c-bus@1e78a480 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + #interrupt-cells = <1>;
> +
> + reg = <0x1e78a480 0x80>;
> + compatible = "aspeed,ast2600-i2c-bus";
> + clocks = <&syscon ASPEED_CLK_APB1>;
> + resets = <&syscon ASPEED_RESET_I2C>;
> + bus-frequency = <100000>;
> + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c9_default>;
> + status = "disabled";
> + };
> +
> + i2c9: i2c-bus@1e78a500 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + #interrupt-cells = <1>;
> +
> + reg = <0x1e78a500 0x80>;
> + compatible = "aspeed,ast2600-i2c-bus";
> + clocks = <&syscon ASPEED_CLK_APB1>;
> + resets = <&syscon ASPEED_RESET_I2C>;
> + bus-frequency = <100000>;
> + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c10_default>;
> + status = "disabled";
> + };
> +
> + i2c10: i2c-bus@1e78a580 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + #interrupt-cells = <1>;
> +
> + reg = <0x1e78a580 0x80>;
> + compatible = "aspeed,ast2600-i2c-bus";
> + clocks = <&syscon ASPEED_CLK_APB1>;
> + resets = <&syscon ASPEED_RESET_I2C>;
> + bus-frequency = <100000>;
> + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c11_default>;
> + status = "disabled";
> + };
> +
> + i2c11: i2c-bus@1e78a600 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + #interrupt-cells = <1>;
> +
> + reg = <0x1e78a600 0x80>;
> + compatible = "aspeed,ast2600-i2c-bus";
> + clocks = <&syscon ASPEED_CLK_APB1>;
> + resets = <&syscon ASPEED_RESET_I2C>;
> + bus-frequency = <100000>;
> + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c12_default>;
> + status = "disabled";
> + };
> +
> + i2c12: i2c-bus@1e78a680 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + #interrupt-cells = <1>;
> +
> + reg = <0x1e78a680 0x80>;
> + compatible = "aspeed,ast2600-i2c-bus";
> + clocks = <&syscon ASPEED_CLK_APB1>;
> + resets = <&syscon ASPEED_RESET_I2C>;
> + bus-frequency = <100000>;
> + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c13_default>;
> + status = "disabled";
> + };
> +
> + i2c13: i2c-bus@1e78a700 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + #interrupt-cells = <1>;
> +
> + reg = <0x1e78a700 0x80>;
> + compatible = "aspeed,ast2600-i2c-bus";
> + clocks = <&syscon ASPEED_CLK_APB1>;
> + resets = <&syscon ASPEED_RESET_I2C>;
> + bus-frequency = <100000>;
> + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c14_default>;
> + status = "disabled";
> + };
> +
> + i2c14: i2c-bus@1e78a780 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + #interrupt-cells = <1>;
> +
> + reg = <0x1e78a780 0x80>;
> + compatible = "aspeed,ast2600-i2c-bus";
> + clocks = <&syscon ASPEED_CLK_APB1>;
> + resets = <&syscon ASPEED_RESET_I2C>;
> + bus-frequency = <100000>;
> + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c15_default>;
> + status = "disabled";
> + };
> +
> + i2c15: i2c-bus@1e78a800 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + #interrupt-cells = <1>;
> +
> + reg = <0x1e78a800 0x80>;
> + compatible = "aspeed,ast2600-i2c-bus";
> + clocks = <&syscon ASPEED_CLK_APB1>;
> + resets = <&syscon ASPEED_RESET_I2C>;
> + bus-frequency = <100000>;
> + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c16_default>;
> + status = "disabled";
> + };
> +
> fsim0: fsi@1e79b000 {
> compatible = "aspeed,ast2600-fsi-master", "fsi-master";
> reg = <0x1e79b000 0x94>;
>
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH linux dev-5.2 v2 3/4] ARM: dts: Aspeed: ast2600: Add I2C busses
2019-09-18 10:18 ` Cédric Le Goater
@ 2019-09-18 14:53 ` Eddie James
2019-09-18 15:57 ` Cédric Le Goater
0 siblings, 1 reply; 10+ messages in thread
From: Eddie James @ 2019-09-18 14:53 UTC (permalink / raw)
To: Cédric Le Goater, openbmc; +Cc: andrew
On 9/18/19 5:18 AM, Cédric Le Goater wrote:
> On 13/09/2019 18:15, Eddie James wrote:
>> Add all the I2C busses to the AST2600 dtsi and set their required
>> properties.
>>
> The DT defines an interrupt per I2C bus but this is not how the I2C
> driver operates. It still uses the old mode from the Aspeed AST2500.
Oh? The I2C interrupt controller driver is a separate driver, which I
didn't include a node for in the AST2600 dts. As far as I can tell the
I2C bus driver just asks for it's interrupt and uses it, so by setting
each bus to it's GIC interrupt line (instead of the line from the I2C
interrupt controller like in the AST2500), the I2C driver receives the
correct interrupt.
Thanks,
Eddie
>
> C.
>
>
>> Signed-off-by: Eddie James <eajames@linux.ibm.com>
>> ---
>> arch/arm/boot/dts/aspeed-g6.dtsi | 272 +++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 272 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
>> index f3edcff..916503a 100644
>> --- a/arch/arm/boot/dts/aspeed-g6.dtsi
>> +++ b/arch/arm/boot/dts/aspeed-g6.dtsi
>> @@ -12,6 +12,22 @@
>> interrupt-parent = <&gic>;
>>
>> aliases {
>> + i2c0 = &i2c0;
>> + i2c1 = &i2c1;
>> + i2c2 = &i2c2;
>> + i2c3 = &i2c3;
>> + i2c4 = &i2c4;
>> + i2c5 = &i2c5;
>> + i2c6 = &i2c6;
>> + i2c7 = &i2c7;
>> + i2c8 = &i2c8;
>> + i2c9 = &i2c9;
>> + i2c10 = &i2c10;
>> + i2c11 = &i2c11;
>> + i2c12 = &i2c12;
>> + i2c13 = &i2c13;
>> + i2c14 = &i2c14;
>> + i2c15 = &i2c15;
>> serial4 = &uart5;
>> };
>>
>> @@ -281,6 +297,262 @@
>> };
>> };
>>
>> + i2c0: i2c-bus@1e78a080 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + #interrupt-cells = <1>;
>> +
>> + reg = <0x1e78a080 0x80>;
>> + compatible = "aspeed,ast2600-i2c-bus";
>> + clocks = <&syscon ASPEED_CLK_APB1>;
>> + resets = <&syscon ASPEED_RESET_I2C>;
>> + bus-frequency = <100000>;
>> + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c1_default>;
>> + status = "disabled";
>> + };
>> +
>> + i2c1: i2c-bus@1e78a100 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + #interrupt-cells = <1>;
>> +
>> + reg = <0x1e78a100 0x80>;
>> + compatible = "aspeed,ast2600-i2c-bus";
>> + clocks = <&syscon ASPEED_CLK_APB1>;
>> + resets = <&syscon ASPEED_RESET_I2C>;
>> + bus-frequency = <100000>;
>> + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c2_default>;
>> + status = "disabled";
>> + };
>> +
>> + i2c2: i2c-bus@1e78a180 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + #interrupt-cells = <1>;
>> +
>> + reg = <0x1e78a180 0x80>;
>> + compatible = "aspeed,ast2600-i2c-bus";
>> + clocks = <&syscon ASPEED_CLK_APB1>;
>> + resets = <&syscon ASPEED_RESET_I2C>;
>> + bus-frequency = <100000>;
>> + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c3_default>;
>> + status = "disabled";
>> + };
>> +
>> + i2c3: i2c-bus@1e78a200 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + #interrupt-cells = <1>;
>> +
>> + reg = <0x1e78a200 0x80>;
>> + compatible = "aspeed,ast2600-i2c-bus";
>> + clocks = <&syscon ASPEED_CLK_APB1>;
>> + resets = <&syscon ASPEED_RESET_I2C>;
>> + bus-frequency = <100000>;
>> + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c4_default>;
>> + status = "disabled";
>> + };
>> +
>> + i2c4: i2c-bus@1e78a280 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + #interrupt-cells = <1>;
>> +
>> + reg = <0x1e78a280 0x80>;
>> + compatible = "aspeed,ast2600-i2c-bus";
>> + clocks = <&syscon ASPEED_CLK_APB1>;
>> + resets = <&syscon ASPEED_RESET_I2C>;
>> + bus-frequency = <100000>;
>> + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c5_default>;
>> + status = "disabled";
>> + };
>> +
>> + i2c5: i2c-bus@1e78a300 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + #interrupt-cells = <1>;
>> +
>> + reg = <0x1e78a300 0x80>;
>> + compatible = "aspeed,ast2600-i2c-bus";
>> + clocks = <&syscon ASPEED_CLK_APB1>;
>> + resets = <&syscon ASPEED_RESET_I2C>;
>> + bus-frequency = <100000>;
>> + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c6_default>;
>> + status = "disabled";
>> + };
>> +
>> + i2c6: i2c-bus@1e78a380 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + #interrupt-cells = <1>;
>> +
>> + reg = <0x1e78a380 0x80>;
>> + compatible = "aspeed,ast2600-i2c-bus";
>> + clocks = <&syscon ASPEED_CLK_APB1>;
>> + resets = <&syscon ASPEED_RESET_I2C>;
>> + bus-frequency = <100000>;
>> + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c7_default>;
>> + status = "disabled";
>> + };
>> +
>> + i2c7: i2c-bus@1e78a400 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + #interrupt-cells = <1>;
>> +
>> + reg = <0x1e78a400 0x80>;
>> + compatible = "aspeed,ast2600-i2c-bus";
>> + clocks = <&syscon ASPEED_CLK_APB1>;
>> + resets = <&syscon ASPEED_RESET_I2C>;
>> + bus-frequency = <100000>;
>> + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c8_default>;
>> + status = "disabled";
>> + };
>> +
>> + i2c8: i2c-bus@1e78a480 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + #interrupt-cells = <1>;
>> +
>> + reg = <0x1e78a480 0x80>;
>> + compatible = "aspeed,ast2600-i2c-bus";
>> + clocks = <&syscon ASPEED_CLK_APB1>;
>> + resets = <&syscon ASPEED_RESET_I2C>;
>> + bus-frequency = <100000>;
>> + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c9_default>;
>> + status = "disabled";
>> + };
>> +
>> + i2c9: i2c-bus@1e78a500 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + #interrupt-cells = <1>;
>> +
>> + reg = <0x1e78a500 0x80>;
>> + compatible = "aspeed,ast2600-i2c-bus";
>> + clocks = <&syscon ASPEED_CLK_APB1>;
>> + resets = <&syscon ASPEED_RESET_I2C>;
>> + bus-frequency = <100000>;
>> + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c10_default>;
>> + status = "disabled";
>> + };
>> +
>> + i2c10: i2c-bus@1e78a580 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + #interrupt-cells = <1>;
>> +
>> + reg = <0x1e78a580 0x80>;
>> + compatible = "aspeed,ast2600-i2c-bus";
>> + clocks = <&syscon ASPEED_CLK_APB1>;
>> + resets = <&syscon ASPEED_RESET_I2C>;
>> + bus-frequency = <100000>;
>> + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c11_default>;
>> + status = "disabled";
>> + };
>> +
>> + i2c11: i2c-bus@1e78a600 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + #interrupt-cells = <1>;
>> +
>> + reg = <0x1e78a600 0x80>;
>> + compatible = "aspeed,ast2600-i2c-bus";
>> + clocks = <&syscon ASPEED_CLK_APB1>;
>> + resets = <&syscon ASPEED_RESET_I2C>;
>> + bus-frequency = <100000>;
>> + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c12_default>;
>> + status = "disabled";
>> + };
>> +
>> + i2c12: i2c-bus@1e78a680 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + #interrupt-cells = <1>;
>> +
>> + reg = <0x1e78a680 0x80>;
>> + compatible = "aspeed,ast2600-i2c-bus";
>> + clocks = <&syscon ASPEED_CLK_APB1>;
>> + resets = <&syscon ASPEED_RESET_I2C>;
>> + bus-frequency = <100000>;
>> + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c13_default>;
>> + status = "disabled";
>> + };
>> +
>> + i2c13: i2c-bus@1e78a700 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + #interrupt-cells = <1>;
>> +
>> + reg = <0x1e78a700 0x80>;
>> + compatible = "aspeed,ast2600-i2c-bus";
>> + clocks = <&syscon ASPEED_CLK_APB1>;
>> + resets = <&syscon ASPEED_RESET_I2C>;
>> + bus-frequency = <100000>;
>> + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c14_default>;
>> + status = "disabled";
>> + };
>> +
>> + i2c14: i2c-bus@1e78a780 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + #interrupt-cells = <1>;
>> +
>> + reg = <0x1e78a780 0x80>;
>> + compatible = "aspeed,ast2600-i2c-bus";
>> + clocks = <&syscon ASPEED_CLK_APB1>;
>> + resets = <&syscon ASPEED_RESET_I2C>;
>> + bus-frequency = <100000>;
>> + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c15_default>;
>> + status = "disabled";
>> + };
>> +
>> + i2c15: i2c-bus@1e78a800 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + #interrupt-cells = <1>;
>> +
>> + reg = <0x1e78a800 0x80>;
>> + compatible = "aspeed,ast2600-i2c-bus";
>> + clocks = <&syscon ASPEED_CLK_APB1>;
>> + resets = <&syscon ASPEED_RESET_I2C>;
>> + bus-frequency = <100000>;
>> + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c16_default>;
>> + status = "disabled";
>> + };
>> +
>> fsim0: fsi@1e79b000 {
>> compatible = "aspeed,ast2600-fsi-master", "fsi-master";
>> reg = <0x1e79b000 0x94>;
>>
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH linux dev-5.2 v2 3/4] ARM: dts: Aspeed: ast2600: Add I2C busses
2019-09-18 14:53 ` Eddie James
@ 2019-09-18 15:57 ` Cédric Le Goater
2019-09-18 17:02 ` Cédric Le Goater
0 siblings, 1 reply; 10+ messages in thread
From: Cédric Le Goater @ 2019-09-18 15:57 UTC (permalink / raw)
To: Eddie James, openbmc; +Cc: andrew
On 18/09/2019 16:53, Eddie James wrote:
>
> On 9/18/19 5:18 AM, Cédric Le Goater wrote:
>> On 13/09/2019 18:15, Eddie James wrote:
>>> Add all the I2C busses to the AST2600 dtsi and set their required
>>> properties.
>>>
>> The DT defines an interrupt per I2C bus but this is not how the I2C
>> driver operates. It still uses the old mode from the Aspeed AST2500.
>
>
> Oh? The I2C interrupt controller driver is a separate driver, which I didn't include a node for in the AST2600 dts. As far as I can tell the I2C bus driver just asks for it's interrupt and uses it, so by setting each bus to it's GIC interrupt line (instead of the line from the I2C interrupt controller like in the AST2500), the I2C driver receives the correct interrupt.
ok. I am seeing this from the I2C model side and that is where the
problem must be. I will dig in QEMU.
Thanks,
C.
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH linux dev-5.2 v2 3/4] ARM: dts: Aspeed: ast2600: Add I2C busses
2019-09-18 15:57 ` Cédric Le Goater
@ 2019-09-18 17:02 ` Cédric Le Goater
2019-09-19 0:34 ` Ryan Chen
0 siblings, 1 reply; 10+ messages in thread
From: Cédric Le Goater @ 2019-09-18 17:02 UTC (permalink / raw)
To: Eddie James, openbmc; +Cc: andrew
On 18/09/2019 17:57, Cédric Le Goater wrote:
> On 18/09/2019 16:53, Eddie James wrote:
>>
>> On 9/18/19 5:18 AM, Cédric Le Goater wrote:
>>> On 13/09/2019 18:15, Eddie James wrote:
>>>> Add all the I2C busses to the AST2600 dtsi and set their required
>>>> properties.
>>>>
>>> The DT defines an interrupt per I2C bus but this is not how the I2C
>>> driver operates. It still uses the old mode from the Aspeed AST2500.
>>
>>
>> Oh? The I2C interrupt controller driver is a separate driver, which I didn't include a node for in the AST2600 dts. As far as I can tell the I2C bus driver just asks for it's interrupt and uses it, so by setting each bus to it's GIC interrupt line (instead of the line from the I2C interrupt controller like in the AST2500), the I2C driver receives the correct interrupt.
>
> ok. I am seeing this from the I2C model side and that is where the
> problem must be. I will dig in QEMU.
We now have one irq per bus and the I2C model needs some rework for
the AST2600 because we only had one with the previous Aspeed SoC.
Are you sure of the I2C IRQ number range ? Shouldn't we using range
142-157 instead ?
Thanks,
C.
^ permalink raw reply [flat|nested] 10+ messages in thread
* RE: [PATCH linux dev-5.2 v2 3/4] ARM: dts: Aspeed: ast2600: Add I2C busses
2019-09-18 17:02 ` Cédric Le Goater
@ 2019-09-19 0:34 ` Ryan Chen
0 siblings, 0 replies; 10+ messages in thread
From: Ryan Chen @ 2019-09-19 0:34 UTC (permalink / raw)
To: Cédric Le Goater, Eddie James, openbmc@lists.ozlabs.org
Cc: andrew@aj.id.au
Hello,
It is correct, the AST2600 IRQ number range is from GIC_SPI 110 ~125.
-----Original Message-----
From: openbmc [mailto:openbmc-bounces+ryan_chen=aspeedtech.com@lists.ozlabs.org] On Behalf Of Cedric Le Goater
Sent: Thursday, September 19, 2019 1:02 AM
To: Eddie James <eajames@linux.ibm.com>; openbmc@lists.ozlabs.org
Cc: andrew@aj.id.au
Subject: Re: [PATCH linux dev-5.2 v2 3/4] ARM: dts: Aspeed: ast2600: Add I2C busses
On 18/09/2019 17:57, Cédric Le Goater wrote:
> On 18/09/2019 16:53, Eddie James wrote:
>>
>> On 9/18/19 5:18 AM, Cédric Le Goater wrote:
>>> On 13/09/2019 18:15, Eddie James wrote:
>>>> Add all the I2C busses to the AST2600 dtsi and set their required
>>>> properties.
>>>>
>>> The DT defines an interrupt per I2C bus but this is not how the I2C
>>> driver operates. It still uses the old mode from the Aspeed AST2500.
>>
>>
>> Oh? The I2C interrupt controller driver is a separate driver, which I didn't include a node for in the AST2600 dts. As far as I can tell the I2C bus driver just asks for it's interrupt and uses it, so by setting each bus to it's GIC interrupt line (instead of the line from the I2C interrupt controller like in the AST2500), the I2C driver receives the correct interrupt.
>
> ok. I am seeing this from the I2C model side and that is where the
> problem must be. I will dig in QEMU.
We now have one irq per bus and the I2C model needs some rework for the AST2600 because we only had one with the previous Aspeed SoC.
Are you sure of the I2C IRQ number range ? Shouldn't we using range
142-157 instead ?
Thanks,
C.
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH linux dev-5.2 v2 4/4] ARM: dts: Aspeed: Tacoma: Enable I2C busses
2019-09-13 16:15 [PATCH linux dev-5.2 v2 0/4] Aspeed: I2C: Add support for AST2600 Eddie James
` (2 preceding siblings ...)
2019-09-13 16:15 ` [PATCH linux dev-5.2 v2 3/4] ARM: dts: Aspeed: ast2600: Add I2C busses Eddie James
@ 2019-09-13 16:15 ` Eddie James
3 siblings, 0 replies; 10+ messages in thread
From: Eddie James @ 2019-09-13 16:15 UTC (permalink / raw)
To: openbmc; +Cc: joel, andrew, Eddie James
Enable all the I2C busses on Tacoma and add the I2C slave devices that
exist on the busses.
Signed-off-by: Eddie James <eajames@linux.ibm.com>
---
arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 384 ++++++++++++++++++++++++++++
1 file changed, 384 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts
index 0a38bc0..408af00 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts
@@ -3,6 +3,7 @@
/dts-v1/;
#include "aspeed-g6.dtsi"
+#include <dt-bindings/leds/leds-pca955x.h>
/ {
model = "Tacoma";
@@ -37,3 +38,386 @@
&fsim0 {
status = "okay";
};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+
+ bmp: bmp280@77 {
+ compatible = "bosch,bmp280";
+ reg = <0x77>;
+ #io-channel-cells = <1>;
+ };
+
+ max31785@52 {
+ compatible = "maxim,max31785a";
+ reg = <0x52>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fan@0 {
+ compatible = "pmbus-fan";
+ reg = <0>;
+ tach-pulses = <2>;
+ maxim,fan-rotor-input = "tach";
+ maxim,fan-pwm-freq = <25000>;
+ maxim,fan-dual-tach;
+ maxim,fan-no-watchdog;
+ maxim,fan-no-fault-ramp;
+ maxim,fan-ramp = <2>;
+ maxim,fan-fault-pin-mon;
+ };
+
+ fan@1 {
+ compatible = "pmbus-fan";
+ reg = <1>;
+ tach-pulses = <2>;
+ maxim,fan-rotor-input = "tach";
+ maxim,fan-pwm-freq = <25000>;
+ maxim,fan-dual-tach;
+ maxim,fan-no-watchdog;
+ maxim,fan-no-fault-ramp;
+ maxim,fan-ramp = <2>;
+ maxim,fan-fault-pin-mon;
+ };
+
+ fan@2 {
+ compatible = "pmbus-fan";
+ reg = <2>;
+ tach-pulses = <2>;
+ maxim,fan-rotor-input = "tach";
+ maxim,fan-pwm-freq = <25000>;
+ maxim,fan-dual-tach;
+ maxim,fan-no-watchdog;
+ maxim,fan-no-fault-ramp;
+ maxim,fan-ramp = <2>;
+ maxim,fan-fault-pin-mon;
+ };
+
+ fan@3 {
+ compatible = "pmbus-fan";
+ reg = <3>;
+ tach-pulses = <2>;
+ maxim,fan-rotor-input = "tach";
+ maxim,fan-pwm-freq = <25000>;
+ maxim,fan-dual-tach;
+ maxim,fan-no-watchdog;
+ maxim,fan-no-fault-ramp;
+ maxim,fan-ramp = <2>;
+ maxim,fan-fault-pin-mon;
+ };
+ };
+
+ dps: dps310@76 {
+ compatible = "infineon,dps310";
+ reg = <0x76>;
+ #io-channel-cells = <0>;
+ };
+
+ pca0: pca9552@60 {
+ compatible = "nxp,pca9552";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio@0 {
+ reg = <0>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@1 {
+ reg = <1>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@8 {
+ reg = <8>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@9 {
+ reg = <9>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@10 {
+ reg = <10>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@11 {
+ reg = <11>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@12 {
+ reg = <12>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@13 {
+ reg = <13>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@14 {
+ reg = <14>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@15 {
+ reg = <15>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
+
+ power-supply@68 {
+ compatible = "ibm,cffps1";
+ reg = <0x68>;
+ };
+
+ power-supply@69 {
+ compatible = "ibm,cffps1";
+ reg = <0x69>;
+ };
+};
+
+&i2c4 {
+ status = "okay";
+
+ tmp423a@4c {
+ compatible = "ti,tmp423";
+ reg = <0x4c>;
+ };
+
+ ir35221@70 {
+ compatible = "infineon,ir35221";
+ reg = <0x70>;
+ };
+
+ ir35221@71 {
+ compatible = "infineon,ir35221";
+ reg = <0x71>;
+ };
+};
+
+&i2c5 {
+ status = "okay";
+
+ tmp423a@4c {
+ compatible = "ti,tmp423";
+ reg = <0x4c>;
+ };
+
+ ir35221@70 {
+ compatible = "infineon,ir35221";
+ reg = <0x70>;
+ };
+
+ ir35221@71 {
+ compatible = "infineon,ir35221";
+ reg = <0x71>;
+ };
+};
+
+&i2c6 {
+ status = "okay";
+};
+
+&i2c7 {
+ status = "okay";
+};
+
+&i2c8 {
+ status = "okay";
+};
+
+&i2c9 {
+ status = "okay";
+
+ tmp275@4a {
+ compatible = "ti,tmp275";
+ reg = <0x4a>;
+ };
+};
+
+&i2c10 {
+ status = "okay";
+};
+
+&i2c11 {
+ status = "okay";
+
+ pca9552: pca9552@60 {
+ compatible = "nxp,pca9552";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names = "PS_SMBUS_RESET_N", "APSS_RESET_N",
+ "GPU0_TH_OVERT_N_BUFF", "GPU1_TH_OVERT_N_BUFF",
+ "GPU2_TH_OVERT_N_BUFF", "GPU3_TH_OVERT_N_BUFF",
+ "GPU4_TH_OVERT_N_BUFF", "GPU5_TH_OVERT_N_BUFF",
+ "GPU0_PWR_GOOD_BUFF", "GPU1_PWR_GOOD_BUFF",
+ "GPU2_PWR_GOOD_BUFF", "GPU3_PWR_GOOD_BUFF",
+ "GPU4_PWR_GOOD_BUFF", "GPU5_PWR_GOOD_BUFF",
+ "12V_BREAKER_FLT_N", "THROTTLE_UNLATCHED_N";
+
+ gpio@0 {
+ reg = <0>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@1 {
+ reg = <1>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@8 {
+ reg = <8>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@9 {
+ reg = <9>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@10 {
+ reg = <10>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@11 {
+ reg = <11>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@12 {
+ reg = <12>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@13 {
+ reg = <13>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@14 {
+ reg = <14>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@15 {
+ reg = <15>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
+
+ rtc@32 {
+ compatible = "epson,rx8900";
+ reg = <0x32>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c64";
+ reg = <0x51>;
+ };
+
+ ucd90160@64 {
+ compatible = "ti,ucd90160";
+ reg = <0x64>;
+ };
+};
+
+&i2c12 {
+ status = "okay";
+};
+
+&i2c13 {
+ status = "okay";
+};
+
+&i2c14 {
+ status = "okay";
+};
+
+&i2c15 {
+ status = "okay";
+};
--
1.8.3.1
^ permalink raw reply related [flat|nested] 10+ messages in thread