* [PATCH v6] arm64: dts: qcom: sc7180: Add A618 gpu dt blob
@ 2020-02-10 7:41 ` Sharat Masetty
0 siblings, 0 replies; 10+ messages in thread
From: Sharat Masetty @ 2020-02-10 7:41 UTC (permalink / raw)
To: freedreno, devicetree
Cc: dianders, linux-arm-msm, Sharat Masetty, linux-kernel,
bjorn.andersson, mka, dri-devel
This patch adds the required dt nodes and properties
to enabled A618 GPU.
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 +++++++++++++++++++++++++++++++++++
1 file changed, 102 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index f3fcc5c..63fff15 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -1043,6 +1043,108 @@
};
};
+ gpu: gpu@5000000 {
+ compatible = "qcom,adreno-618.0", "qcom,adreno";
+ #stream-id-cells = <16>;
+ reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
+ <0 0x05061000 0 0x800>;
+ reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&adreno_smmu 0>;
+ operating-points-v2 = <&gpu_opp_table>;
+ qcom,gmu = <&gmu>;
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ };
+
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ opp-565000000 {
+ opp-hz = /bits/ 64 <565000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ opp-430000000 {
+ opp-hz = /bits/ 64 <430000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ opp-355000000 {
+ opp-hz = /bits/ 64 <355000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ opp-267000000 {
+ opp-hz = /bits/ 64 <267000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+
+ opp-180000000 {
+ opp-hz = /bits/ 64 <180000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+ };
+ };
+
+ adreno_smmu: iommu@5040000 {
+ compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2";
+ reg = <0 0x05040000 0 0x10000>;
+ #iommu-cells = <1>;
+ #global-interrupts = <2>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gcc GCC_GPU_CFG_AHB_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>;
+
+ clock-names = "bus", "iface", "mem_iface_clk";
+ power-domains = <&gpucc CX_GDSC>;
+ };
+
+ gmu: gmu@506a000 {
+ compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
+ reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
+ <0 0x0b490000 0 0x10000>;
+ reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hfi", "gmu";
+ clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
+ clock-names = "gmu", "cxo", "axi", "memnoc";
+ power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
+ power-domain-names = "cx", "gx";
+ iommus = <&adreno_smmu 5>;
+ operating-points-v2 = <&gmu_opp_table>;
+
+ gmu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+ };
+ };
+
gpucc: clock-controller@5090000 {
compatible = "qcom,sc7180-gpucc";
reg = <0 0x05090000 0 0x9000>;
--
1.9.1
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v6] arm64: dts: qcom: sc7180: Add A618 gpu dt blob
2020-02-10 7:41 ` Sharat Masetty
@ 2020-02-10 21:21 ` Doug Anderson
-1 siblings, 0 replies; 10+ messages in thread
From: Doug Anderson @ 2020-02-10 21:21 UTC (permalink / raw)
To: Sharat Masetty
Cc: freedreno,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
dri-devel, linux-arm-msm, LKML, Bjorn Andersson, Jordan Crouse,
Matthias Kaehlcke
Hi,
On Sun, Feb 9, 2020 at 11:41 PM Sharat Masetty <smasetty@codeaurora.org> wrote:
>
> This patch adds the required dt nodes and properties
> to enabled A618 GPU.
>
> Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
In v4 I added my tags [1]. Please keep them for future patches unless
something major changes. AKA:
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
> ---
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 +++++++++++++++++++++++++++++++++++
> 1 file changed, 102 insertions(+)
Just to summarize where we are:
* As per my notes in v3 and v4 [1], this can't land until
"mem_iface_clk" is in the bindings. Please post a patch for this and
reply with a link here so others can follow the disucssion.
* This also can't land until the gpucc bindings change from Taniya
recently [2] lands.
...so we're in limbo waiting for the bindings to be resolved, but
otherwise this patch looks good.
[1] https://lore.kernel.org/r/CAD=FV=UEQ0mOXuDrSZrcJ8g6jb0eLf1Ttn+Mn7T6d2TpCMUcuA@mail.gmail.com
[2] https://lore.kernel.org/r/1581307266-26989-1-git-send-email-tdas@codeaurora.org
-Doug
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v6] arm64: dts: qcom: sc7180: Add A618 gpu dt blob
@ 2020-02-10 21:21 ` Doug Anderson
0 siblings, 0 replies; 10+ messages in thread
From: Doug Anderson @ 2020-02-10 21:21 UTC (permalink / raw)
To: Sharat Masetty
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-arm-msm, LKML, Bjorn Andersson, Matthias Kaehlcke,
dri-devel, freedreno
Hi,
On Sun, Feb 9, 2020 at 11:41 PM Sharat Masetty <smasetty@codeaurora.org> wrote:
>
> This patch adds the required dt nodes and properties
> to enabled A618 GPU.
>
> Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
In v4 I added my tags [1]. Please keep them for future patches unless
something major changes. AKA:
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
> ---
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 +++++++++++++++++++++++++++++++++++
> 1 file changed, 102 insertions(+)
Just to summarize where we are:
* As per my notes in v3 and v4 [1], this can't land until
"mem_iface_clk" is in the bindings. Please post a patch for this and
reply with a link here so others can follow the disucssion.
* This also can't land until the gpucc bindings change from Taniya
recently [2] lands.
...so we're in limbo waiting for the bindings to be resolved, but
otherwise this patch looks good.
[1] https://lore.kernel.org/r/CAD=FV=UEQ0mOXuDrSZrcJ8g6jb0eLf1Ttn+Mn7T6d2TpCMUcuA@mail.gmail.com
[2] https://lore.kernel.org/r/1581307266-26989-1-git-send-email-tdas@codeaurora.org
-Doug
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v6] arm64: dts: qcom: sc7180: Add A618 gpu dt blob
2020-02-10 21:21 ` Doug Anderson
@ 2020-02-20 8:20 ` Sharat Masetty
-1 siblings, 0 replies; 10+ messages in thread
From: Sharat Masetty @ 2020-02-20 8:20 UTC (permalink / raw)
To: Doug Anderson
Cc: freedreno,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
dri-devel, linux-arm-msm, LKML, Bjorn Andersson, Jordan Crouse,
Matthias Kaehlcke
On 2/11/2020 2:51 AM, Doug Anderson wrote:
> Hi,
>
> On Sun, Feb 9, 2020 at 11:41 PM Sharat Masetty <smasetty@codeaurora.org> wrote:
>> This patch adds the required dt nodes and properties
>> to enabled A618 GPU.
>>
>> Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
> In v4 I added my tags [1]. Please keep them for future patches unless
> something major changes. AKA:
>
> Reviewed-by: Douglas Anderson <dianders@chromium.org>
> Tested-by: Douglas Anderson <dianders@chromium.org>
>
>
>> ---
>> arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 +++++++++++++++++++++++++++++++++++
>> 1 file changed, 102 insertions(+)
> Just to summarize where we are:
>
> * As per my notes in v3 and v4 [1], this can't land until
> "mem_iface_clk" is in the bindings. Please post a patch for this and
> reply with a link here so others can follow the disucssion.
I posted a patch for this @https://patchwork.freedesktop.org/patch/354130/
>
> * This also can't land until the gpucc bindings change from Taniya
> recently [2] lands.
>
> ...so we're in limbo waiting for the bindings to be resolved, but
> otherwise this patch looks good.
>
>
> [1] https://lore.kernel.org/r/CAD=FV=UEQ0mOXuDrSZrcJ8g6jb0eLf1Ttn+Mn7T6d2TpCMUcuA@mail.gmail.com
> [2] https://lore.kernel.org/r/1581307266-26989-1-git-send-email-tdas@codeaurora.org
>
>
> -Doug
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v6] arm64: dts: qcom: sc7180: Add A618 gpu dt blob
@ 2020-02-20 8:20 ` Sharat Masetty
0 siblings, 0 replies; 10+ messages in thread
From: Sharat Masetty @ 2020-02-20 8:20 UTC (permalink / raw)
To: Doug Anderson
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-arm-msm, LKML, Bjorn Andersson, Matthias Kaehlcke,
dri-devel, freedreno
On 2/11/2020 2:51 AM, Doug Anderson wrote:
> Hi,
>
> On Sun, Feb 9, 2020 at 11:41 PM Sharat Masetty <smasetty@codeaurora.org> wrote:
>> This patch adds the required dt nodes and properties
>> to enabled A618 GPU.
>>
>> Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
> In v4 I added my tags [1]. Please keep them for future patches unless
> something major changes. AKA:
>
> Reviewed-by: Douglas Anderson <dianders@chromium.org>
> Tested-by: Douglas Anderson <dianders@chromium.org>
>
>
>> ---
>> arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 +++++++++++++++++++++++++++++++++++
>> 1 file changed, 102 insertions(+)
> Just to summarize where we are:
>
> * As per my notes in v3 and v4 [1], this can't land until
> "mem_iface_clk" is in the bindings. Please post a patch for this and
> reply with a link here so others can follow the disucssion.
I posted a patch for this @https://patchwork.freedesktop.org/patch/354130/
>
> * This also can't land until the gpucc bindings change from Taniya
> recently [2] lands.
>
> ...so we're in limbo waiting for the bindings to be resolved, but
> otherwise this patch looks good.
>
>
> [1] https://lore.kernel.org/r/CAD=FV=UEQ0mOXuDrSZrcJ8g6jb0eLf1Ttn+Mn7T6d2TpCMUcuA@mail.gmail.com
> [2] https://lore.kernel.org/r/1581307266-26989-1-git-send-email-tdas@codeaurora.org
>
>
> -Doug
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Freedreno] [PATCH v6] arm64: dts: qcom: sc7180: Add A618 gpu dt blob
2020-02-10 7:41 ` Sharat Masetty
@ 2020-02-20 16:19 ` Rob Clark
-1 siblings, 0 replies; 10+ messages in thread
From: Rob Clark @ 2020-02-20 16:19 UTC (permalink / raw)
To: Sharat Masetty
Cc: freedreno,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Douglas Anderson, linux-arm-msm, Linux Kernel Mailing List,
Bjorn Andersson, Jordan Crouse, Matthias Kaehlcke, dri-devel
On Sun, Feb 9, 2020 at 11:41 PM Sharat Masetty <smasetty@codeaurora.org> wrote:
>
> This patch adds the required dt nodes and properties
> to enabled A618 GPU.
>
> Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
> ---
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 +++++++++++++++++++++++++++++++++++
> 1 file changed, 102 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index f3fcc5c..63fff15 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -1043,6 +1043,108 @@
> };
> };
>
> + gpu: gpu@5000000 {
> + compatible = "qcom,adreno-618.0", "qcom,adreno";
> + #stream-id-cells = <16>;
> + reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
> + <0 0x05061000 0 0x800>;
> + reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
> + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
> + iommus = <&adreno_smmu 0>;
> + operating-points-v2 = <&gpu_opp_table>;
> + qcom,gmu = <&gmu>;
> +
> + gpu_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-800000000 {
> + opp-hz = /bits/ 64 <800000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> + };
> +
> + opp-650000000 {
> + opp-hz = /bits/ 64 <650000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> + };
> +
> + opp-565000000 {
> + opp-hz = /bits/ 64 <565000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> + };
> +
> + opp-430000000 {
> + opp-hz = /bits/ 64 <430000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> + };
> +
> + opp-355000000 {
> + opp-hz = /bits/ 64 <355000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> + };
> +
> + opp-267000000 {
> + opp-hz = /bits/ 64 <267000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> + };
> +
> + opp-180000000 {
> + opp-hz = /bits/ 64 <180000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
> + };
> + };
> + };
> +
> + adreno_smmu: iommu@5040000 {
> + compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2";
> + reg = <0 0x05040000 0 0x10000>;
> + #iommu-cells = <1>;
> + #global-interrupts = <2>;
> + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
> + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> + <&gcc GCC_GPU_CFG_AHB_CLK>,
> + <&gcc GCC_DDRSS_GPU_AXI_CLK>;
> +
> + clock-names = "bus", "iface", "mem_iface_clk";
> + power-domains = <&gpucc CX_GDSC>;
> + };
> +
> + gmu: gmu@506a000 {
> + compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
> + reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
> + <0 0x0b490000 0 0x10000>;
> + reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
> + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hfi", "gmu";
> + clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
> + <&gpucc GPU_CC_CXO_CLK>,
> + <&gcc GCC_DDRSS_GPU_AXI_CLK>,
> + <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
> + clock-names = "gmu", "cxo", "axi", "memnoc";
> + power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
> + power-domain-names = "cx", "gx";
> + iommus = <&adreno_smmu 5>;
> + operating-points-v2 = <&gmu_opp_table>;
jfyi, this will shortly require a dma-ranges property[1].. it might
simplify things, wrt. to which order patches land (this vs dma-ranges)
to go ahead and add the dma-ranges property now
BR,
-R
[1] https://lists.freedesktop.org/archives/freedreno/2020-February/006903.html
> +
> + gmu_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-200000000 {
> + opp-hz = /bits/ 64 <200000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
> + };
> + };
> + };
> +
> gpucc: clock-controller@5090000 {
> compatible = "qcom,sc7180-gpucc";
> reg = <0 0x05090000 0 0x9000>;
> --
> 1.9.1
> _______________________________________________
> Freedreno mailing list
> Freedreno@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/freedreno
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [Freedreno] [PATCH v6] arm64: dts: qcom: sc7180: Add A618 gpu dt blob
@ 2020-02-20 16:19 ` Rob Clark
0 siblings, 0 replies; 10+ messages in thread
From: Rob Clark @ 2020-02-20 16:19 UTC (permalink / raw)
To: Sharat Masetty
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Douglas Anderson, Bjorn Andersson,
Matthias Kaehlcke, dri-devel, linux-arm-msm, freedreno
On Sun, Feb 9, 2020 at 11:41 PM Sharat Masetty <smasetty@codeaurora.org> wrote:
>
> This patch adds the required dt nodes and properties
> to enabled A618 GPU.
>
> Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
> ---
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 +++++++++++++++++++++++++++++++++++
> 1 file changed, 102 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index f3fcc5c..63fff15 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -1043,6 +1043,108 @@
> };
> };
>
> + gpu: gpu@5000000 {
> + compatible = "qcom,adreno-618.0", "qcom,adreno";
> + #stream-id-cells = <16>;
> + reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
> + <0 0x05061000 0 0x800>;
> + reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
> + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
> + iommus = <&adreno_smmu 0>;
> + operating-points-v2 = <&gpu_opp_table>;
> + qcom,gmu = <&gmu>;
> +
> + gpu_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-800000000 {
> + opp-hz = /bits/ 64 <800000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> + };
> +
> + opp-650000000 {
> + opp-hz = /bits/ 64 <650000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> + };
> +
> + opp-565000000 {
> + opp-hz = /bits/ 64 <565000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> + };
> +
> + opp-430000000 {
> + opp-hz = /bits/ 64 <430000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> + };
> +
> + opp-355000000 {
> + opp-hz = /bits/ 64 <355000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> + };
> +
> + opp-267000000 {
> + opp-hz = /bits/ 64 <267000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> + };
> +
> + opp-180000000 {
> + opp-hz = /bits/ 64 <180000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
> + };
> + };
> + };
> +
> + adreno_smmu: iommu@5040000 {
> + compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2";
> + reg = <0 0x05040000 0 0x10000>;
> + #iommu-cells = <1>;
> + #global-interrupts = <2>;
> + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
> + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> + <&gcc GCC_GPU_CFG_AHB_CLK>,
> + <&gcc GCC_DDRSS_GPU_AXI_CLK>;
> +
> + clock-names = "bus", "iface", "mem_iface_clk";
> + power-domains = <&gpucc CX_GDSC>;
> + };
> +
> + gmu: gmu@506a000 {
> + compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
> + reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
> + <0 0x0b490000 0 0x10000>;
> + reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
> + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hfi", "gmu";
> + clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
> + <&gpucc GPU_CC_CXO_CLK>,
> + <&gcc GCC_DDRSS_GPU_AXI_CLK>,
> + <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
> + clock-names = "gmu", "cxo", "axi", "memnoc";
> + power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
> + power-domain-names = "cx", "gx";
> + iommus = <&adreno_smmu 5>;
> + operating-points-v2 = <&gmu_opp_table>;
jfyi, this will shortly require a dma-ranges property[1].. it might
simplify things, wrt. to which order patches land (this vs dma-ranges)
to go ahead and add the dma-ranges property now
BR,
-R
[1] https://lists.freedesktop.org/archives/freedreno/2020-February/006903.html
> +
> + gmu_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-200000000 {
> + opp-hz = /bits/ 64 <200000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
> + };
> + };
> + };
> +
> gpucc: clock-controller@5090000 {
> compatible = "qcom,sc7180-gpucc";
> reg = <0 0x05090000 0 0x9000>;
> --
> 1.9.1
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