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From: Sharat Masetty <smasetty@codeaurora.org>
To: freedreno@lists.freedesktop.org, devicetree@vger.kernel.org
Cc: dri-devel@freedesktop.org, linux-arm-msm@vger.kernel.org,
	linux-kernel@vger.kernel.org, jcrouse@codeaurora.org,
	mka@chromium.org, sibis@codeaurora.org, saravanak@google.com,
	viresh.kumar@linaro.org, Sharat Masetty <smasetty@codeaurora.org>
Subject: [PATCH 2/5] arm64: dts: qcom: sc7180: Add GPU DDR BW opp table
Date: Tue, 31 Mar 2020 13:25:50 +0530	[thread overview]
Message-ID: <1585641353-23229-3-git-send-email-smasetty@codeaurora.org> (raw)
In-Reply-To: <1585641353-23229-1-git-send-email-smasetty@codeaurora.org>

This patch adds a new opp table listing the GPU DDR bandwidth opps. Also
adds a required_opp binding to the GPUs main OPP table which holds a
phandle to a bandwidth opp in the new table. This enables linking the
GPU power level opp to the DDR bandwidth opp and helps with scaling
DDR along with GPU frequency.

Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 50 +++++++++++++++++++++++++++++++++++-
 1 file changed, 49 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 51630dd..74b023b 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -1715,7 +1715,8 @@
 			reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
 			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
 			iommus = <&adreno_smmu 0>;
-			operating-points-v2 = <&gpu_opp_table>;
+			operating-points-v2 = <&gpu_opp_table>,
+						<&gpu_ddr_bw_opp_table>;
 			qcom,gmu = <&gmu>;

 			interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
@@ -1726,40 +1727,87 @@
 				opp-800000000 {
 					opp-hz = /bits/ 64 <800000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+					required-opps = <&gpu_ddr_bw_opp9>;
 				};

 				opp-650000000 {
 					opp-hz = /bits/ 64 <650000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+					required-opps = <&gpu_ddr_bw_opp8>;
 				};

 				opp-565000000 {
 					opp-hz = /bits/ 64 <565000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+					required-opps = <&gpu_ddr_bw_opp6>;
 				};

 				opp-430000000 {
 					opp-hz = /bits/ 64 <430000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+					required-opps = <&gpu_ddr_bw_opp6>;
 				};

 				opp-355000000 {
 					opp-hz = /bits/ 64 <355000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+					required-opps = <&gpu_ddr_bw_opp4>;
 				};

 				opp-267000000 {
 					opp-hz = /bits/ 64 <267000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+					required-opps = <&gpu_ddr_bw_opp4>;
 				};

 				opp-180000000 {
 					opp-hz = /bits/ 64 <180000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+					required-opps = <&gpu_ddr_bw_opp2>;
 				};
 			};
 		};

+		gpu_ddr_bw_opp_table: gpu-ddr-bw-opp-table {
+			compatible = "operating-points-v2";
+
+			gpu_ddr_bw_opp1: opp-300000000  {
+				opp-peak-kBps =/bits/ 32 <1200000>;
+			};
+
+			gpu_ddr_bw_opp2: opp-451000000  {
+				opp-peak-kBps =/bits/ 32 <1804000>;
+			};
+
+			gpu_ddr_bw_opp3: opp-547000000  {
+				opp-peak-kBps =/bits/ 32 <2188000>;
+			};
+
+			gpu_ddr_bw_opp4: opp-768000000  {
+				opp-peak-kBps =/bits/ 32 <3072000>;
+			};
+
+			gpu_ddr_bw_opp5: opp-1017000000  {
+				opp-peak-kBps =/bits/ 32 <4068000>;
+			};
+
+			gpu_ddr_bw_opp6: opp-1353000000  {
+				opp-peak-kBps =/bits/ 32 <5412000>;
+			};
+
+			gpu_ddr_bw_opp7: opp-1555000000  {
+				opp-peak-kBps =/bits/ 32 <6220000>;
+			};
+
+			gpu_ddr_bw_opp8: opp-1804000000  {
+				opp-peak-kBps =/bits/ 32 <7216000>;
+			};
+
+			gpu_ddr_bw_opp9: opp-2133000000  {
+				opp-peak-kBps =/bits/ 32 <8532000>;
+			};
+		};
+
 		adreno_smmu: iommu@5040000 {
 			compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2";
 			reg = <0 0x05040000 0 0x10000>;
--
2.7.4

WARNING: multiple messages have this Message-ID (diff)
From: Sharat Masetty <smasetty@codeaurora.org>
To: freedreno@lists.freedesktop.org, devicetree@vger.kernel.org
Cc: saravanak@google.com, linux-arm-msm@vger.kernel.org,
	Sharat Masetty <smasetty@codeaurora.org>,
	linux-kernel@vger.kernel.org, mka@chromium.org,
	sibis@codeaurora.org, viresh.kumar@linaro.org,
	dri-devel@freedesktop.org
Subject: [PATCH 2/5] arm64: dts: qcom: sc7180: Add GPU DDR BW opp table
Date: Tue, 31 Mar 2020 13:25:50 +0530	[thread overview]
Message-ID: <1585641353-23229-3-git-send-email-smasetty@codeaurora.org> (raw)
In-Reply-To: <1585641353-23229-1-git-send-email-smasetty@codeaurora.org>

This patch adds a new opp table listing the GPU DDR bandwidth opps. Also
adds a required_opp binding to the GPUs main OPP table which holds a
phandle to a bandwidth opp in the new table. This enables linking the
GPU power level opp to the DDR bandwidth opp and helps with scaling
DDR along with GPU frequency.

Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 50 +++++++++++++++++++++++++++++++++++-
 1 file changed, 49 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 51630dd..74b023b 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -1715,7 +1715,8 @@
 			reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
 			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
 			iommus = <&adreno_smmu 0>;
-			operating-points-v2 = <&gpu_opp_table>;
+			operating-points-v2 = <&gpu_opp_table>,
+						<&gpu_ddr_bw_opp_table>;
 			qcom,gmu = <&gmu>;

 			interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
@@ -1726,40 +1727,87 @@
 				opp-800000000 {
 					opp-hz = /bits/ 64 <800000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+					required-opps = <&gpu_ddr_bw_opp9>;
 				};

 				opp-650000000 {
 					opp-hz = /bits/ 64 <650000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+					required-opps = <&gpu_ddr_bw_opp8>;
 				};

 				opp-565000000 {
 					opp-hz = /bits/ 64 <565000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+					required-opps = <&gpu_ddr_bw_opp6>;
 				};

 				opp-430000000 {
 					opp-hz = /bits/ 64 <430000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+					required-opps = <&gpu_ddr_bw_opp6>;
 				};

 				opp-355000000 {
 					opp-hz = /bits/ 64 <355000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+					required-opps = <&gpu_ddr_bw_opp4>;
 				};

 				opp-267000000 {
 					opp-hz = /bits/ 64 <267000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+					required-opps = <&gpu_ddr_bw_opp4>;
 				};

 				opp-180000000 {
 					opp-hz = /bits/ 64 <180000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+					required-opps = <&gpu_ddr_bw_opp2>;
 				};
 			};
 		};

+		gpu_ddr_bw_opp_table: gpu-ddr-bw-opp-table {
+			compatible = "operating-points-v2";
+
+			gpu_ddr_bw_opp1: opp-300000000  {
+				opp-peak-kBps =/bits/ 32 <1200000>;
+			};
+
+			gpu_ddr_bw_opp2: opp-451000000  {
+				opp-peak-kBps =/bits/ 32 <1804000>;
+			};
+
+			gpu_ddr_bw_opp3: opp-547000000  {
+				opp-peak-kBps =/bits/ 32 <2188000>;
+			};
+
+			gpu_ddr_bw_opp4: opp-768000000  {
+				opp-peak-kBps =/bits/ 32 <3072000>;
+			};
+
+			gpu_ddr_bw_opp5: opp-1017000000  {
+				opp-peak-kBps =/bits/ 32 <4068000>;
+			};
+
+			gpu_ddr_bw_opp6: opp-1353000000  {
+				opp-peak-kBps =/bits/ 32 <5412000>;
+			};
+
+			gpu_ddr_bw_opp7: opp-1555000000  {
+				opp-peak-kBps =/bits/ 32 <6220000>;
+			};
+
+			gpu_ddr_bw_opp8: opp-1804000000  {
+				opp-peak-kBps =/bits/ 32 <7216000>;
+			};
+
+			gpu_ddr_bw_opp9: opp-2133000000  {
+				opp-peak-kBps =/bits/ 32 <8532000>;
+			};
+		};
+
 		adreno_smmu: iommu@5040000 {
 			compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2";
 			reg = <0 0x05040000 0 0x10000>;
--
2.7.4
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dri-devel@lists.freedesktop.org
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  parent reply	other threads:[~2020-03-31  7:56 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-31  7:55 [PATCH 0/5] Add support for GPU DDR BW scaling Sharat Masetty
2020-03-31  7:55 ` Sharat Masetty
2020-03-31  7:55 ` [PATCH 1/5] arm64: dts: qcom: sc7180: Add interconnect bindings for GPU Sharat Masetty
2020-03-31  7:55   ` Sharat Masetty
2020-03-31  7:55 ` Sharat Masetty [this message]
2020-03-31  7:55   ` [PATCH 2/5] arm64: dts: qcom: sc7180: Add GPU DDR BW opp table Sharat Masetty
2020-03-31  7:55 ` [PATCH 3/5] drm: msm: scale DDR BW along with GPU frequency Sharat Masetty
2020-03-31  7:55   ` Sharat Masetty
2020-03-31 17:26   ` Jordan Crouse
2020-03-31 17:26     ` Jordan Crouse
2020-04-01 12:30     ` Sharat Masetty
2020-04-01 12:30       ` Sharat Masetty
2020-03-31  7:55 ` [PATCH 4/5] drm: msm: a6xx: Fix off by one error when setting GPU freq Sharat Masetty
2020-03-31  7:55   ` Sharat Masetty
2020-03-31 16:43   ` Jordan Crouse
2020-03-31 16:43     ` Jordan Crouse
2020-03-31  7:55 ` [PATCH 5/5] dt-bindings: drm/msm/gpu: Document OPP phandle list for the GPU Sharat Masetty
2020-03-31  7:55   ` Sharat Masetty
2020-04-10 17:48   ` Rob Herring
2020-04-10 17:48     ` Rob Herring

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