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From: Crystal Guo <crystal.guo@mediatek.com>
To: Matthias Brugger <matthias.bgg@gmail.com>
Cc: "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	srv_heupstream <srv_heupstream@mediatek.com>,
	"Seiya Wang (王迺君)" <seiya.wang@mediatek.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	"linux-mediatek@lists.infradead.org"
	<linux-mediatek@lists.infradead.org>,
	"p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 2/2] arm64: dts: mt8192: add infracfg_rst node
Date: Wed, 29 Jul 2020 16:18:44 +0800	[thread overview]
Message-ID: <1596010724.11360.6.camel@mhfsdcap03> (raw)
In-Reply-To: <b81f1936-caf0-e843-9556-14e3024d6d6f@gmail.com>

On Wed, 2020-07-29 at 15:45 +0800, Matthias Brugger wrote:
> 
> On 29/07/2020 09:39, Crystal Guo wrote:
> > add infracfg_rst node which is for MT8192 platform
> > 
> > Signed-off-by: Crystal Guo <crystal.guo@mediatek.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 +++++++++-
> >   1 file changed, 9 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index b16dbbd..adc6239 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -217,9 +217,17 @@
> >   		};
> >   
> >   		infracfg: infracfg@10001000 {
> > -			compatible = "mediatek,mt8192-infracfg", "syscon";
> > +			compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd";
> >   			reg = <0 0x10001000 0 0x1000>;
> >   			#clock-cells = <1>;
> > +
> > +			infracfg_rst: reset-controller {
> > +				compatible = "ti,syscon-reset";
> > +				#reset-cells = <1>;
> > +				ti,reset-bits = <
> > +					0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: pcie */
> 
> You have Texas Instruments hardware inside infracfg? Are you sure?
> 
TI reset-controller driver is a common driver, MTK SOC has the similar
control flow, thus can reuse it.

> > +				>;
> > +			};
> >   		};
> >   
> >   		pericfg: pericfg@10003000 {
> > 

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

WARNING: multiple messages have this Message-ID (diff)
From: Crystal Guo <crystal.guo@mediatek.com>
To: Matthias Brugger <matthias.bgg@gmail.com>
Cc: "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	srv_heupstream <srv_heupstream@mediatek.com>,
	"Seiya Wang (王迺君)" <seiya.wang@mediatek.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	"linux-mediatek@lists.infradead.org"
	<linux-mediatek@lists.infradead.org>,
	"p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 2/2] arm64: dts: mt8192: add infracfg_rst node
Date: Wed, 29 Jul 2020 16:18:44 +0800	[thread overview]
Message-ID: <1596010724.11360.6.camel@mhfsdcap03> (raw)
In-Reply-To: <b81f1936-caf0-e843-9556-14e3024d6d6f@gmail.com>

On Wed, 2020-07-29 at 15:45 +0800, Matthias Brugger wrote:
> 
> On 29/07/2020 09:39, Crystal Guo wrote:
> > add infracfg_rst node which is for MT8192 platform
> > 
> > Signed-off-by: Crystal Guo <crystal.guo@mediatek.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 +++++++++-
> >   1 file changed, 9 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index b16dbbd..adc6239 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -217,9 +217,17 @@
> >   		};
> >   
> >   		infracfg: infracfg@10001000 {
> > -			compatible = "mediatek,mt8192-infracfg", "syscon";
> > +			compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd";
> >   			reg = <0 0x10001000 0 0x1000>;
> >   			#clock-cells = <1>;
> > +
> > +			infracfg_rst: reset-controller {
> > +				compatible = "ti,syscon-reset";
> > +				#reset-cells = <1>;
> > +				ti,reset-bits = <
> > +					0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: pcie */
> 
> You have Texas Instruments hardware inside infracfg? Are you sure?
> 
TI reset-controller driver is a common driver, MTK SOC has the similar
control flow, thus can reuse it.

> > +				>;
> > +			};
> >   		};
> >   
> >   		pericfg: pericfg@10003000 {
> > 

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: Crystal Guo <crystal.guo@mediatek.com>
To: Matthias Brugger <matthias.bgg@gmail.com>
Cc: "p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	srv_heupstream <srv_heupstream@mediatek.com>,
	"linux-mediatek@lists.infradead.org"
	<linux-mediatek@lists.infradead.org>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"Seiya Wang (王迺君)" <seiya.wang@mediatek.com>
Subject: Re: [PATCH 2/2] arm64: dts: mt8192: add infracfg_rst node
Date: Wed, 29 Jul 2020 16:18:44 +0800	[thread overview]
Message-ID: <1596010724.11360.6.camel@mhfsdcap03> (raw)
In-Reply-To: <b81f1936-caf0-e843-9556-14e3024d6d6f@gmail.com>

On Wed, 2020-07-29 at 15:45 +0800, Matthias Brugger wrote:
> 
> On 29/07/2020 09:39, Crystal Guo wrote:
> > add infracfg_rst node which is for MT8192 platform
> > 
> > Signed-off-by: Crystal Guo <crystal.guo@mediatek.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 +++++++++-
> >   1 file changed, 9 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index b16dbbd..adc6239 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -217,9 +217,17 @@
> >   		};
> >   
> >   		infracfg: infracfg@10001000 {
> > -			compatible = "mediatek,mt8192-infracfg", "syscon";
> > +			compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd";
> >   			reg = <0 0x10001000 0 0x1000>;
> >   			#clock-cells = <1>;
> > +
> > +			infracfg_rst: reset-controller {
> > +				compatible = "ti,syscon-reset";
> > +				#reset-cells = <1>;
> > +				ti,reset-bits = <
> > +					0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: pcie */
> 
> You have Texas Instruments hardware inside infracfg? Are you sure?
> 
TI reset-controller driver is a common driver, MTK SOC has the similar
control flow, thus can reuse it.

> > +				>;
> > +			};
> >   		};
> >   
> >   		pericfg: pericfg@10003000 {
> > 


  reply	other threads:[~2020-07-29  8:22 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-29  7:39 [PATCH 0/2] adjust the reset assert and deassert interface Crystal Guo
2020-07-29  7:39 ` Crystal Guo
2020-07-29  7:39 ` Crystal Guo
2020-07-29  7:39 ` [PATCH 1/2] reset-controller: ti: " Crystal Guo
2020-07-29  7:39   ` Crystal Guo
2020-07-29  7:39   ` Crystal Guo
2020-07-29  7:48   ` Matthias Brugger
2020-07-29  7:48     ` Matthias Brugger
2020-07-29  7:48     ` Matthias Brugger
2020-07-29  8:02     ` Philipp Zabel
2020-07-29  8:02       ` Philipp Zabel
2020-07-29  8:02       ` Philipp Zabel
2020-07-30  6:27       ` Crystal Guo
2020-07-30  6:27         ` Crystal Guo
2020-07-30  6:27         ` Crystal Guo
2020-07-29  7:39 ` [PATCH 2/2] arm64: dts: mt8192: add infracfg_rst node Crystal Guo
2020-07-29  7:39   ` Crystal Guo
2020-07-29  7:39   ` Crystal Guo
2020-07-29  7:45   ` Matthias Brugger
2020-07-29  7:45     ` Matthias Brugger
2020-07-29  7:45     ` Matthias Brugger
2020-07-29  8:18     ` Crystal Guo [this message]
2020-07-29  8:18       ` Crystal Guo
2020-07-29  8:18       ` Crystal Guo

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