* [PATCH V2 1/4] perf/x86: Add Intel Raptor Lake support
@ 2022-03-15 17:45 kan.liang
2022-03-15 17:45 ` [PATCH V2 2/4] perf/x86/cstate: Add " kan.liang
` (4 more replies)
0 siblings, 5 replies; 9+ messages in thread
From: kan.liang @ 2022-03-15 17:45 UTC (permalink / raw)
To: peterz, mingo, linux-kernel; +Cc: Kan Liang
From: Kan Liang <kan.liang@linux.intel.com>
From PMU's perspective, Raptor Lake is the same as the Alder Lake. The
only difference is the event list, which will be supported in the perf
tool later.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
No changes since V1
arch/x86/events/intel/core.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 88dcfb4..24a4a75 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -6199,6 +6199,7 @@ __init int intel_pmu_init(void)
case INTEL_FAM6_ALDERLAKE:
case INTEL_FAM6_ALDERLAKE_L:
+ case INTEL_FAM6_RAPTORLAKE:
/*
* Alder Lake has 2 types of CPU, core and atom.
*
--
2.7.4
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH V2 2/4] perf/x86/cstate: Add Raptor Lake support 2022-03-15 17:45 [PATCH V2 1/4] perf/x86: Add Intel Raptor Lake support kan.liang @ 2022-03-15 17:45 ` kan.liang 2022-04-05 8:29 ` [tip: perf/urgent] " tip-bot2 for Kan Liang 2022-03-15 17:45 ` [PATCH V2 3/4] perf/x86/msr: Add Raptor Lake CPU support kan.liang ` (3 subsequent siblings) 4 siblings, 1 reply; 9+ messages in thread From: kan.liang @ 2022-03-15 17:45 UTC (permalink / raw) To: peterz, mingo, linux-kernel; +Cc: Kan Liang From: Kan Liang <kan.liang@linux.intel.com> Raptor Lake is Intel's successor to Alder lake. From the perspective of Intel cstate residency counters, there is nothing changed compared with Alder lake. Share adl_cstates with Alder lake. Update the comments for Raptor Lake. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> --- No changes since V1 arch/x86/events/intel/cstate.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c index c6262b1..5d77622 100644 --- a/arch/x86/events/intel/cstate.c +++ b/arch/x86/events/intel/cstate.c @@ -40,7 +40,7 @@ * Model specific counters: * MSR_CORE_C1_RES: CORE C1 Residency Counter * perf code: 0x00 - * Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL + * Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL,RPL * Scope: Core (each processor core has a MSR) * MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter * perf code: 0x01 @@ -51,49 +51,50 @@ * perf code: 0x02 * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW, * SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX, - * TGL,TNT,RKL,ADL + * TGL,TNT,RKL,ADL,RPL * Scope: Core * MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter * perf code: 0x03 * Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML, - * ICL,TGL,RKL,ADL + * ICL,TGL,RKL,ADL,RPL * Scope: Core * MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter. * perf code: 0x00 * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL, - * KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL + * KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL, + * RPL * Scope: Package (physical package) * MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter. * perf code: 0x01 * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL, * GLM,CNL,KBL,CML,ICL,TGL,TNT,RKL, - * ADL + * ADL,RPL * Scope: Package (physical package) * MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter. * perf code: 0x02 * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW, * SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX, - * TGL,TNT,RKL,ADL + * TGL,TNT,RKL,ADL,RPL * Scope: Package (physical package) * MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter. * perf code: 0x03 * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL, - * KBL,CML,ICL,TGL,RKL,ADL + * KBL,CML,ICL,TGL,RKL,ADL,RPL * Scope: Package (physical package) * MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter. * perf code: 0x04 * Available model: HSW ULT,KBL,CNL,CML,ICL,TGL,RKL, - * ADL + * ADL,RPL * Scope: Package (physical package) * MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter. * perf code: 0x05 * Available model: HSW ULT,KBL,CNL,CML,ICL,TGL,RKL, - * ADL + * ADL,RPL * Scope: Package (physical package) * MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter. * perf code: 0x06 * Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL, - * TNT,RKL,ADL + * TNT,RKL,ADL,RPL * Scope: Package (physical package) * */ @@ -680,6 +681,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE, &icl_cstates), X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, &adl_cstates), X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, &adl_cstates), + X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, &adl_cstates), { }, }; MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match); -- 2.7.4 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [tip: perf/urgent] perf/x86/cstate: Add Raptor Lake support 2022-03-15 17:45 ` [PATCH V2 2/4] perf/x86/cstate: Add " kan.liang @ 2022-04-05 8:29 ` tip-bot2 for Kan Liang 0 siblings, 0 replies; 9+ messages in thread From: tip-bot2 for Kan Liang @ 2022-04-05 8:29 UTC (permalink / raw) To: linux-tip-commits; +Cc: Kan Liang, Peter Zijlstra (Intel), x86, linux-kernel The following commit has been merged into the perf/urgent branch of tip: Commit-ID: 2da202aa1c38bfe8841611a3d339892eb5579e2b Gitweb: https://git.kernel.org/tip/2da202aa1c38bfe8841611a3d339892eb5579e2b Author: Kan Liang <kan.liang@linux.intel.com> AuthorDate: Tue, 15 Mar 2022 10:45:58 -07:00 Committer: Peter Zijlstra <peterz@infradead.org> CommitterDate: Tue, 05 Apr 2022 09:59:43 +02:00 perf/x86/cstate: Add Raptor Lake support Raptor Lake is Intel's successor to Alder lake. From the perspective of Intel cstate residency counters, there is nothing changed compared with Alder lake. Share adl_cstates with Alder lake. Update the comments for Raptor Lake. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/1647366360-82824-2-git-send-email-kan.liang@linux.intel.com --- arch/x86/events/intel/cstate.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c index c6262b1..5d77622 100644 --- a/arch/x86/events/intel/cstate.c +++ b/arch/x86/events/intel/cstate.c @@ -40,7 +40,7 @@ * Model specific counters: * MSR_CORE_C1_RES: CORE C1 Residency Counter * perf code: 0x00 - * Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL + * Available model: SLM,AMT,GLM,CNL,ICX,TNT,ADL,RPL * Scope: Core (each processor core has a MSR) * MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter * perf code: 0x01 @@ -51,49 +51,50 @@ * perf code: 0x02 * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW, * SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX, - * TGL,TNT,RKL,ADL + * TGL,TNT,RKL,ADL,RPL * Scope: Core * MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter * perf code: 0x03 * Available model: SNB,IVB,HSW,BDW,SKL,CNL,KBL,CML, - * ICL,TGL,RKL,ADL + * ICL,TGL,RKL,ADL,RPL * Scope: Core * MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter. * perf code: 0x00 * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL, - * KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL + * KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL, + * RPL * Scope: Package (physical package) * MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter. * perf code: 0x01 * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL, * GLM,CNL,KBL,CML,ICL,TGL,TNT,RKL, - * ADL + * ADL,RPL * Scope: Package (physical package) * MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter. * perf code: 0x02 * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW, * SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX, - * TGL,TNT,RKL,ADL + * TGL,TNT,RKL,ADL,RPL * Scope: Package (physical package) * MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter. * perf code: 0x03 * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL, - * KBL,CML,ICL,TGL,RKL,ADL + * KBL,CML,ICL,TGL,RKL,ADL,RPL * Scope: Package (physical package) * MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter. * perf code: 0x04 * Available model: HSW ULT,KBL,CNL,CML,ICL,TGL,RKL, - * ADL + * ADL,RPL * Scope: Package (physical package) * MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter. * perf code: 0x05 * Available model: HSW ULT,KBL,CNL,CML,ICL,TGL,RKL, - * ADL + * ADL,RPL * Scope: Package (physical package) * MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter. * perf code: 0x06 * Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL, - * TNT,RKL,ADL + * TNT,RKL,ADL,RPL * Scope: Package (physical package) * */ @@ -680,6 +681,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE, &icl_cstates), X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, &adl_cstates), X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, &adl_cstates), + X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, &adl_cstates), { }, }; MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match); ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH V2 3/4] perf/x86/msr: Add Raptor Lake CPU support 2022-03-15 17:45 [PATCH V2 1/4] perf/x86: Add Intel Raptor Lake support kan.liang 2022-03-15 17:45 ` [PATCH V2 2/4] perf/x86/cstate: Add " kan.liang @ 2022-03-15 17:45 ` kan.liang 2022-04-05 8:29 ` [tip: perf/urgent] " tip-bot2 for Kan Liang 2022-03-15 17:46 ` [PATCH V2 4/4] perf/x86/uncore: Add Raptor Lake uncore support kan.liang ` (2 subsequent siblings) 4 siblings, 1 reply; 9+ messages in thread From: kan.liang @ 2022-03-15 17:45 UTC (permalink / raw) To: peterz, mingo, linux-kernel; +Cc: Kan Liang From: Kan Liang <kan.liang@linux.intel.com> Raptor Lake is Intel's successor to Alder lake. PPERF and SMI_COUNT MSRs are also supported. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> --- No changes since V1 arch/x86/events/msr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c index 96c775a..6d759f8 100644 --- a/arch/x86/events/msr.c +++ b/arch/x86/events/msr.c @@ -103,6 +103,7 @@ static bool test_intel(int idx, void *data) case INTEL_FAM6_ROCKETLAKE: case INTEL_FAM6_ALDERLAKE: case INTEL_FAM6_ALDERLAKE_L: + case INTEL_FAM6_RAPTORLAKE: if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF) return true; break; -- 2.7.4 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [tip: perf/urgent] perf/x86/msr: Add Raptor Lake CPU support 2022-03-15 17:45 ` [PATCH V2 3/4] perf/x86/msr: Add Raptor Lake CPU support kan.liang @ 2022-04-05 8:29 ` tip-bot2 for Kan Liang 0 siblings, 0 replies; 9+ messages in thread From: tip-bot2 for Kan Liang @ 2022-04-05 8:29 UTC (permalink / raw) To: linux-tip-commits; +Cc: Kan Liang, Peter Zijlstra (Intel), x86, linux-kernel The following commit has been merged into the perf/urgent branch of tip: Commit-ID: 82cd83047a9a80e52c0849e56885279166215310 Gitweb: https://git.kernel.org/tip/82cd83047a9a80e52c0849e56885279166215310 Author: Kan Liang <kan.liang@linux.intel.com> AuthorDate: Tue, 15 Mar 2022 10:45:59 -07:00 Committer: Peter Zijlstra <peterz@infradead.org> CommitterDate: Tue, 05 Apr 2022 09:59:43 +02:00 perf/x86/msr: Add Raptor Lake CPU support Raptor Lake is Intel's successor to Alder lake. PPERF and SMI_COUNT MSRs are also supported. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/1647366360-82824-3-git-send-email-kan.liang@linux.intel.com --- arch/x86/events/msr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c index 96c775a..6d759f8 100644 --- a/arch/x86/events/msr.c +++ b/arch/x86/events/msr.c @@ -103,6 +103,7 @@ static bool test_intel(int idx, void *data) case INTEL_FAM6_ROCKETLAKE: case INTEL_FAM6_ALDERLAKE: case INTEL_FAM6_ALDERLAKE_L: + case INTEL_FAM6_RAPTORLAKE: if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF) return true; break; ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH V2 4/4] perf/x86/uncore: Add Raptor Lake uncore support 2022-03-15 17:45 [PATCH V2 1/4] perf/x86: Add Intel Raptor Lake support kan.liang 2022-03-15 17:45 ` [PATCH V2 2/4] perf/x86/cstate: Add " kan.liang 2022-03-15 17:45 ` [PATCH V2 3/4] perf/x86/msr: Add Raptor Lake CPU support kan.liang @ 2022-03-15 17:46 ` kan.liang 2022-04-05 8:29 ` [tip: perf/urgent] " tip-bot2 for Kan Liang 2022-03-18 11:06 ` [PATCH V2 1/4] perf/x86: Add Intel Raptor Lake support Peter Zijlstra 2022-04-05 8:29 ` [tip: perf/urgent] " tip-bot2 for Kan Liang 4 siblings, 1 reply; 9+ messages in thread From: kan.liang @ 2022-03-15 17:46 UTC (permalink / raw) To: peterz, mingo, linux-kernel; +Cc: Kan Liang From: Kan Liang <kan.liang@intel.com> The uncore PMU of the Raptor Lake is the same as Alder Lake. Add new PCIIDs of IMC for Raptor Lake. Signed-off-by: Kan Liang <kan.liang@intel.com> --- Changes since V1: - Add one more PCIID arch/x86/events/intel/uncore.c | 1 + arch/x86/events/intel/uncore_snb.c | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index e497da9..7695dca 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -1828,6 +1828,7 @@ static const struct x86_cpu_id intel_uncore_match[] __initconst = { X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE, &rkl_uncore_init), X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, &adl_uncore_init), X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, &adl_uncore_init), + X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, &adl_uncore_init), X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &spr_uncore_init), X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &snr_uncore_init), {}, diff --git a/arch/x86/events/intel/uncore_snb.c b/arch/x86/events/intel/uncore_snb.c index f698a55..4262351 100644 --- a/arch/x86/events/intel/uncore_snb.c +++ b/arch/x86/events/intel/uncore_snb.c @@ -79,6 +79,10 @@ #define PCI_DEVICE_ID_INTEL_ADL_14_IMC 0x4650 #define PCI_DEVICE_ID_INTEL_ADL_15_IMC 0x4668 #define PCI_DEVICE_ID_INTEL_ADL_16_IMC 0x4670 +#define PCI_DEVICE_ID_INTEL_RPL_1_IMC 0xA700 +#define PCI_DEVICE_ID_INTEL_RPL_2_IMC 0xA702 +#define PCI_DEVICE_ID_INTEL_RPL_3_IMC 0xA706 +#define PCI_DEVICE_ID_INTEL_RPL_4_IMC 0xA709 /* SNB event control */ #define SNB_UNC_CTL_EV_SEL_MASK 0x000000ff @@ -1406,6 +1410,22 @@ static const struct pci_device_id tgl_uncore_pci_ids[] = { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ADL_16_IMC), .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), }, + { /* IMC */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_RPL_1_IMC), + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), + }, + { /* IMC */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_RPL_2_IMC), + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), + }, + { /* IMC */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_RPL_3_IMC), + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), + }, + { /* IMC */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_RPL_4_IMC), + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), + }, { /* end: all zeroes */ } }; -- 2.7.4 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [tip: perf/urgent] perf/x86/uncore: Add Raptor Lake uncore support 2022-03-15 17:46 ` [PATCH V2 4/4] perf/x86/uncore: Add Raptor Lake uncore support kan.liang @ 2022-04-05 8:29 ` tip-bot2 for Kan Liang 0 siblings, 0 replies; 9+ messages in thread From: tip-bot2 for Kan Liang @ 2022-04-05 8:29 UTC (permalink / raw) To: linux-tip-commits; +Cc: Kan Liang, Peter Zijlstra (Intel), x86, linux-kernel The following commit has been merged into the perf/urgent branch of tip: Commit-ID: ad4878d4d71d9ada913be2ad5b6d7f526a695b6f Gitweb: https://git.kernel.org/tip/ad4878d4d71d9ada913be2ad5b6d7f526a695b6f Author: Kan Liang <kan.liang@intel.com> AuthorDate: Tue, 15 Mar 2022 10:46:00 -07:00 Committer: Peter Zijlstra <peterz@infradead.org> CommitterDate: Tue, 05 Apr 2022 09:59:43 +02:00 perf/x86/uncore: Add Raptor Lake uncore support The uncore PMU of the Raptor Lake is the same as Alder Lake. Add new PCIIDs of IMC for Raptor Lake. Signed-off-by: Kan Liang <kan.liang@intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/1647366360-82824-4-git-send-email-kan.liang@linux.intel.com --- arch/x86/events/intel/uncore.c | 1 + arch/x86/events/intel/uncore_snb.c | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index e497da9..7695dca 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -1828,6 +1828,7 @@ static const struct x86_cpu_id intel_uncore_match[] __initconst = { X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE, &rkl_uncore_init), X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, &adl_uncore_init), X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, &adl_uncore_init), + X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, &adl_uncore_init), X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &spr_uncore_init), X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &snr_uncore_init), {}, diff --git a/arch/x86/events/intel/uncore_snb.c b/arch/x86/events/intel/uncore_snb.c index f698a55..4262351 100644 --- a/arch/x86/events/intel/uncore_snb.c +++ b/arch/x86/events/intel/uncore_snb.c @@ -79,6 +79,10 @@ #define PCI_DEVICE_ID_INTEL_ADL_14_IMC 0x4650 #define PCI_DEVICE_ID_INTEL_ADL_15_IMC 0x4668 #define PCI_DEVICE_ID_INTEL_ADL_16_IMC 0x4670 +#define PCI_DEVICE_ID_INTEL_RPL_1_IMC 0xA700 +#define PCI_DEVICE_ID_INTEL_RPL_2_IMC 0xA702 +#define PCI_DEVICE_ID_INTEL_RPL_3_IMC 0xA706 +#define PCI_DEVICE_ID_INTEL_RPL_4_IMC 0xA709 /* SNB event control */ #define SNB_UNC_CTL_EV_SEL_MASK 0x000000ff @@ -1406,6 +1410,22 @@ static const struct pci_device_id tgl_uncore_pci_ids[] = { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ADL_16_IMC), .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), }, + { /* IMC */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_RPL_1_IMC), + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), + }, + { /* IMC */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_RPL_2_IMC), + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), + }, + { /* IMC */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_RPL_3_IMC), + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), + }, + { /* IMC */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_RPL_4_IMC), + .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), + }, { /* end: all zeroes */ } }; ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH V2 1/4] perf/x86: Add Intel Raptor Lake support 2022-03-15 17:45 [PATCH V2 1/4] perf/x86: Add Intel Raptor Lake support kan.liang ` (2 preceding siblings ...) 2022-03-15 17:46 ` [PATCH V2 4/4] perf/x86/uncore: Add Raptor Lake uncore support kan.liang @ 2022-03-18 11:06 ` Peter Zijlstra 2022-04-05 8:29 ` [tip: perf/urgent] " tip-bot2 for Kan Liang 4 siblings, 0 replies; 9+ messages in thread From: Peter Zijlstra @ 2022-03-18 11:06 UTC (permalink / raw) To: kan.liang; +Cc: mingo, linux-kernel On Tue, Mar 15, 2022 at 10:45:57AM -0700, kan.liang@linux.intel.com wrote: > From: Kan Liang <kan.liang@linux.intel.com> > > From PMU's perspective, Raptor Lake is the same as the Alder Lake. The > only difference is the event list, which will be supported in the perf > tool later. Thanks! ^ permalink raw reply [flat|nested] 9+ messages in thread
* [tip: perf/urgent] perf/x86: Add Intel Raptor Lake support 2022-03-15 17:45 [PATCH V2 1/4] perf/x86: Add Intel Raptor Lake support kan.liang ` (3 preceding siblings ...) 2022-03-18 11:06 ` [PATCH V2 1/4] perf/x86: Add Intel Raptor Lake support Peter Zijlstra @ 2022-04-05 8:29 ` tip-bot2 for Kan Liang 4 siblings, 0 replies; 9+ messages in thread From: tip-bot2 for Kan Liang @ 2022-04-05 8:29 UTC (permalink / raw) To: linux-tip-commits; +Cc: Kan Liang, Peter Zijlstra (Intel), x86, linux-kernel The following commit has been merged into the perf/urgent branch of tip: Commit-ID: c61759e581576d3330bd1d9490b4d7552e24da6b Gitweb: https://git.kernel.org/tip/c61759e581576d3330bd1d9490b4d7552e24da6b Author: Kan Liang <kan.liang@linux.intel.com> AuthorDate: Tue, 15 Mar 2022 10:45:57 -07:00 Committer: Peter Zijlstra <peterz@infradead.org> CommitterDate: Tue, 05 Apr 2022 09:59:43 +02:00 perf/x86: Add Intel Raptor Lake support >From PMU's perspective, Raptor Lake is the same as the Alder Lake. The only difference is the event list, which will be supported in the perf tool later. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/1647366360-82824-1-git-send-email-kan.liang@linux.intel.com --- arch/x86/events/intel/core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index e88791b..28f075e 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -6212,6 +6212,7 @@ __init int intel_pmu_init(void) case INTEL_FAM6_ALDERLAKE: case INTEL_FAM6_ALDERLAKE_L: + case INTEL_FAM6_RAPTORLAKE: /* * Alder Lake has 2 types of CPU, core and atom. * ^ permalink raw reply related [flat|nested] 9+ messages in thread
end of thread, other threads:[~2022-04-05 10:50 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-03-15 17:45 [PATCH V2 1/4] perf/x86: Add Intel Raptor Lake support kan.liang 2022-03-15 17:45 ` [PATCH V2 2/4] perf/x86/cstate: Add " kan.liang 2022-04-05 8:29 ` [tip: perf/urgent] " tip-bot2 for Kan Liang 2022-03-15 17:45 ` [PATCH V2 3/4] perf/x86/msr: Add Raptor Lake CPU support kan.liang 2022-04-05 8:29 ` [tip: perf/urgent] " tip-bot2 for Kan Liang 2022-03-15 17:46 ` [PATCH V2 4/4] perf/x86/uncore: Add Raptor Lake uncore support kan.liang 2022-04-05 8:29 ` [tip: perf/urgent] " tip-bot2 for Kan Liang 2022-03-18 11:06 ` [PATCH V2 1/4] perf/x86: Add Intel Raptor Lake support Peter Zijlstra 2022-04-05 8:29 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
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