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From: Li Jun <jun.li@nxp.com>
To: shawnguo@kernel.org
Cc: l.stach@pengutronix.de, robh+dt@kernel.org,
	krzysztof.kozlowski+dt@linaro.org, s.hauer@pengutronix.de,
	kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com,
	aford173@gmail.com, tharvey@gateworks.com,
	frieder.schrempf@kontron.de, marex@denx.de,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	xu.yang_2@nxp.com, jun.li@nxp.com
Subject: [PATCH 2/4] arm64: dts: imx8mm: correct usb power domains
Date: Mon, 26 Sep 2022 19:45:33 +0800	[thread overview]
Message-ID: <1664192735-14313-3-git-send-email-jun.li@nxp.com> (raw)
In-Reply-To: <1664192735-14313-1-git-send-email-jun.li@nxp.com>

pgc_otg1/2 is actual the power domain of usb PHY, usb controller
is in hsio power domain, and pgc_otg1/2 is required to be powered
up to detect usb remote wakeup, so move the pgc_otg1/2 power domain
to the usb phy node.

Fixes: 01df28d80859 ("arm64: dts: imx8mm: put USB controllers into power-domains")
Signed-off-by: Li Jun <jun.li@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 41204b871f4f..dabd94dc30c4 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -276,6 +276,7 @@ usbphynop1: usbphynop1 {
 		assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
 		assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
 		clock-names = "main_clk";
+		power-domains = <&pgc_otg1>;
 	};
 
 	usbphynop2: usbphynop2 {
@@ -285,6 +286,7 @@ usbphynop2: usbphynop2 {
 		assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
 		assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
 		clock-names = "main_clk";
+		power-domains = <&pgc_otg2>;
 	};
 
 	soc: soc@0 {
@@ -1184,7 +1186,7 @@ usbotg1: usb@32e40000 {
 				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
 				phys = <&usbphynop1>;
 				fsl,usbmisc = <&usbmisc1 0>;
-				power-domains = <&pgc_otg1>;
+				power-domains = <&pgc_hsiomix>;
 				status = "disabled";
 			};
 
@@ -1204,7 +1206,7 @@ usbotg2: usb@32e50000 {
 				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
 				phys = <&usbphynop2>;
 				fsl,usbmisc = <&usbmisc2 0>;
-				power-domains = <&pgc_otg2>;
+				power-domains = <&pgc_hsiomix>;
 				status = "disabled";
 			};
 
-- 
2.34.1


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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: Li Jun <jun.li@nxp.com>
To: shawnguo@kernel.org
Cc: l.stach@pengutronix.de, robh+dt@kernel.org,
	krzysztof.kozlowski+dt@linaro.org, s.hauer@pengutronix.de,
	kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com,
	aford173@gmail.com, tharvey@gateworks.com,
	frieder.schrempf@kontron.de, marex@denx.de,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	xu.yang_2@nxp.com, jun.li@nxp.com
Subject: [PATCH 2/4] arm64: dts: imx8mm: correct usb power domains
Date: Mon, 26 Sep 2022 19:45:33 +0800	[thread overview]
Message-ID: <1664192735-14313-3-git-send-email-jun.li@nxp.com> (raw)
In-Reply-To: <1664192735-14313-1-git-send-email-jun.li@nxp.com>

pgc_otg1/2 is actual the power domain of usb PHY, usb controller
is in hsio power domain, and pgc_otg1/2 is required to be powered
up to detect usb remote wakeup, so move the pgc_otg1/2 power domain
to the usb phy node.

Fixes: 01df28d80859 ("arm64: dts: imx8mm: put USB controllers into power-domains")
Signed-off-by: Li Jun <jun.li@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 41204b871f4f..dabd94dc30c4 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -276,6 +276,7 @@ usbphynop1: usbphynop1 {
 		assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
 		assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
 		clock-names = "main_clk";
+		power-domains = <&pgc_otg1>;
 	};
 
 	usbphynop2: usbphynop2 {
@@ -285,6 +286,7 @@ usbphynop2: usbphynop2 {
 		assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
 		assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
 		clock-names = "main_clk";
+		power-domains = <&pgc_otg2>;
 	};
 
 	soc: soc@0 {
@@ -1184,7 +1186,7 @@ usbotg1: usb@32e40000 {
 				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
 				phys = <&usbphynop1>;
 				fsl,usbmisc = <&usbmisc1 0>;
-				power-domains = <&pgc_otg1>;
+				power-domains = <&pgc_hsiomix>;
 				status = "disabled";
 			};
 
@@ -1204,7 +1206,7 @@ usbotg2: usb@32e50000 {
 				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
 				phys = <&usbphynop2>;
 				fsl,usbmisc = <&usbmisc2 0>;
-				power-domains = <&pgc_otg2>;
+				power-domains = <&pgc_hsiomix>;
 				status = "disabled";
 			};
 
-- 
2.34.1


  parent reply	other threads:[~2022-09-26 12:07 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-26 11:45 [PATCH 0/4] Split usb otg1/2 power domain from hsio for imx8mm/n Li Jun
2022-09-26 11:45 ` Li Jun
2022-09-26 11:45 ` [PATCH 1/4] arm64: dts: imx8mm: remove otg1/2 power domain dependency on hsio Li Jun
2022-09-26 11:45   ` Li Jun
2022-09-26 11:45 ` Li Jun [this message]
2022-09-26 11:45   ` [PATCH 2/4] arm64: dts: imx8mm: correct usb power domains Li Jun
2022-09-26 11:45 ` [PATCH 3/4] arm64: dts: imx8mn: remove otg1 power domain dependency on hsio Li Jun
2022-09-26 11:45   ` Li Jun
2022-09-26 11:45 ` [PATCH 4/4] arm64: dts: imx8mn: Correct the usb power domain Li Jun
2022-09-26 11:45   ` Li Jun
2022-10-24  1:37 ` [PATCH 0/4] Split usb otg1/2 power domain from hsio for imx8mm/n Shawn Guo
2022-10-24  1:37   ` Shawn Guo

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