From: Bjorn Andersson <andersson@kernel.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
lpieralisi@kernel.org, vkoul@kernel.org, kw@linux.com,
krzysztof.kozlowski+dt@linaro.org, robh@kernel.org
Cc: linux-kernel@vger.kernel.org, kishon@kernel.org,
konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org, bhelgaas@google.com,
linux-phy@lists.infradead.org, linux-pci@vger.kernel.org
Subject: Re: (subset) [PATCH v3 00/13] Add PCIe RC support to Qcom SDX55 SoC
Date: Wed, 15 Mar 2023 20:20:56 -0700 [thread overview]
Message-ID: <167893686410.303819.5208981481540188437.b4-ty@kernel.org> (raw)
In-Reply-To: <20230308082424.140224-1-manivannan.sadhasivam@linaro.org>
On Wed, 8 Mar 2023 13:54:11 +0530, Manivannan Sadhasivam wrote:
> This series adds PCIe RC support to the Qcom SDX55 SoC. The PCIe controller
> in SDX55 can act as both Root Complex and Endpoint but only one mode at a
> time i.e., the mode cannot be switched during runtime.
>
> This series has been tested on Thundercomm T55 board having QCA6390 WLAN
> chipset connected to the PCIe controller. For powering up the WLAN chipset,
> an out-of-tree patch has been used since we do not have a proper driver in
> mainline to handle the power supplies.
>
> [...]
Applied, thanks!
[05/13] ARM: dts: qcom: sdx55: Fix the unit address of PCIe EP node
commit: 3b76b736cd9933ff88764ffec01cbd859c1475e7
[06/13] ARM: dts: qcom: sdx55: Rename pcie0_{phy/lane} to pcie_{phy/lane}
commit: c9f30e3dd92ba779c9cb8bb694ed7a8e2c9f0bb3
[07/13] ARM: dts: qcom: sdx55: Add support for PCIe RC controller
commit: 2b20437e67a4b74b990d19d3dbf55388e941f30f
[08/13] ARM: dts: qcom: sdx55: List the property values vertically
commit: f9364a7ced5e6e36904c359cafe23cbf03645884
[09/13] ARM: dts: qcom: sdx55-t55: Enable PCIe RC support
commit: 046392390884c9dead1d3703fa60dff97f22857a
[10/13] ARM: dts: qcom: sdx55-t55: Move "status" property down
commit: 43743bfa36daed8f31860ad889a1413f239bb2f2
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
WARNING: multiple messages have this Message-ID (diff)
From: Bjorn Andersson <andersson@kernel.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
lpieralisi@kernel.org, vkoul@kernel.org, kw@linux.com,
krzysztof.kozlowski+dt@linaro.org, robh@kernel.org
Cc: linux-kernel@vger.kernel.org, kishon@kernel.org,
konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org, bhelgaas@google.com,
linux-phy@lists.infradead.org, linux-pci@vger.kernel.org
Subject: Re: (subset) [PATCH v3 00/13] Add PCIe RC support to Qcom SDX55 SoC
Date: Wed, 15 Mar 2023 20:20:56 -0700 [thread overview]
Message-ID: <167893686410.303819.5208981481540188437.b4-ty@kernel.org> (raw)
In-Reply-To: <20230308082424.140224-1-manivannan.sadhasivam@linaro.org>
On Wed, 8 Mar 2023 13:54:11 +0530, Manivannan Sadhasivam wrote:
> This series adds PCIe RC support to the Qcom SDX55 SoC. The PCIe controller
> in SDX55 can act as both Root Complex and Endpoint but only one mode at a
> time i.e., the mode cannot be switched during runtime.
>
> This series has been tested on Thundercomm T55 board having QCA6390 WLAN
> chipset connected to the PCIe controller. For powering up the WLAN chipset,
> an out-of-tree patch has been used since we do not have a proper driver in
> mainline to handle the power supplies.
>
> [...]
Applied, thanks!
[05/13] ARM: dts: qcom: sdx55: Fix the unit address of PCIe EP node
commit: 3b76b736cd9933ff88764ffec01cbd859c1475e7
[06/13] ARM: dts: qcom: sdx55: Rename pcie0_{phy/lane} to pcie_{phy/lane}
commit: c9f30e3dd92ba779c9cb8bb694ed7a8e2c9f0bb3
[07/13] ARM: dts: qcom: sdx55: Add support for PCIe RC controller
commit: 2b20437e67a4b74b990d19d3dbf55388e941f30f
[08/13] ARM: dts: qcom: sdx55: List the property values vertically
commit: f9364a7ced5e6e36904c359cafe23cbf03645884
[09/13] ARM: dts: qcom: sdx55-t55: Enable PCIe RC support
commit: 046392390884c9dead1d3703fa60dff97f22857a
[10/13] ARM: dts: qcom: sdx55-t55: Move "status" property down
commit: 43743bfa36daed8f31860ad889a1413f239bb2f2
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
next prev parent reply other threads:[~2023-03-16 3:18 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-08 8:24 [PATCH v3 00/13] Add PCIe RC support to Qcom SDX55 SoC Manivannan Sadhasivam
2023-03-08 8:24 ` Manivannan Sadhasivam
2023-03-08 8:24 ` [PATCH v3 01/13] dt-bindings: PCI: qcom: Update maintainers entry Manivannan Sadhasivam
2023-03-08 8:24 ` Manivannan Sadhasivam
2023-03-08 8:24 ` [PATCH v3 02/13] dt-bindings: PCI: qcom: Add iommu-map properties Manivannan Sadhasivam
2023-03-08 8:24 ` Manivannan Sadhasivam
2023-03-16 22:51 ` Rob Herring
2023-03-16 22:51 ` Rob Herring
2023-03-08 8:24 ` [PATCH v3 03/13] dt-bindings: PCI: qcom: Add SDX55 SoC Manivannan Sadhasivam
2023-03-08 8:24 ` Manivannan Sadhasivam
2023-03-08 8:24 ` [PATCH v3 04/13] dt-bindings: PCI: qcom-ep: Fix the unit address used in example Manivannan Sadhasivam
2023-03-08 8:24 ` Manivannan Sadhasivam
2023-03-08 8:24 ` [PATCH v3 05/13] ARM: dts: qcom: sdx55: Fix the unit address of PCIe EP node Manivannan Sadhasivam
2023-03-08 8:24 ` Manivannan Sadhasivam
2023-03-08 8:24 ` [PATCH v3 06/13] ARM: dts: qcom: sdx55: Rename pcie0_{phy/lane} to pcie_{phy/lane} Manivannan Sadhasivam
2023-03-08 8:24 ` Manivannan Sadhasivam
2023-03-08 8:24 ` [PATCH v3 07/13] ARM: dts: qcom: sdx55: Add support for PCIe RC controller Manivannan Sadhasivam
2023-03-08 8:24 ` Manivannan Sadhasivam
2023-03-08 8:24 ` [PATCH v3 08/13] ARM: dts: qcom: sdx55: List the property values vertically Manivannan Sadhasivam
2023-03-08 8:24 ` Manivannan Sadhasivam
2023-03-08 8:24 ` [PATCH v3 09/13] ARM: dts: qcom: sdx55-t55: Enable PCIe RC support Manivannan Sadhasivam
2023-03-08 8:24 ` Manivannan Sadhasivam
2023-03-08 8:24 ` [PATCH v3 10/13] ARM: dts: qcom: sdx55-t55: Move "status" property down Manivannan Sadhasivam
2023-03-08 8:24 ` Manivannan Sadhasivam
2023-03-08 8:24 ` [PATCH v3 11/13] phy: qcom-qmp-pcie: Split out EP related init sequence for SDX55 Manivannan Sadhasivam
2023-03-08 8:24 ` Manivannan Sadhasivam
2023-03-20 9:27 ` Vinod Koul
2023-03-20 9:27 ` Vinod Koul
2023-03-08 8:24 ` [PATCH v3 12/13] phy: qcom-qmp-pcie: Add RC " Manivannan Sadhasivam
2023-03-08 8:24 ` Manivannan Sadhasivam
2023-03-20 9:27 ` Vinod Koul
2023-03-20 9:27 ` Vinod Koul
2023-03-08 8:24 ` [PATCH v3 13/13] PCI: qcom: Add support for SDX55 SoC Manivannan Sadhasivam
2023-03-08 8:24 ` Manivannan Sadhasivam
2023-03-16 3:20 ` Bjorn Andersson [this message]
2023-03-16 3:20 ` (subset) [PATCH v3 00/13] Add PCIe RC support to Qcom " Bjorn Andersson
2023-04-11 10:09 ` Lorenzo Pieralisi
2023-04-11 10:09 ` Lorenzo Pieralisi
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=167893686410.303819.5208981481540188437.b4-ty@kernel.org \
--to=andersson@kernel.org \
--cc=bhelgaas@google.com \
--cc=devicetree@vger.kernel.org \
--cc=kishon@kernel.org \
--cc=konrad.dybcio@linaro.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=kw@linux.com \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-phy@lists.infradead.org \
--cc=lpieralisi@kernel.org \
--cc=manivannan.sadhasivam@linaro.org \
--cc=robh@kernel.org \
--cc=vkoul@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.