[dpdk-dev] [PATCH 01/10] common/mlx5: update PRM definitions for regex availability

[dpdk-dev] [PATCH 01/10] common/mlx5: update PRM definitions for regex availability

[Francis Kelly]

From: Ady Agbarih <adypodoman@gmail.com>

Update PRM hca capabilities definitions as follows:
regexp_version field added - specifies whether BF2 or BF3
regexp field removed
regexp_params field moved
regexp_log_crspace_size field removed
regexp_mmo added - specifies if using regex mmo wqe is supported

Allow regex only if both regexp_params and regexp_mmo are set,
instead of checking regexp_mmo only.

Check version through the new capability field regexp_version instead
of reading crspace register.

Signed-off-by: Ady Agbarih <adypodoman@gmail.com>
---
 drivers/common/mlx5/mlx5_devx_cmds.c |  3 ++-
 drivers/common/mlx5/mlx5_devx_cmds.h |  3 ++-
 drivers/common/mlx5/mlx5_prm.h       | 12 +++++-------
 drivers/regex/mlx5/mlx5_regex.c      | 11 ++---------
 drivers/regex/mlx5/mlx5_rxp_csrs.h   |  2 +-
 5 files changed, 12 insertions(+), 19 deletions(-)

diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index fb7c8e986f..f0af94b31c 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -821,7 +821,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
 	attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format);
 	attr->steering_format_version =
 		MLX5_GET(cmd_hca_cap, hcattr, steering_format_version);
-	attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp);
+	attr->regexp_params = MLX5_GET(cmd_hca_cap, hcattr, regexp_params);
+	attr->regexp_version = MLX5_GET(cmd_hca_cap, hcattr, regexp_version);
 	attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr,
 					       regexp_num_of_engines);
 	/* Read the general_obj_types bitmap and extract the relevant bits. */
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h
index 5e4f3b749e..69b6bed2dd 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -151,7 +151,8 @@ struct mlx5_hca_attr {
 	uint32_t sq_ts_format:2;
 	uint32_t steering_format_version:4;
 	uint32_t qp_ts_format:2;
-	uint32_t regex:1;
+	uint32_t regexp_params:1;
+	uint32_t regexp_version:3;
 	uint32_t reg_c_preserve:1;
 	uint32_t ct_offload:1; /* General obj type ASO CT offload supported. */
 	uint32_t crypto:1; /* Crypto engine is supported. */
diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index eab80eaead..8b0f2f1a89 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -1341,16 +1341,13 @@ struct mlx5_ifc_cmd_hca_cap_bits {
 	u8 wqe_index_ignore_cap[0x1];
 	u8 dynamic_qp_allocation[0x1];
 	u8 log_max_qp[0x5];
-	u8 regexp[0x1];
-	u8 reserved_at_a1[0x3];
+	u8 reserved_at_a0[0x4];
 	u8 regexp_num_of_engines[0x4];
 	u8 reserved_at_a8[0x1];
 	u8 reg_c_preserve[0x1];
 	u8 reserved_at_aa[0x1];
 	u8 log_max_srq[0x5];
-	u8 reserved_at_b0[0x3];
-	u8 regexp_log_crspace_size[0x5];
-	u8 reserved_at_b8[0x3];
+	u8 reserved_at_b0[0xb];
 	u8 scatter_fcs_w_decap_disable[0x1];
 	u8 reserved_at_bc[0x4];
 	u8 reserved_at_c0[0x8];
@@ -1506,7 +1503,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
 	u8 uc[0x1];
 	u8 rc[0x1];
 	u8 uar_4k[0x1];
-	u8 reserved_at_241[0x9];
+	u8 reserved_at_241[0x8];
+	u8 regexp_params[0x1];
 	u8 uar_sz[0x6];
 	u8 port_selection_cap[0x1];
 	u8 reserved_at_251[0x7];
@@ -1523,7 +1521,7 @@ struct mlx5_ifc_cmd_hca_cap_bits {
 	u8 max_wqe_sz_sq[0x10];
 	u8 reserved_at_2a0[0xc];
 	u8 regexp_mmo_sq[0x1];
-	u8 reserved_at_2b0[0x3];
+	u8 regexp_version[0x3];
 	u8 max_wqe_sz_rq[0x10];
 	u8 max_flow_counter_31_16[0x10];
 	u8 max_wqe_sz_sq_dc[0x10];
diff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c
index 5aa988be6d..2124fd15f0 100644
--- a/drivers/regex/mlx5/mlx5_regex.c
+++ b/drivers/regex/mlx5/mlx5_regex.c
@@ -129,7 +129,6 @@ mlx5_regex_dev_probe(struct rte_device *rte_dev)
 	struct mlx5_hca_attr attr;
 	char name[RTE_REGEXDEV_NAME_MAX_LEN];
 	int ret;
-	uint32_t val;
 
 	ibv = mlx5_os_get_ibv_dev(rte_dev);
 	if (ibv == NULL)
@@ -146,7 +145,7 @@ mlx5_regex_dev_probe(struct rte_device *rte_dev)
 		DRV_LOG(ERR, "Unable to read HCA capabilities.");
 		rte_errno = ENOTSUP;
 		goto dev_error;
-	} else if (((!attr.regex) && (!attr.mmo_regex_sq_en) &&
+	} else if (((!attr.regexp_params) && (!attr.mmo_regex_sq_en) &&
 		(!attr.mmo_regex_qp_en)) || attr.regexp_num_of_engines == 0) {
 		DRV_LOG(ERR, "Not enough capabilities to support RegEx, maybe "
 			"old FW/OFED version?");
@@ -170,13 +169,7 @@ mlx5_regex_dev_probe(struct rte_device *rte_dev)
 	priv->qp_ts_format = attr.qp_ts_format;
 	priv->ctx = ctx;
 	priv->nb_engines = 2; /* attr.regexp_num_of_engines */
-	ret = mlx5_devx_regex_register_read(priv->ctx, 0,
-					    MLX5_RXP_CSR_IDENTIFIER, &val);
-	if (ret) {
-		DRV_LOG(ERR, "CSR read failed!");
-		goto dev_error;
-	}
-	if (val == MLX5_RXP_BF2_IDENTIFIER)
+	if (attr.regexp_version == MLX5_RXP_BF2_IDENTIFIER)
 		priv->is_bf2 = 1;
 	/* Default RXP programming mode to Shared. */
 	priv->prog_mode = MLX5_RXP_SHARED_PROG_MODE;
diff --git a/drivers/regex/mlx5/mlx5_rxp_csrs.h b/drivers/regex/mlx5/mlx5_rxp_csrs.h
index f3ffdfdef2..08cb6f3261 100644
--- a/drivers/regex/mlx5/mlx5_rxp_csrs.h
+++ b/drivers/regex/mlx5/mlx5_rxp_csrs.h
@@ -6,7 +6,7 @@
 #define _MLX5_RXP_CSRS_H_
 
 /* BF types */
-#define MLX5_RXP_BF2_IDENTIFIER 0x07055254ul
+#define MLX5_RXP_BF2_IDENTIFIER 0x0
 
 /*
  * Common to all RXP implementations
-- 
2.25.1

[dpdk-dev] [PATCH 02/10] regex/mlx5: add cleanup code

[Francis Kelly]

From: Ori Kam <orika@nvidia.com>

When stopping the device we should release all
data allocated.

This commit add this cleanup logic.

Signed-off-by: Ori Kam <orika@nvidia.com>
---
 drivers/regex/mlx5/mlx5_regex.c         | 14 ++++++++++++++
 drivers/regex/mlx5/mlx5_regex.h         |  1 +
 drivers/regex/mlx5/mlx5_regex_control.c | 20 ++++++++++++++++++++
 drivers/regex/mlx5/mlx5_rxp.c           |  4 ++--
 4 files changed, 37 insertions(+), 2 deletions(-)

diff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c
index 2124fd15f0..b7175ff8e9 100644
--- a/drivers/regex/mlx5/mlx5_regex.c
+++ b/drivers/regex/mlx5/mlx5_regex.c
@@ -48,6 +48,20 @@ mlx5_regex_start(struct rte_regexdev *dev __rte_unused)
 int
 mlx5_regex_stop(struct rte_regexdev *dev __rte_unused)
 {
+	struct mlx5_regex_priv *priv = dev->data->dev_private;
+	uint32_t i;
+
+	mlx5_regex_clean_ctrl(dev);
+	rte_free(priv->qps);
+	priv->qps = NULL;
+
+	for (i = 0; i < (priv->nb_engines + MLX5_RXP_EM_COUNT); i++) {
+		if (priv->db[i].umem.umem)
+			mlx5_glue->devx_umem_dereg(priv->db[i].umem.umem);
+		rte_free(priv->db[i].ptr);
+		priv->db[i].ptr = NULL;
+	}
+
 	return 0;
 }
 
diff --git a/drivers/regex/mlx5/mlx5_regex.h b/drivers/regex/mlx5/mlx5_regex.h
index 2242d250a3..329768980d 100644
--- a/drivers/regex/mlx5/mlx5_regex.h
+++ b/drivers/regex/mlx5/mlx5_regex.h
@@ -125,6 +125,7 @@ int mlx5_devx_regex_database_program(void *ctx, uint8_t engine,
 /* mlx5_regex_control.c */
 int mlx5_regex_qp_setup(struct rte_regexdev *dev, uint16_t qp_ind,
 			const struct rte_regexdev_qp_conf *cfg);
+void mlx5_regex_clean_ctrl(struct rte_regexdev *dev);
 
 /* mlx5_regex_fastpath.c */
 int mlx5_regexdev_setup_fastpath(struct mlx5_regex_priv *priv, uint32_t qp_id);
diff --git a/drivers/regex/mlx5/mlx5_regex_control.c b/drivers/regex/mlx5/mlx5_regex_control.c
index 572ecc6d86..1783df923c 100644
--- a/drivers/regex/mlx5/mlx5_regex_control.c
+++ b/drivers/regex/mlx5/mlx5_regex_control.c
@@ -271,3 +271,23 @@ mlx5_regex_qp_setup(struct rte_regexdev *dev, uint16_t qp_ind,
 	rte_free(qp->qps);
 	return ret;
 }
+
+void
+mlx5_regex_clean_ctrl(struct rte_regexdev *dev)
+{
+	struct mlx5_regex_priv *priv = dev->data->dev_private;
+	struct mlx5_regex_qp *qp;
+	int qp_ind;
+	int i;
+
+	if (!priv->qps)
+		return;
+	for (qp_ind = 0; qp_ind < priv->nb_queues; qp_ind++) {
+		qp = &priv->qps[qp_ind];
+		mlx5_regexdev_teardown_fastpath(priv, qp_ind);
+		mlx5_mr_btree_free(&qp->mr_ctrl.cache_bh);
+		for (i = 0; i < qp->nb_obj; i++)
+			regex_ctrl_destroy_hw_qp(qp, i);
+		regex_ctrl_destroy_cq(&qp->cq);
+	}
+}
diff --git a/drivers/regex/mlx5/mlx5_rxp.c b/drivers/regex/mlx5/mlx5_rxp.c
index 380037e24c..5afdcb35cc 100644
--- a/drivers/regex/mlx5/mlx5_rxp.c
+++ b/drivers/regex/mlx5/mlx5_rxp.c
@@ -776,10 +776,10 @@ rxp_db_setup(struct mlx5_regex_priv *priv)
 	return 0;
 tidyup_error:
 	for (i = 0; i < (priv->nb_engines + MLX5_RXP_EM_COUNT); i++) {
-		if (priv->db[i].ptr)
-			rte_free(priv->db[i].ptr);
 		if (priv->db[i].umem.umem)
 			mlx5_glue->devx_umem_dereg(priv->db[i].umem.umem);
+		rte_free(priv->db[i].ptr);
+		priv->db[i].ptr = NULL;
 	}
 	return -ret;
 }
-- 
2.25.1

[dpdk-dev] [PATCH 03/10] common/mlx5: update regex DevX commands

[Francis Kelly]

From: Ady Agbarih <adypodoman@gmail.com>

This patch modifies the SET_REGEXP_PARAMS devx command as follows:
  Remove DB setup devx command. The command is no longer needed
    in DPDK, it will always be invoked by the regex-daemon.
  Add new devx command, for programming rof rules for a specific
    engine. The command takes as an input an mkey of the rof.
    It also introduces a new field_select bit.

Signed-off-by: Ady Agbarih <adypodoman@gmail.com>
---
 drivers/common/mlx5/mlx5_prm.h       | 13 ++++++++-----
 drivers/regex/mlx5/mlx5_regex.c      |  9 +++------
 drivers/regex/mlx5/mlx5_regex.h      |  4 ++--
 drivers/regex/mlx5/mlx5_regex_devx.c | 15 ++++++++-------
 drivers/regex/mlx5/mlx5_rxp.c        | 27 ---------------------------
 5 files changed, 21 insertions(+), 47 deletions(-)

diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 8b0f2f1a89..fb75f2da4d 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -3710,17 +3710,20 @@ struct mlx5_ifc_parse_graph_flex_out_bits {
 };
 
 struct regexp_params_field_select_bits {
-	u8 reserved_at_0[0x1e];
+	u8 reserved_at_0[0x1d];
+	u8 rof_mkey[0x1];
 	u8 stop_engine[0x1];
-	u8 db_umem_id[0x1];
+	u8 reserved_at_1f[0x1];
 };
 
 struct mlx5_ifc_regexp_params_bits {
 	u8 reserved_at_0[0x1f];
 	u8 stop_engine[0x1];
-	u8 db_umem_id[0x20];
-	u8 db_umem_offset[0x40];
-	u8 reserved_at_80[0x100];
+	u8 reserved_at_20[0x60];
+	u8 rof_mkey[0x20];
+	u8 rof_size[0x20];
+	u8 rof_mkey_va[0x40];
+	u8 reserved_at_100[0x80];
 };
 
 struct mlx5_ifc_set_regexp_params_in_bits {
diff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c
index b7175ff8e9..4be36e40c5 100644
--- a/drivers/regex/mlx5/mlx5_regex.c
+++ b/drivers/regex/mlx5/mlx5_regex.c
@@ -55,12 +55,9 @@ mlx5_regex_stop(struct rte_regexdev *dev __rte_unused)
 	rte_free(priv->qps);
 	priv->qps = NULL;
 
-	for (i = 0; i < (priv->nb_engines + MLX5_RXP_EM_COUNT); i++) {
-		if (priv->db[i].umem.umem)
-			mlx5_glue->devx_umem_dereg(priv->db[i].umem.umem);
-		rte_free(priv->db[i].ptr);
-		priv->db[i].ptr = NULL;
-	}
+	for (i = 0; i < priv->nb_engines; i++)
+		/* Stop engine. */
+		mlx5_devx_regex_database_stop(priv->ctx, i);
 
 	return 0;
 }
diff --git a/drivers/regex/mlx5/mlx5_regex.h b/drivers/regex/mlx5/mlx5_regex.h
index 329768980d..c9586ae714 100644
--- a/drivers/regex/mlx5/mlx5_regex.h
+++ b/drivers/regex/mlx5/mlx5_regex.h
@@ -119,8 +119,8 @@ int mlx5_devx_regex_register_read(struct ibv_context *ctx, int engine_id,
 				  uint32_t addr, uint32_t *data);
 int mlx5_devx_regex_database_stop(void *ctx, uint8_t engine);
 int mlx5_devx_regex_database_resume(void *ctx, uint8_t engine);
-int mlx5_devx_regex_database_program(void *ctx, uint8_t engine,
-				     uint32_t umem_id, uint64_t umem_offset);
+int mlx5_devx_regex_rules_program(void *ctx, uint8_t engine, uint32_t rof_mkey,
+				uint32_t rof_size, uint64_t db_mkey_offset);
 
 /* mlx5_regex_control.c */
 int mlx5_regex_qp_setup(struct rte_regexdev *dev, uint16_t qp_ind,
diff --git a/drivers/regex/mlx5/mlx5_regex_devx.c b/drivers/regex/mlx5/mlx5_regex_devx.c
index f66d7aa08b..d8515768c3 100644
--- a/drivers/regex/mlx5/mlx5_regex_devx.c
+++ b/drivers/regex/mlx5/mlx5_regex_devx.c
@@ -103,8 +103,8 @@ mlx5_devx_regex_database_resume(void *ctx, uint8_t engine)
 }
 
 int
-mlx5_devx_regex_database_program(void *ctx, uint8_t engine, uint32_t umem_id,
-				 uint64_t umem_offset)
+mlx5_devx_regex_rules_program(void *ctx, uint8_t engine, uint32_t rof_mkey,
+				uint32_t rof_size, uint64_t rof_mkey_va)
 {
 	uint32_t out[MLX5_ST_SZ_DW(set_regexp_params_out)] = {0};
 	uint32_t in[MLX5_ST_SZ_DW(set_regexp_params_in)] = {0};
@@ -112,14 +112,15 @@ mlx5_devx_regex_database_program(void *ctx, uint8_t engine, uint32_t umem_id,
 
 	MLX5_SET(set_regexp_params_in, in, opcode, MLX5_CMD_SET_REGEX_PARAMS);
 	MLX5_SET(set_regexp_params_in, in, engine_id, engine);
-	MLX5_SET(set_regexp_params_in, in, regexp_params.db_umem_id, umem_id);
-	MLX5_SET64(set_regexp_params_in, in, regexp_params.db_umem_offset,
-		   umem_offset);
-	MLX5_SET(set_regexp_params_in, in, field_select.db_umem_id, 1);
+	MLX5_SET(set_regexp_params_in, in, regexp_params.rof_mkey, rof_mkey);
+	MLX5_SET(set_regexp_params_in, in, regexp_params.rof_size, rof_size);
+	MLX5_SET64(set_regexp_params_in, in, regexp_params.rof_mkey_va,
+		   rof_mkey_va);
+	MLX5_SET(set_regexp_params_in, in, field_select.rof_mkey, 1);
 	ret = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
 					  sizeof(out));
 	if (ret) {
-		DRV_LOG(ERR, "Database program failed %d", ret);
+		DRV_LOG(ERR, "Rules program failed %d", ret);
 		rte_errno = errno;
 		return -errno;
 	}
diff --git a/drivers/regex/mlx5/mlx5_rxp.c b/drivers/regex/mlx5/mlx5_rxp.c
index 5afdcb35cc..79f063a127 100644
--- a/drivers/regex/mlx5/mlx5_rxp.c
+++ b/drivers/regex/mlx5/mlx5_rxp.c
@@ -33,8 +33,6 @@ rxp_poll_csr_for_value(struct ibv_context *ctx, uint32_t *value,
 		       uint32_t address, uint32_t expected_value,
 		       uint32_t expected_mask, uint32_t timeout_ms, uint8_t id);
 static int
-mlnx_set_database(struct mlx5_regex_priv *priv, uint8_t id, uint8_t db_to_use);
-static int
 mlnx_resume_database(struct mlx5_regex_priv *priv, uint8_t id);
 static int
 mlnx_update_database(struct mlx5_regex_priv *priv, uint8_t id);
@@ -488,11 +486,6 @@ rxp_program_rof(struct mlx5_regex_priv *priv, const char *buf, uint32_t len,
 		}
 
 	}
-	ret = mlnx_set_database(priv, id, db_free);
-	if (ret < 0) {
-		DRV_LOG(ERR, "Failed to register db memory!");
-		goto parse_error;
-	}
 	rte_free(tmp);
 	return 0;
 parse_error:
@@ -500,26 +493,6 @@ rxp_program_rof(struct mlx5_regex_priv *priv, const char *buf, uint32_t len,
 	return ret;
 }
 
-static int
-mlnx_set_database(struct mlx5_regex_priv *priv, uint8_t id, uint8_t db_to_use)
-{
-	int ret;
-	uint32_t umem_id;
-
-	ret = mlx5_devx_regex_database_stop(priv->ctx, id);
-	if (ret < 0) {
-		DRV_LOG(ERR, "stop engine failed!");
-		return ret;
-	}
-	umem_id = mlx5_os_get_umem_id(priv->db[db_to_use].umem.umem);
-	ret = mlx5_devx_regex_database_program(priv->ctx, id, umem_id, 0);
-	if (ret < 0) {
-		DRV_LOG(ERR, "program db failed!");
-		return ret;
-	}
-	return 0;
-}
-
 static int
 mlnx_resume_database(struct mlx5_regex_priv *priv, uint8_t id)
 {
-- 
2.25.1

Re: [dpdk-dev] [PATCH 03/10] common/mlx5: update regex DevX commands

[Ori Kam]

Hi Francis,

> -----Original Message-----
> From: Francis Kelly <fkelly@nvidia.com>
> Sent: Friday, October 22, 2021 6:46 PM
> Subject: [PATCH 03/10] common/mlx5: update regex DevX commands
> 
> From: Ady Agbarih <adypodoman@gmail.com>
> 
> This patch modifies the SET_REGEXP_PARAMS devx command as follows:
>   Remove DB setup devx command. The command is no longer needed
>     in DPDK, it will always be invoked by the regex-daemon.
>   Add new devx command, for programming rof rules for a specific
>     engine. The command takes as an input an mkey of the rof.
>     It also introduces a new field_select bit.
> 
> Signed-off-by: Ady Agbarih <adypodoman@gmail.com>
> ---

Acked-by: Ori Kam <orika@nvidia.com>
Best,
Ori

[dpdk-dev] [PATCH 04/10] regex/mlx5: remove regexp register read/write

[Francis Kelly]

From: Ady Agbarih <adypodoman@gmail.com>

Remove the set/query regexp register commands from devx.
Remove functions that used these commands.
Remove manual rules programming.

Signed-off-by: Ady Agbarih <adypodoman@gmail.com>
---
 drivers/regex/mlx5/mlx5_regex.c      |  28 --
 drivers/regex/mlx5/mlx5_regex.h      |   4 -
 drivers/regex/mlx5/mlx5_regex_devx.c |  48 --
 drivers/regex/mlx5/mlx5_rxp.c        | 708 +--------------------------
 4 files changed, 1 insertion(+), 787 deletions(-)

diff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c
index 4be36e40c5..f9eb3a2fab 100644
--- a/drivers/regex/mlx5/mlx5_regex.c
+++ b/drivers/regex/mlx5/mlx5_regex.c
@@ -68,29 +68,6 @@ mlx5_regex_close(struct rte_regexdev *dev __rte_unused)
 	return 0;
 }
 
-static int
-mlx5_regex_engines_status(struct ibv_context *ctx, int num_engines)
-{
-	uint32_t fpga_ident = 0;
-	int err;
-	int i;
-
-	for (i = 0; i < num_engines; i++) {
-		err = mlx5_devx_regex_register_read(ctx, i,
-						    MLX5_RXP_CSR_IDENTIFIER,
-						    &fpga_ident);
-		fpga_ident = (fpga_ident & (0x0000FFFF));
-		if (err || fpga_ident != MLX5_RXP_IDENTIFIER) {
-			DRV_LOG(ERR, "Failed setup RXP %d err %d database "
-				"memory 0x%x", i, err, fpga_ident);
-			if (!err)
-				err = EINVAL;
-			return err;
-		}
-	}
-	return 0;
-}
-
 static void
 mlx5_regex_get_name(char *name, struct rte_device *dev)
 {
@@ -163,11 +140,6 @@ mlx5_regex_dev_probe(struct rte_device *rte_dev)
 		rte_errno = ENOTSUP;
 		goto dev_error;
 	}
-	if (mlx5_regex_engines_status(ctx, 2)) {
-		DRV_LOG(ERR, "RegEx engine error.");
-		rte_errno = ENOMEM;
-		goto dev_error;
-	}
 	priv = rte_zmalloc("mlx5 regex device private", sizeof(*priv),
 			   RTE_CACHE_LINE_SIZE);
 	if (!priv) {
diff --git a/drivers/regex/mlx5/mlx5_regex.h b/drivers/regex/mlx5/mlx5_regex.h
index c9586ae714..09b360a1ab 100644
--- a/drivers/regex/mlx5/mlx5_regex.h
+++ b/drivers/regex/mlx5/mlx5_regex.h
@@ -113,10 +113,6 @@ int mlx5_regex_rules_db_import(struct rte_regexdev *dev,
 			       const char *rule_db, uint32_t rule_db_len);
 
 /* mlx5_regex_devx.c */
-int mlx5_devx_regex_register_write(struct ibv_context *ctx, int engine_id,
-				   uint32_t addr, uint32_t data);
-int mlx5_devx_regex_register_read(struct ibv_context *ctx, int engine_id,
-				  uint32_t addr, uint32_t *data);
 int mlx5_devx_regex_database_stop(void *ctx, uint8_t engine);
 int mlx5_devx_regex_database_resume(void *ctx, uint8_t engine);
 int mlx5_devx_regex_rules_program(void *ctx, uint8_t engine, uint32_t rof_mkey,
diff --git a/drivers/regex/mlx5/mlx5_regex_devx.c b/drivers/regex/mlx5/mlx5_regex_devx.c
index d8515768c3..262f301121 100644
--- a/drivers/regex/mlx5/mlx5_regex_devx.c
+++ b/drivers/regex/mlx5/mlx5_regex_devx.c
@@ -12,54 +12,6 @@
 #include "mlx5_regex.h"
 #include "mlx5_regex_utils.h"
 
-int
-mlx5_devx_regex_register_write(struct ibv_context *ctx, int engine_id,
-			       uint32_t addr, uint32_t data)
-{
-	uint32_t out[MLX5_ST_SZ_DW(set_regexp_register_out)] = {0};
-	uint32_t in[MLX5_ST_SZ_DW(set_regexp_register_in)] = {0};
-	int ret;
-
-	MLX5_SET(set_regexp_register_in, in, opcode,
-		 MLX5_CMD_SET_REGEX_REGISTERS);
-	MLX5_SET(set_regexp_register_in, in, engine_id, engine_id);
-	MLX5_SET(set_regexp_register_in, in, register_address, addr);
-	MLX5_SET(set_regexp_register_in, in, register_data, data);
-
-	ret = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
-					  sizeof(out));
-	if (ret) {
-		DRV_LOG(ERR, "Set regexp register failed %d", ret);
-		rte_errno = errno;
-		return -errno;
-	}
-	return 0;
-}
-
-int
-mlx5_devx_regex_register_read(struct ibv_context *ctx, int engine_id,
-			      uint32_t addr, uint32_t *data)
-{
-	uint32_t out[MLX5_ST_SZ_DW(query_regexp_register_out)] = {0};
-	uint32_t in[MLX5_ST_SZ_DW(query_regexp_register_in)] = {0};
-	int ret;
-
-	MLX5_SET(query_regexp_register_in, in, opcode,
-		 MLX5_CMD_QUERY_REGEX_REGISTERS);
-	MLX5_SET(query_regexp_register_in, in, engine_id, engine_id);
-	MLX5_SET(query_regexp_register_in, in, register_address, addr);
-
-	ret = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
-					  sizeof(out));
-	if (ret) {
-		DRV_LOG(ERR, "Query regexp register failed %d", ret);
-		rte_errno = errno;
-		return -errno;
-	}
-	*data = MLX5_GET(query_regexp_register_out, out, register_data);
-	return 0;
-}
-
 int
 mlx5_devx_regex_database_stop(void *ctx, uint8_t engine)
 {
diff --git a/drivers/regex/mlx5/mlx5_rxp.c b/drivers/regex/mlx5/mlx5_rxp.c
index 79f063a127..8f54ab018e 100644
--- a/drivers/regex/mlx5/mlx5_rxp.c
+++ b/drivers/regex/mlx5/mlx5_rxp.c
@@ -28,71 +28,6 @@
 #define MLX5_REGEX_RXP_ROF2_LINE_LEN 34
 
 /* Private Declarations */
-static int
-rxp_poll_csr_for_value(struct ibv_context *ctx, uint32_t *value,
-		       uint32_t address, uint32_t expected_value,
-		       uint32_t expected_mask, uint32_t timeout_ms, uint8_t id);
-static int
-mlnx_resume_database(struct mlx5_regex_priv *priv, uint8_t id);
-static int
-mlnx_update_database(struct mlx5_regex_priv *priv, uint8_t id);
-static int
-program_rxp_rules(struct mlx5_regex_priv *priv, const char *buf, uint32_t len,
-		  uint8_t id);
-static int
-rxp_init_eng(struct mlx5_regex_priv *priv, uint8_t id);
-static int
-rxp_db_setup(struct mlx5_regex_priv *priv);
-static void
-rxp_dump_csrs(struct ibv_context *ctx, uint8_t id);
-static int
-rxp_start_engine(struct ibv_context *ctx, uint8_t id);
-static int
-rxp_stop_engine(struct ibv_context *ctx, uint8_t id);
-
-static void __rte_unused
-rxp_dump_csrs(struct ibv_context *ctx __rte_unused, uint8_t id __rte_unused)
-{
-	uint32_t reg, i;
-
-	/* Main CSRs*/
-	for (i = 0; i < MLX5_RXP_CSR_NUM_ENTRIES; i++) {
-		if (mlx5_devx_regex_register_read(ctx, id,
-						  (MLX5_RXP_CSR_WIDTH * i) +
-						  MLX5_RXP_CSR_BASE_ADDRESS,
-						  &reg)) {
-			DRV_LOG(ERR, "Failed to read Main CSRs Engine %d!", id);
-			return;
-		}
-		DRV_LOG(DEBUG, "RXP Main CSRs (Eng%d) register (%d): %08x",
-			id, i, reg);
-	}
-	/* RTRU CSRs*/
-	for (i = 0; i < MLX5_RXP_CSR_NUM_ENTRIES; i++) {
-		if (mlx5_devx_regex_register_read(ctx, id,
-						  (MLX5_RXP_CSR_WIDTH * i) +
-						 MLX5_RXP_RTRU_CSR_BASE_ADDRESS,
-						  &reg)) {
-			DRV_LOG(ERR, "Failed to read RTRU CSRs Engine %d!", id);
-			return;
-		}
-		DRV_LOG(DEBUG, "RXP RTRU CSRs (Eng%d) register (%d): %08x",
-			id, i, reg);
-	}
-	/* STAT CSRs */
-	for (i = 0; i < MLX5_RXP_CSR_NUM_ENTRIES; i++) {
-		if (mlx5_devx_regex_register_read(ctx, id,
-						  (MLX5_RXP_CSR_WIDTH * i) +
-						MLX5_RXP_STATS_CSR_BASE_ADDRESS,
-						  &reg)) {
-			DRV_LOG(ERR, "Failed to read STAT CSRs Engine %d!", id);
-			return;
-		}
-		DRV_LOG(DEBUG, "RXP STAT CSRs (Eng%d) register (%d): %08x",
-			id, i, reg);
-	}
-}
-
 int
 mlx5_regex_info_get(struct rte_regexdev *dev __rte_unused,
 		    struct rte_regexdev_info *info)
@@ -108,614 +43,6 @@ mlx5_regex_info_get(struct rte_regexdev *dev __rte_unused,
 	return 0;
 }
 
-static int
-rxp_poll_csr_for_value(struct ibv_context *ctx, uint32_t *value,
-		       uint32_t address, uint32_t expected_value,
-		       uint32_t expected_mask, uint32_t timeout_ms, uint8_t id)
-{
-	unsigned int i;
-	int ret;
-
-	ret = -EBUSY;
-	for (i = 0; i < timeout_ms; i++) {
-		if (mlx5_devx_regex_register_read(ctx, id, address, value))
-			return -1;
-		if ((*value & expected_mask) == expected_value) {
-			ret = 0;
-			break;
-		}
-		rte_delay_us(1000);
-	}
-	return ret;
-}
-
-static int
-rxp_start_engine(struct ibv_context *ctx, uint8_t id)
-{
-	uint32_t ctrl;
-	int ret;
-
-	ret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CTRL, &ctrl);
-	if (ret)
-		return ret;
-	ctrl |= MLX5_RXP_CSR_CTRL_GO;
-	ctrl |= MLX5_RXP_CSR_CTRL_DISABLE_L2C;
-	ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL, ctrl);
-	return ret;
-}
-
-static int
-rxp_stop_engine(struct ibv_context *ctx, uint8_t id)
-{
-	uint32_t ctrl;
-	int ret;
-
-	ret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CTRL, &ctrl);
-	if (ret)
-		return ret;
-	ctrl &= ~MLX5_RXP_CSR_CTRL_GO;
-	ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL, ctrl);
-	return ret;
-}
-
-static int
-rxp_init_rtru(struct mlx5_regex_priv *priv, uint8_t id, uint32_t init_bits)
-{
-	uint32_t ctrl_value;
-	uint32_t poll_value;
-	uint32_t expected_value;
-	uint32_t expected_mask;
-	struct ibv_context *ctx = priv->ctx;
-	int ret = 0;
-
-	/* Read the rtru ctrl CSR. */
-	ret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
-					    &ctrl_value);
-	if (ret)
-		return -1;
-	/* Clear any previous init modes. */
-	ctrl_value &= ~(MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_MASK);
-	if (ctrl_value & MLX5_RXP_RTRU_CSR_CTRL_INIT) {
-		ctrl_value &= ~(MLX5_RXP_RTRU_CSR_CTRL_INIT);
-		mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
-					       ctrl_value);
-	}
-	/* Set the init_mode bits in the rtru ctrl CSR. */
-	ctrl_value |= init_bits;
-	mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
-				       ctrl_value);
-	/* Need to sleep for a short period after pulsing the rtru init bit. */
-	rte_delay_us(20000);
-	/* Poll the rtru status CSR until all the init done bits are set. */
-	DRV_LOG(DEBUG, "waiting for RXP rule memory to complete init");
-	/* Set the init bit in the rtru ctrl CSR. */
-	ctrl_value |= MLX5_RXP_RTRU_CSR_CTRL_INIT;
-	mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
-				       ctrl_value);
-	/* Clear the init bit in the rtru ctrl CSR */
-	ctrl_value &= ~MLX5_RXP_RTRU_CSR_CTRL_INIT;
-	mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
-				       ctrl_value);
-	/* Check that the following bits are set in the RTRU_CSR. */
-	if (init_bits == MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_L1_L2) {
-		/* Must be incremental mode */
-		expected_value = MLX5_RXP_RTRU_CSR_STATUS_L1C_INIT_DONE;
-	} else {
-		expected_value = MLX5_RXP_RTRU_CSR_STATUS_IM_INIT_DONE |
-			MLX5_RXP_RTRU_CSR_STATUS_L1C_INIT_DONE;
-	}
-	if (priv->is_bf2)
-		expected_value |= MLX5_RXP_RTRU_CSR_STATUS_L2C_INIT_DONE;
-
-
-	expected_mask = expected_value;
-	ret = rxp_poll_csr_for_value(ctx, &poll_value,
-				     MLX5_RXP_RTRU_CSR_STATUS,
-				     expected_value, expected_mask,
-				     MLX5_RXP_CSR_STATUS_TRIAL_TIMEOUT, id);
-	if (ret)
-		return ret;
-	DRV_LOG(DEBUG, "rule memory initialise: 0x%08X", poll_value);
-	/* Clear the init bit in the rtru ctrl CSR */
-	ctrl_value &= ~(MLX5_RXP_RTRU_CSR_CTRL_INIT);
-	mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
-				       ctrl_value);
-	return 0;
-}
-
-static int
-rxp_parse_line(char *line, uint32_t *type, uint32_t *address, uint64_t *value)
-{
-	char *cur_pos;
-
-	if (*line == '\0' || *line == '#')
-		return  1;
-	*type = strtoul(line, &cur_pos, 10);
-	if (*cur_pos != ',' && *cur_pos != '\0')
-		return -1;
-	*address = strtoul(cur_pos+1, &cur_pos, 16);
-	if (*cur_pos != ',' && *cur_pos != '\0')
-		return -1;
-	*value = strtoul(cur_pos+1, &cur_pos, 16);
-	if (*cur_pos != ',' && *cur_pos != '\0')
-		return -1;
-	return 0;
-}
-
-static uint32_t
-rxp_get_reg_address(uint32_t address)
-{
-	uint32_t block;
-	uint32_t reg;
-
-	block = (address >> 16) & 0xFFFF;
-	if (block == 0)
-		reg = MLX5_RXP_CSR_BASE_ADDRESS;
-	else if (block == 1)
-		reg = MLX5_RXP_RTRU_CSR_BASE_ADDRESS;
-	else {
-		DRV_LOG(ERR, "Invalid ROF register 0x%08X!", address);
-			return UINT32_MAX;
-	}
-	reg += (address & 0xFFFF) * MLX5_RXP_CSR_WIDTH;
-	return reg;
-}
-
-#define MLX5_RXP_NUM_LINES_PER_BLOCK 8
-
-static int
-rxp_program_rof(struct mlx5_regex_priv *priv, const char *buf, uint32_t len,
-		uint8_t id)
-{
-	static const char del[] = "\n\r";
-	char *line;
-	char *tmp;
-	uint32_t type = 0;
-	uint32_t address;
-	uint64_t val;
-	uint32_t reg_val;
-	int ret;
-	int skip = -1;
-	int last = 0;
-	uint32_t temp;
-	uint32_t tmp_addr;
-	uint32_t rof_rule_addr;
-	uint64_t tmp_write_swap[4];
-	struct mlx5_rxp_rof_entry rules[8];
-	int i;
-	int db_free;
-	int j;
-
-	tmp = rte_malloc("", len, 0);
-	if (!tmp)
-		return -ENOMEM;
-	memcpy(tmp, buf, len);
-	db_free = mlnx_update_database(priv, id);
-	if (db_free < 0) {
-		DRV_LOG(ERR, "Failed to setup db memory!");
-		rte_free(tmp);
-		return db_free;
-	}
-	for (line = strtok(tmp, del), j = 0; line; line = strtok(NULL, del),
-	     j++, last = type) {
-		ret = rxp_parse_line(line, &type, &address, &val);
-		if (ret != 0) {
-			if (ret < 0)
-				goto parse_error;
-			continue;
-		}
-		switch (type) {
-		case MLX5_RXP_ROF_ENTRY_EQ:
-			if (skip == 0 && address == 0)
-				skip = 1;
-			tmp_addr = rxp_get_reg_address(address);
-			if (tmp_addr == UINT32_MAX)
-				goto parse_error;
-			ret = mlx5_devx_regex_register_read(priv->ctx, id,
-							    tmp_addr, &reg_val);
-			if (ret)
-				goto parse_error;
-			if (skip == -1 && address == 0) {
-				if (val == reg_val) {
-					skip = 0;
-					continue;
-				}
-			} else if (skip == 0) {
-				if (val != reg_val) {
-					DRV_LOG(ERR,
-						"got %08X expected == %" PRIx64,
-						reg_val, val);
-					goto parse_error;
-				}
-			}
-			break;
-		case MLX5_RXP_ROF_ENTRY_GTE:
-			if (skip == 0 && address == 0)
-				skip = 1;
-			tmp_addr = rxp_get_reg_address(address);
-			if (tmp_addr == UINT32_MAX)
-				goto parse_error;
-			ret = mlx5_devx_regex_register_read(priv->ctx, id,
-							    tmp_addr, &reg_val);
-			if (ret)
-				goto parse_error;
-			if (skip == -1 && address == 0) {
-				if (reg_val >= val) {
-					skip = 0;
-					continue;
-				}
-			} else if (skip == 0) {
-				if (reg_val < val) {
-					DRV_LOG(ERR,
-						"got %08X expected >= %" PRIx64,
-						reg_val, val);
-					goto parse_error;
-				}
-			}
-			break;
-		case MLX5_RXP_ROF_ENTRY_LTE:
-			tmp_addr = rxp_get_reg_address(address);
-			if (tmp_addr == UINT32_MAX)
-				goto parse_error;
-			ret = mlx5_devx_regex_register_read(priv->ctx, id,
-							    tmp_addr, &reg_val);
-			if (ret)
-				goto parse_error;
-			if (skip == 0 && address == 0 &&
-			    last != MLX5_RXP_ROF_ENTRY_GTE) {
-				skip = 1;
-			} else if (skip == 0 && address == 0 &&
-				   last == MLX5_RXP_ROF_ENTRY_GTE) {
-				if (reg_val > val)
-					skip = -1;
-				continue;
-			}
-			if (skip == -1 && address == 0) {
-				if (reg_val <= val) {
-					skip = 0;
-					continue;
-				}
-			} else if (skip == 0) {
-				if (reg_val > val) {
-					DRV_LOG(ERR,
-						"got %08X expected <= %" PRIx64,
-						reg_val, val);
-					goto parse_error;
-				}
-			}
-			break;
-		case MLX5_RXP_ROF_ENTRY_CHECKSUM:
-			break;
-		case MLX5_RXP_ROF_ENTRY_CHECKSUM_EX_EM:
-			if (skip)
-				continue;
-			tmp_addr = rxp_get_reg_address(address);
-			if (tmp_addr == UINT32_MAX)
-				goto parse_error;
-
-			ret = mlx5_devx_regex_register_read(priv->ctx, id,
-							    tmp_addr, &reg_val);
-			if (ret) {
-				DRV_LOG(ERR, "RXP CSR read failed!");
-				return ret;
-			}
-			if (reg_val != val) {
-				DRV_LOG(ERR, "got %08X expected <= %" PRIx64,
-					reg_val, val);
-				goto parse_error;
-			}
-			break;
-		case MLX5_RXP_ROF_ENTRY_IM:
-			if (skip)
-				continue;
-			/*
-			 * NOTE: All rules written to RXP must be carried out in
-			 * triplets of: 2xData + 1xAddr.
-			 * No optimisation is currently allowed in this
-			 * sequence to perform less writes.
-			 */
-			temp = val;
-			ret |= mlx5_devx_regex_register_write
-					(priv->ctx, id,
-					 MLX5_RXP_RTRU_CSR_DATA_0, temp);
-			temp = (uint32_t)(val >> 32);
-			ret |= mlx5_devx_regex_register_write
-					(priv->ctx, id,
-					 MLX5_RXP_RTRU_CSR_DATA_0 +
-					 MLX5_RXP_CSR_WIDTH, temp);
-			temp = address;
-			ret |= mlx5_devx_regex_register_write
-					(priv->ctx, id, MLX5_RXP_RTRU_CSR_ADDR,
-					 temp);
-			if (ret) {
-				DRV_LOG(ERR,
-					"Failed to copy instructions to RXP.");
-				goto parse_error;
-			}
-			break;
-		case MLX5_RXP_ROF_ENTRY_EM:
-			if (skip)
-				continue;
-			for (i = 0; i < MLX5_RXP_NUM_LINES_PER_BLOCK; i++) {
-				ret = rxp_parse_line(line, &type,
-						     &rules[i].addr,
-						     &rules[i].value);
-				if (ret != 0)
-					goto parse_error;
-				if (i < (MLX5_RXP_NUM_LINES_PER_BLOCK - 1)) {
-					line = strtok(NULL, del);
-					if (!line)
-						goto parse_error;
-				}
-			}
-			if ((uint8_t *)((uint8_t *)
-					priv->db[id].ptr +
-					((rules[7].addr <<
-					 MLX5_RXP_INST_OFFSET))) >=
-					((uint8_t *)((uint8_t *)
-					priv->db[id].ptr + MLX5_MAX_DB_SIZE))) {
-				DRV_LOG(ERR, "DB exceeded memory!");
-				goto parse_error;
-			}
-			/*
-			 * Rule address Offset to align with RXP
-			 * external instruction offset.
-			 */
-			rof_rule_addr = (rules[0].addr << MLX5_RXP_INST_OFFSET);
-			/* 32 byte instruction swap (sw work around)! */
-			tmp_write_swap[0] = le64toh(rules[4].value);
-			tmp_write_swap[1] = le64toh(rules[5].value);
-			tmp_write_swap[2] = le64toh(rules[6].value);
-			tmp_write_swap[3] = le64toh(rules[7].value);
-			/* Write only 4 of the 8 instructions. */
-			memcpy((uint8_t *)((uint8_t *)
-				priv->db[id].ptr + rof_rule_addr),
-				&tmp_write_swap, (sizeof(uint64_t) * 4));
-			/* Write 1st 4 rules of block after last 4. */
-			rof_rule_addr = (rules[4].addr << MLX5_RXP_INST_OFFSET);
-			tmp_write_swap[0] = le64toh(rules[0].value);
-			tmp_write_swap[1] = le64toh(rules[1].value);
-			tmp_write_swap[2] = le64toh(rules[2].value);
-			tmp_write_swap[3] = le64toh(rules[3].value);
-			memcpy((uint8_t *)((uint8_t *)
-				priv->db[id].ptr + rof_rule_addr),
-				&tmp_write_swap, (sizeof(uint64_t) * 4));
-			break;
-		default:
-			break;
-		}
-
-	}
-	rte_free(tmp);
-	return 0;
-parse_error:
-	rte_free(tmp);
-	return ret;
-}
-
-static int
-mlnx_resume_database(struct mlx5_regex_priv *priv, uint8_t id)
-{
-	mlx5_devx_regex_database_resume(priv->ctx, id);
-	return 0;
-}
-
-/*
- * Assign db memory for RXP programming.
- */
-static int
-mlnx_update_database(struct mlx5_regex_priv *priv, uint8_t id)
-{
-	unsigned int i;
-	uint8_t db_free = MLX5_RXP_DB_NOT_ASSIGNED;
-	uint8_t eng_assigned = MLX5_RXP_DB_NOT_ASSIGNED;
-
-	/* Check which database rxp_eng is currently located if any? */
-	for (i = 0; i < (priv->nb_engines + MLX5_RXP_EM_COUNT);
-	     i++) {
-		if (priv->db[i].db_assigned_to_eng_num == id) {
-			eng_assigned = i;
-			break;
-		}
-	}
-	/*
-	 * If private mode then, we can keep the same db ptr as RXP will be
-	 * programming EM itself if necessary, however need to see if
-	 * programmed yet.
-	 */
-	if ((priv->prog_mode == MLX5_RXP_PRIVATE_PROG_MODE) &&
-	    (eng_assigned != MLX5_RXP_DB_NOT_ASSIGNED))
-		return eng_assigned;
-	/* Check for inactive db memory to use. */
-	for (i = 0; i < (priv->nb_engines + MLX5_RXP_EM_COUNT);
-	     i++) {
-		if (priv->db[i].active == true)
-			continue; /* Already in use, so skip db. */
-		/* Set this db to active now as free to use. */
-		priv->db[i].active = true;
-		/* Now unassign last db index in use by RXP Eng. */
-		if (eng_assigned != MLX5_RXP_DB_NOT_ASSIGNED) {
-			priv->db[eng_assigned].active = false;
-			priv->db[eng_assigned].db_assigned_to_eng_num =
-				MLX5_RXP_DB_NOT_ASSIGNED;
-
-			/* Set all DB memory to 0's before setting up DB. */
-			memset(priv->db[i].ptr, 0x00, MLX5_MAX_DB_SIZE);
-		}
-		/* Now reassign new db index with RXP Engine. */
-		priv->db[i].db_assigned_to_eng_num = id;
-		db_free = i;
-		break;
-	}
-	if (db_free == MLX5_RXP_DB_NOT_ASSIGNED)
-		return -1;
-	return db_free;
-}
-
-/*
- * Program RXP instruction db to RXP engine/s.
- */
-static int
-program_rxp_rules(struct mlx5_regex_priv *priv, const char *buf, uint32_t len,
-		  uint8_t id)
-{
-	int ret;
-	uint32_t val;
-
-	ret = rxp_init_eng(priv, id);
-	if (ret < 0)
-		return ret;
-	/* Confirm the RXP is initialised. */
-	if (mlx5_devx_regex_register_read(priv->ctx, id,
-					    MLX5_RXP_CSR_STATUS, &val)) {
-		DRV_LOG(ERR, "Failed to read from RXP!");
-		return -ENODEV;
-	}
-	if (!(val & MLX5_RXP_CSR_STATUS_INIT_DONE)) {
-		DRV_LOG(ERR, "RXP not initialised...");
-		return -EBUSY;
-	}
-	ret = mlx5_devx_regex_register_read(priv->ctx, id,
-					    MLX5_RXP_RTRU_CSR_CTRL, &val);
-	if (ret) {
-		DRV_LOG(ERR, "CSR read failed!");
-		return -1;
-	}
-	val |= MLX5_RXP_RTRU_CSR_CTRL_GO;
-	ret = mlx5_devx_regex_register_write(priv->ctx, id,
-					     MLX5_RXP_RTRU_CSR_CTRL, val);
-	if (ret) {
-		DRV_LOG(ERR, "Can't program rof file!");
-		return -1;
-	}
-	ret = rxp_program_rof(priv, buf, len, id);
-	if (ret) {
-		DRV_LOG(ERR, "Can't program rof file!");
-		return -1;
-	}
-	if (priv->is_bf2) {
-		ret = rxp_poll_csr_for_value
-			(priv->ctx, &val, MLX5_RXP_RTRU_CSR_STATUS,
-			 MLX5_RXP_RTRU_CSR_STATUS_UPDATE_DONE,
-			 MLX5_RXP_RTRU_CSR_STATUS_UPDATE_DONE,
-			 MLX5_RXP_POLL_CSR_FOR_VALUE_TIMEOUT, id);
-		if (ret < 0) {
-			DRV_LOG(ERR, "Rules update timeout: 0x%08X", val);
-			return ret;
-		}
-		DRV_LOG(DEBUG, "Rules update took %d cycles", ret);
-	}
-	if (mlx5_devx_regex_register_read(priv->ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
-					  &val)) {
-		DRV_LOG(ERR, "CSR read failed!");
-		return -1;
-	}
-	val &= ~(MLX5_RXP_RTRU_CSR_CTRL_GO);
-	if (mlx5_devx_regex_register_write(priv->ctx, id,
-					   MLX5_RXP_RTRU_CSR_CTRL, val)) {
-		DRV_LOG(ERR, "CSR write failed!");
-		return -1;
-	}
-	ret = mlx5_devx_regex_register_read(priv->ctx, id, MLX5_RXP_CSR_CTRL,
-					    &val);
-	if (ret)
-		return ret;
-	val &= ~MLX5_RXP_CSR_CTRL_INIT;
-	ret = mlx5_devx_regex_register_write(priv->ctx, id, MLX5_RXP_CSR_CTRL,
-					     val);
-	if (ret)
-		return ret;
-	rxp_init_rtru(priv, id, MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_L1_L2);
-	if (priv->is_bf2) {
-		ret = rxp_poll_csr_for_value(priv->ctx, &val,
-					     MLX5_RXP_CSR_STATUS,
-					     MLX5_RXP_CSR_STATUS_INIT_DONE,
-					     MLX5_RXP_CSR_STATUS_INIT_DONE,
-					     MLX5_RXP_CSR_STATUS_TRIAL_TIMEOUT,
-					     id);
-		if (ret) {
-			DRV_LOG(ERR, "Device init failed!");
-			return ret;
-		}
-	}
-	ret = mlnx_resume_database(priv, id);
-	if (ret < 0) {
-		DRV_LOG(ERR, "Failed to resume engine!");
-		return ret;
-	}
-
-	return ret;
-
-}
-
-static int
-rxp_init_eng(struct mlx5_regex_priv *priv, uint8_t id)
-{
-	uint32_t ctrl;
-	uint32_t reg;
-	struct ibv_context *ctx = priv->ctx;
-	int ret;
-
-	ret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CTRL, &ctrl);
-	if (ret)
-		return ret;
-	if (ctrl & MLX5_RXP_CSR_CTRL_INIT) {
-		ctrl &= ~MLX5_RXP_CSR_CTRL_INIT;
-		ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL,
-						     ctrl);
-		if (ret)
-			return ret;
-	}
-	ctrl |= MLX5_RXP_CSR_CTRL_INIT;
-	ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL, ctrl);
-	if (ret)
-		return ret;
-	ctrl &= ~MLX5_RXP_CSR_CTRL_INIT;
-	ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL, ctrl);
-	if (ret)
-		return ret;
-	rte_delay_us(20000);
-	ret = rxp_poll_csr_for_value(ctx, &ctrl, MLX5_RXP_CSR_STATUS,
-				     MLX5_RXP_CSR_STATUS_INIT_DONE,
-				     MLX5_RXP_CSR_STATUS_INIT_DONE,
-				     MLX5_RXP_CSR_STATUS_TRIAL_TIMEOUT, id);
-	if (ret)
-		return ret;
-	ret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CTRL, &ctrl);
-	if (ret)
-		return ret;
-	ctrl &= ~MLX5_RXP_CSR_CTRL_INIT;
-	ret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL,
-					     ctrl);
-	if (ret)
-		return ret;
-	ret = rxp_init_rtru(priv, id,
-			    MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_IM_L1_L2);
-	if (ret)
-		return ret;
-	ret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CAPABILITY_5,
-					    &reg);
-	if (ret)
-		return ret;
-	DRV_LOG(DEBUG, "max matches: %d, DDOS threshold: %d", reg >> 16,
-		reg & 0xffff);
-	if ((reg >> 16) >= priv->nb_max_matches)
-		ret = mlx5_devx_regex_register_write(ctx, id,
-						     MLX5_RXP_CSR_MAX_MATCH,
-						     priv->nb_max_matches);
-	else
-		ret = mlx5_devx_regex_register_write(ctx, id,
-						     MLX5_RXP_CSR_MAX_MATCH,
-						     (reg >> 16));
-	ret |= mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_MAX_PREFIX,
-					 (reg & 0xFFFF));
-	ret |= mlx5_devx_regex_register_write(ctx, id,
-					      MLX5_RXP_CSR_MAX_LATENCY, 0);
-	ret |= mlx5_devx_regex_register_write(ctx, id,
-					      MLX5_RXP_CSR_MAX_PRI_THREAD, 0);
-	return ret;
-}
-
 static int
 rxp_db_setup(struct mlx5_regex_priv *priv)
 {
@@ -762,10 +89,6 @@ mlx5_regex_rules_db_import(struct rte_regexdev *dev,
 		     const char *rule_db, uint32_t rule_db_len)
 {
 	struct mlx5_regex_priv *priv = dev->data->dev_private;
-	struct mlx5_rxp_ctl_rules_pgm *rules = NULL;
-	uint32_t id;
-	int ret;
-	uint32_t ver;
 
 	if (priv->prog_mode == MLX5_RXP_MODE_NOT_DEFINED) {
 		DRV_LOG(ERR, "RXP programming mode not set!");
@@ -777,37 +100,8 @@ mlx5_regex_rules_db_import(struct rte_regexdev *dev,
 	}
 	if (rule_db_len == 0)
 		return -EINVAL;
-	if (mlx5_devx_regex_register_read(priv->ctx, 0,
-					  MLX5_RXP_CSR_BASE_ADDRESS, &ver)) {
-		DRV_LOG(ERR, "Failed to read Main CSRs Engine 0!");
-		return -1;
-	}
-	/* Need to ensure RXP not busy before stop! */
-	for (id = 0; id < priv->nb_engines; id++) {
-		ret = rxp_stop_engine(priv->ctx, id);
-		if (ret) {
-			DRV_LOG(ERR, "Can't stop engine.");
-			ret = -ENODEV;
-			goto tidyup_error;
-		}
-		ret = program_rxp_rules(priv, rule_db, rule_db_len, id);
-		if (ret < 0) {
-			DRV_LOG(ERR, "Failed to program rxp rules.");
-			ret = -ENODEV;
-			goto tidyup_error;
-		}
-		ret = rxp_start_engine(priv->ctx, id);
-		if (ret) {
-			DRV_LOG(ERR, "Can't start engine.");
-			ret = -ENODEV;
-			goto tidyup_error;
-		}
-	}
-	rte_free(rules);
+
 	return 0;
-tidyup_error:
-	rte_free(rules);
-	return ret;
 }
 
 int
-- 
2.25.1

Re: [dpdk-dev] [PATCH 04/10] regex/mlx5: remove regexp register read/write

[Ori Kam]

Hi Francis,

> -----Original Message-----
> From: Francis Kelly <fkelly@nvidia.com>
> Sent: Friday, October 22, 2021 6:46 PM
> Subject: [PATCH 04/10] regex/mlx5: remove regexp register read/write
> 
> From: Ady Agbarih <adypodoman@gmail.com>
> 
> Remove the set/query regexp register commands from devx.
> Remove functions that used these commands.
> Remove manual rules programming.
> 
> Signed-off-by: Ady Agbarih <adypodoman@gmail.com>
> ---

Acked-by: Ori Kam <orika@nvidia.com>
Best,
Ori

[dpdk-dev] [PATCH 05/10] regex/mlx5: move RXP to CrSpace

[Francis Kelly]

From: Ady Agbarih <adypodoman@gmail.com>

Add patch for programming the regex database through rof file,
using the firmware instead of manually through the software.
No need to setup the DB anymore, the regex-daemon is responsible
for that always.
In the new flow the regex driver only has to program rof rules
by using set params devx cmd, requires rof mkey creation.
The rules file has to be read into 4KB aligned memory.

Signed-off-by: Ady Agbarih <adypodoman@gmail.com>
---
 drivers/regex/mlx5/mlx5_regex.h |  12 ----
 drivers/regex/mlx5/mlx5_rxp.c   | 111 ++++++++++++++++++++------------
 drivers/regex/mlx5/mlx5_rxp.h   |   4 +-
 3 files changed, 72 insertions(+), 55 deletions(-)

diff --git a/drivers/regex/mlx5/mlx5_regex.h b/drivers/regex/mlx5/mlx5_regex.h
index 09b360a1ab..9741421e7a 100644
--- a/drivers/regex/mlx5/mlx5_regex.h
+++ b/drivers/regex/mlx5/mlx5_regex.h
@@ -46,16 +46,6 @@ struct mlx5_regex_qp {
 	struct mlx5_mr_ctrl mr_ctrl;
 };
 
-struct mlx5_regex_db {
-	void *ptr; /* Pointer to the db memory. */
-	uint32_t len; /* The memory len. */
-	bool active; /* Active flag. */
-	uint8_t db_assigned_to_eng_num;
-	/**< To which engine the db is connected. */
-	struct mlx5_regex_umem umem;
-	/**< The umem struct. */
-};
-
 struct mlx5_regex_priv {
 	TAILQ_ENTRY(mlx5_regex_priv) next;
 	struct ibv_context *ctx; /* Device context. */
@@ -64,8 +54,6 @@ struct mlx5_regex_priv {
 	struct mlx5_regex_qp *qps; /* Pointer to the qp array. */
 	uint16_t nb_max_matches; /* Max number of matches. */
 	enum mlx5_rxp_program_mode prog_mode;
-	struct mlx5_regex_db db[MLX5_RXP_MAX_ENGINES +
-				MLX5_RXP_EM_COUNT];
 	uint32_t nb_engines; /* Number of RegEx engines. */
 	struct mlx5dv_devx_uar *uar; /* UAR object. */
 	struct ibv_pd *pd;
diff --git a/drivers/regex/mlx5/mlx5_rxp.c b/drivers/regex/mlx5/mlx5_rxp.c
index 8f54ab018e..59c68544ad 100644
--- a/drivers/regex/mlx5/mlx5_rxp.c
+++ b/drivers/regex/mlx5/mlx5_rxp.c
@@ -28,6 +28,12 @@
 #define MLX5_REGEX_RXP_ROF2_LINE_LEN 34
 
 /* Private Declarations */
+static int
+rxp_create_mkey(struct mlx5_regex_priv *priv, void *ptr, size_t size,
+	uint32_t access, struct mlx5_regex_mkey *mkey);
+static inline void
+rxp_destroy_mkey(struct mlx5_regex_mkey *mkey);
+
 int
 mlx5_regex_info_get(struct rte_regexdev *dev __rte_unused,
 		    struct rte_regexdev_info *info)
@@ -44,44 +50,46 @@ mlx5_regex_info_get(struct rte_regexdev *dev __rte_unused,
 }
 
 static int
-rxp_db_setup(struct mlx5_regex_priv *priv)
+rxp_create_mkey(struct mlx5_regex_priv *priv, void *ptr, size_t size,
+	uint32_t access, struct mlx5_regex_mkey *mkey)
 {
-	int ret;
-	uint8_t i;
+	struct mlx5_devx_mkey_attr mkey_attr;
 
-	/* Setup database memories for both RXP engines + reprogram memory. */
-	for (i = 0; i < (priv->nb_engines + MLX5_RXP_EM_COUNT); i++) {
-		priv->db[i].ptr = rte_malloc("", MLX5_MAX_DB_SIZE, 1 << 21);
-		if (!priv->db[i].ptr) {
-			DRV_LOG(ERR, "Failed to alloc db memory!");
-			ret = ENODEV;
-			goto tidyup_error;
-		}
-		/* Register the memory. */
-		priv->db[i].umem.umem = mlx5_glue->devx_umem_reg(priv->ctx,
-							priv->db[i].ptr,
-							MLX5_MAX_DB_SIZE, 7);
-		if (!priv->db[i].umem.umem) {
-			DRV_LOG(ERR, "Failed to register memory!");
-			ret = ENODEV;
-			goto tidyup_error;
-		}
-		/* Ensure set all DB memory to 0's before setting up DB. */
-		memset(priv->db[i].ptr, 0x00, MLX5_MAX_DB_SIZE);
-		/* No data currently in database. */
-		priv->db[i].len = 0;
-		priv->db[i].active = false;
-		priv->db[i].db_assigned_to_eng_num = MLX5_RXP_DB_NOT_ASSIGNED;
+	/* Register the memory. */
+	mkey->umem = mlx5_glue->devx_umem_reg(priv->ctx, ptr, size, access);
+	if (!mkey->umem) {
+		DRV_LOG(ERR, "Failed to register memory!");
+		return -ENODEV;
 	}
-	return 0;
-tidyup_error:
-	for (i = 0; i < (priv->nb_engines + MLX5_RXP_EM_COUNT); i++) {
-		if (priv->db[i].umem.umem)
-			mlx5_glue->devx_umem_dereg(priv->db[i].umem.umem);
-		rte_free(priv->db[i].ptr);
-		priv->db[i].ptr = NULL;
+	/* Create mkey */
+	mkey_attr = (struct mlx5_devx_mkey_attr) {
+		.addr = (uintptr_t)ptr,
+		.size = (uint32_t)size,
+		.umem_id = mlx5_os_get_umem_id(mkey->umem),
+		.pg_access = 1,
+		.umr_en = 0,
+	};
+#ifdef HAVE_IBV_FLOW_DV_SUPPORT
+	if (regex_get_pdn(priv->pd, &mkey_attr.pd) < 0) {
+		DRV_LOG(ERR, "Failed to get pdn!");
+		return -ENODEV;
+	}
+#endif
+	mkey->mkey = mlx5_devx_cmd_mkey_create(priv->ctx, &mkey_attr);
+	if (!mkey->mkey) {
+		DRV_LOG(ERR, "Failed to create direct mkey!");
+		return -ENODEV;
 	}
-	return -ret;
+	return 0;
+}
+
+static inline void
+rxp_destroy_mkey(struct mlx5_regex_mkey *mkey)
+{
+	if (mkey->mkey)
+		claim_zero(mlx5_devx_cmd_destroy(mkey->mkey));
+	if (mkey->umem)
+		claim_zero(mlx5_glue->devx_umem_dereg(mkey->umem));
 }
 
 int
@@ -89,6 +97,10 @@ mlx5_regex_rules_db_import(struct rte_regexdev *dev,
 		     const char *rule_db, uint32_t rule_db_len)
 {
 	struct mlx5_regex_priv *priv = dev->data->dev_private;
+	struct mlx5_regex_mkey mkey;
+	uint32_t id;
+	int ret;
+	void *ptr;
 
 	if (priv->prog_mode == MLX5_RXP_MODE_NOT_DEFINED) {
 		DRV_LOG(ERR, "RXP programming mode not set!");
@@ -100,8 +112,31 @@ mlx5_regex_rules_db_import(struct rte_regexdev *dev,
 	}
 	if (rule_db_len == 0)
 		return -EINVAL;
+	/* copy rules - rules have to be 4KB aligned. */
+	ptr = rte_malloc("", rule_db_len, 1 << 12);
+	if (!ptr) {
+		DRV_LOG(ERR, "Failed to allocate rules file memory.");
+		return -ENOMEM;
+	}
+	rte_memcpy(ptr, rule_db, rule_db_len);
+	/* Register umem and create rof mkey. */
+	ret = rxp_create_mkey(priv, ptr, rule_db_len, /*access=*/7, &mkey);
+	if (ret < 0)
+		return ret;
 
-	return 0;
+	for (id = 0; id < priv->nb_engines; id++) {
+		ret = mlx5_devx_regex_rules_program(priv->ctx, id,
+			mkey.mkey->id, rule_db_len, (uintptr_t)ptr);
+		if (ret < 0) {
+			DRV_LOG(ERR, "Failed to program rxp rules.");
+			ret = -ENODEV;
+			break;
+		}
+		ret = 0;
+	}
+	rxp_destroy_mkey(&mkey);
+	rte_free(ptr);
+	return ret;
 }
 
 int
@@ -123,12 +158,6 @@ mlx5_regex_configure(struct rte_regexdev *dev,
 		return -rte_errno;
 	}
 	priv->nb_max_matches = cfg->nb_max_matches;
-	/* Setup rxp db memories. */
-	if (rxp_db_setup(priv)) {
-		DRV_LOG(ERR, "Failed to setup RXP db memory");
-		rte_errno = ENOMEM;
-		return -rte_errno;
-	}
 	if (cfg->rule_db != NULL) {
 		ret = mlx5_regex_rules_db_import(dev, cfg->rule_db,
 						 cfg->rule_db_len);
diff --git a/drivers/regex/mlx5/mlx5_rxp.h b/drivers/regex/mlx5/mlx5_rxp.h
index 9686e24cdb..254e9cfa2b 100644
--- a/drivers/regex/mlx5/mlx5_rxp.h
+++ b/drivers/regex/mlx5/mlx5_rxp.h
@@ -129,9 +129,9 @@ enum mlx5_rxp_program_mode {
 #define MLX5_RXP_EM_COUNT 1u /* Extra External Memories to use. */
 #define MLX5_RXP_DB_NOT_ASSIGNED 0xFF
 
-struct mlx5_regex_umem {
+struct mlx5_regex_mkey {
 	struct mlx5dv_devx_umem *umem;
-	uint32_t id;
+	struct mlx5_devx_obj *mkey;
 	uint64_t offset;
 };
 
-- 
2.25.1

Re: [dpdk-dev] [PATCH 05/10] regex/mlx5: move RXP to CrSpace

[Ori Kam]

Hi Francis,

> -----Original Message-----
> From: Francis Kelly <fkelly@nvidia.com>
> Sent: Friday, October 22, 2021 6:46 PM
> Subject: [PATCH 05/10] regex/mlx5: move RXP to CrSpace
> 
> From: Ady Agbarih <adypodoman@gmail.com>
> 
> Add patch for programming the regex database through rof file,
> using the firmware instead of manually through the software.
> No need to setup the DB anymore, the regex-daemon is responsible
> for that always.
> In the new flow the regex driver only has to program rof rules
> by using set params devx cmd, requires rof mkey creation.
> The rules file has to be read into 4KB aligned memory.
> 
> Signed-off-by: Ady Agbarih <adypodoman@gmail.com>
> ---

Acked-by: Ori Kam <orika@nvidia.com>
Best,
Ori

[dpdk-dev] [PATCH 06/10] regex/mlx5: remove start/stop engine API

[Francis Kelly]

From: Ady Agbarih <adypodoman@gmail.com>

Remove the engine start/stop DevX commands,
as they have been deprecated and moved to FW.

Signed-off-by: Ady Agbarih <adypodoman@gmail.com>
---
 drivers/regex/mlx5/mlx5_regex.c      |  5 ----
 drivers/regex/mlx5/mlx5_regex.h      |  2 --
 drivers/regex/mlx5/mlx5_regex_devx.c | 42 ----------------------------
 3 files changed, 49 deletions(-)

diff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c
index f9eb3a2fab..d58851d41d 100644
--- a/drivers/regex/mlx5/mlx5_regex.c
+++ b/drivers/regex/mlx5/mlx5_regex.c
@@ -49,16 +49,11 @@ int
 mlx5_regex_stop(struct rte_regexdev *dev __rte_unused)
 {
 	struct mlx5_regex_priv *priv = dev->data->dev_private;
-	uint32_t i;
 
 	mlx5_regex_clean_ctrl(dev);
 	rte_free(priv->qps);
 	priv->qps = NULL;
 
-	for (i = 0; i < priv->nb_engines; i++)
-		/* Stop engine. */
-		mlx5_devx_regex_database_stop(priv->ctx, i);
-
 	return 0;
 }
 
diff --git a/drivers/regex/mlx5/mlx5_regex.h b/drivers/regex/mlx5/mlx5_regex.h
index 9741421e7a..5c2bda36c9 100644
--- a/drivers/regex/mlx5/mlx5_regex.h
+++ b/drivers/regex/mlx5/mlx5_regex.h
@@ -101,8 +101,6 @@ int mlx5_regex_rules_db_import(struct rte_regexdev *dev,
 			       const char *rule_db, uint32_t rule_db_len);
 
 /* mlx5_regex_devx.c */
-int mlx5_devx_regex_database_stop(void *ctx, uint8_t engine);
-int mlx5_devx_regex_database_resume(void *ctx, uint8_t engine);
 int mlx5_devx_regex_rules_program(void *ctx, uint8_t engine, uint32_t rof_mkey,
 				uint32_t rof_size, uint64_t db_mkey_offset);
 
diff --git a/drivers/regex/mlx5/mlx5_regex_devx.c b/drivers/regex/mlx5/mlx5_regex_devx.c
index 262f301121..a8aa64c325 100644
--- a/drivers/regex/mlx5/mlx5_regex_devx.c
+++ b/drivers/regex/mlx5/mlx5_regex_devx.c
@@ -12,48 +12,6 @@
 #include "mlx5_regex.h"
 #include "mlx5_regex_utils.h"
 
-int
-mlx5_devx_regex_database_stop(void *ctx, uint8_t engine)
-{
-	uint32_t out[MLX5_ST_SZ_DW(set_regexp_params_out)] = {0};
-	uint32_t in[MLX5_ST_SZ_DW(set_regexp_params_in)] = {0};
-	int ret;
-
-	MLX5_SET(set_regexp_params_in, in, opcode, MLX5_CMD_SET_REGEX_PARAMS);
-	MLX5_SET(set_regexp_params_in, in, engine_id, engine);
-	MLX5_SET(set_regexp_params_in, in, regexp_params.stop_engine, 1);
-	MLX5_SET(set_regexp_params_in, in, field_select.stop_engine, 1);
-	ret = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
-					  sizeof(out));
-	if (ret) {
-		DRV_LOG(ERR, "Database stop failed %d", ret);
-		rte_errno = errno;
-		return -errno;
-	}
-	return 0;
-}
-
-int
-mlx5_devx_regex_database_resume(void *ctx, uint8_t engine)
-{
-	uint32_t out[MLX5_ST_SZ_DW(set_regexp_params_out)] = {0};
-	uint32_t in[MLX5_ST_SZ_DW(set_regexp_params_in)] = {0};
-	int ret;
-
-	MLX5_SET(set_regexp_params_in, in, opcode, MLX5_CMD_SET_REGEX_PARAMS);
-	MLX5_SET(set_regexp_params_in, in, engine_id, engine);
-	MLX5_SET(set_regexp_params_in, in, regexp_params.stop_engine, 0);
-	MLX5_SET(set_regexp_params_in, in, field_select.stop_engine, 1);
-	ret = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
-					  sizeof(out));
-	if (ret) {
-		DRV_LOG(ERR, "Database start failed %d", ret);
-		rte_errno = errno;
-		return -errno;
-	}
-	return 0;
-}
-
 int
 mlx5_devx_regex_rules_program(void *ctx, uint8_t engine, uint32_t rof_mkey,
 				uint32_t rof_size, uint64_t rof_mkey_va)
-- 
2.25.1

[dpdk-dev] [PATCH 07/10] regex/mlx5: removed redundant rxp csr file

[Francis Kelly]

The mlx5_rxp_csrs.h file has been deprecated as
its contents has now been moved to FW.

Signed-off-by: Francis Kelly <fkelly@nvidia.com>
---
 drivers/regex/mlx5/mlx5_regex.c         |   1 -
 drivers/regex/mlx5/mlx5_regex_control.c |   1 -
 drivers/regex/mlx5/mlx5_rxp.c           |   1 -
 drivers/regex/mlx5/mlx5_rxp.h           |   1 +
 drivers/regex/mlx5/mlx5_rxp_csrs.h      | 342 ------------------------
 5 files changed, 1 insertion(+), 345 deletions(-)
 delete mode 100644 drivers/regex/mlx5/mlx5_rxp_csrs.h

diff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c
index d58851d41d..49ef6fb212 100644
--- a/drivers/regex/mlx5/mlx5_regex.c
+++ b/drivers/regex/mlx5/mlx5_regex.c
@@ -19,7 +19,6 @@
 
 #include "mlx5_regex.h"
 #include "mlx5_regex_utils.h"
-#include "mlx5_rxp_csrs.h"
 
 #define MLX5_REGEX_DRIVER_NAME regex_mlx5
 
diff --git a/drivers/regex/mlx5/mlx5_regex_control.c b/drivers/regex/mlx5/mlx5_regex_control.c
index 1783df923c..3e0a0cdd71 100644
--- a/drivers/regex/mlx5/mlx5_regex_control.c
+++ b/drivers/regex/mlx5/mlx5_regex_control.c
@@ -22,7 +22,6 @@
 
 #include "mlx5_regex.h"
 #include "mlx5_regex_utils.h"
-#include "mlx5_rxp_csrs.h"
 #include "mlx5_rxp.h"
 
 #define MLX5_REGEX_NUM_WQE_PER_PAGE (4096/64)
diff --git a/drivers/regex/mlx5/mlx5_rxp.c b/drivers/regex/mlx5/mlx5_rxp.c
index 59c68544ad..dbd632fc74 100644
--- a/drivers/regex/mlx5/mlx5_rxp.c
+++ b/drivers/regex/mlx5/mlx5_rxp.c
@@ -17,7 +17,6 @@
 
 #include "mlx5_regex.h"
 #include "mlx5_regex_utils.h"
-#include "mlx5_rxp_csrs.h"
 #include "mlx5_rxp.h"
 
 #define MLX5_REGEX_MAX_MATCHES MLX5_RXP_MAX_MATCHES
diff --git a/drivers/regex/mlx5/mlx5_rxp.h b/drivers/regex/mlx5/mlx5_rxp.h
index 254e9cfa2b..315e3b4ca3 100644
--- a/drivers/regex/mlx5/mlx5_rxp.h
+++ b/drivers/regex/mlx5/mlx5_rxp.h
@@ -5,6 +5,7 @@
 #ifndef RTE_PMD_MLX5_REGEX_RXP_H_
 #define RTE_PMD_MLX5_REGEX_RXP_H_
 
+#define MLX5_RXP_BF2_IDENTIFIER 0x0
 #define MLX5_RXP_MAX_JOB_LENGTH	16384
 #define MLX5_RXP_MAX_SUBSETS 4095
 #define MLX5_RXP_CSR_NUM_ENTRIES 31
diff --git a/drivers/regex/mlx5/mlx5_rxp_csrs.h b/drivers/regex/mlx5/mlx5_rxp_csrs.h
deleted file mode 100644
index 08cb6f3261..0000000000
--- a/drivers/regex/mlx5/mlx5_rxp_csrs.h
+++ /dev/null
@@ -1,342 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright 2020 Mellanox Technologies, Ltd
- */
-
-#ifndef _MLX5_RXP_CSRS_H_
-#define _MLX5_RXP_CSRS_H_
-
-/* BF types */
-#define MLX5_RXP_BF2_IDENTIFIER 0x0
-
-/*
- * Common to all RXP implementations
- */
-#define MLX5_RXP_CSR_BASE_ADDRESS 0x0000ul
-#define MLX5_RXP_RTRU_CSR_BASE_ADDRESS 0x0100ul
-#define MLX5_RXP_STATS_CSR_BASE_ADDRESS	0x0200ul
-#define MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS 0x0600ul
-
-#define MLX5_RXP_CSR_WIDTH 4
-
-/* This is the identifier we expect to see in the first RXP CSR */
-#define MLX5_RXP_IDENTIFIER 0x5254
-
-/* Hyperion specific BAR0 offsets */
-#define MLX5_RXP_FPGA_BASE_ADDRESS 0x0000ul
-#define MLX5_RXP_PCIE_BASE_ADDRESS 0x1000ul
-#define MLX5_RXP_IDMA_BASE_ADDRESS 0x2000ul
-#define MLX5_RXP_EDMA_BASE_ADDRESS 0x3000ul
-#define MLX5_RXP_SYSMON_BASE_ADDRESS 0xf300ul
-#define MLX5_RXP_ISP_CSR_BASE_ADDRESS 0xf400ul
-
-/* Offset to the RXP common 4K CSR space */
-#define MLX5_RXP_PCIE_CSR_BASE_ADDRESS 0xf000ul
-
-/* FPGA CSRs */
-
-#define MLX5_RXP_FPGA_VERSION (MLX5_RXP_FPGA_BASE_ADDRESS + \
-			       MLX5_RXP_CSR_WIDTH * 0)
-
-/* PCIe CSRs */
-#define MLX5_RXP_PCIE_INIT_ISR (MLX5_RXP_PCIE_BASE_ADDRESS + \
-				MLX5_RXP_CSR_WIDTH * 0)
-#define MLX5_RXP_PCIE_INIT_IMR (MLX5_RXP_PCIE_BASE_ADDRESS + \
-				MLX5_RXP_CSR_WIDTH * 1)
-#define MLX5_RXP_PCIE_INIT_CFG_STAT (MLX5_RXP_PCIE_BASE_ADDRESS + \
-				     MLX5_RXP_CSR_WIDTH * 2)
-#define MLX5_RXP_PCIE_INIT_FLR (MLX5_RXP_PCIE_BASE_ADDRESS + \
-				MLX5_RXP_CSR_WIDTH * 3)
-#define MLX5_RXP_PCIE_INIT_CTRL	(MLX5_RXP_PCIE_BASE_ADDRESS + \
-				 MLX5_RXP_CSR_WIDTH * 4)
-
-/* IDMA CSRs */
-#define MLX5_RXP_IDMA_ISR (MLX5_RXP_IDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 0)
-#define MLX5_RXP_IDMA_IMR (MLX5_RXP_IDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 1)
-#define MLX5_RXP_IDMA_CSR (MLX5_RXP_IDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 4)
-#define MLX5_RXP_IDMA_CSR_RST_MSK 0x0001
-#define MLX5_RXP_IDMA_CSR_PDONE_MSK 0x0002
-#define MLX5_RXP_IDMA_CSR_INIT_MSK 0x0004
-#define MLX5_RXP_IDMA_CSR_EN_MSK 0x0008
-#define MLX5_RXP_IDMA_QCR (MLX5_RXP_IDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 5)
-#define MLX5_RXP_IDMA_QCR_QAVAIL_MSK 0x00FF
-#define MLX5_RXP_IDMA_QCR_QEN_MSK 0xFF00
-#define MLX5_RXP_IDMA_DCR (MLX5_RXP_IDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 6)
-#define MLX5_RXP_IDMA_DWCTR (MLX5_RXP_IDMA_BASE_ADDRESS + \
-			     MLX5_RXP_CSR_WIDTH * 7)
-#define MLX5_RXP_IDMA_DWTOR (MLX5_RXP_IDMA_BASE_ADDRESS + \
-			     MLX5_RXP_CSR_WIDTH * 8)
-#define MLX5_RXP_IDMA_PADCR (MLX5_RXP_IDMA_BASE_ADDRESS + \
-			     MLX5_RXP_CSR_WIDTH * 9)
-#define MLX5_RXP_IDMA_DFCR (MLX5_RXP_IDMA_BASE_ADDRESS + \
-			    MLX5_RXP_CSR_WIDTH * 10)
-#define MLX5_RXP_IDMA_FOFLR0 (MLX5_RXP_IDMA_BASE_ADDRESS + \
-			      MLX5_RXP_CSR_WIDTH * 16)
-#define MLX5_RXP_IDMA_FOFLR1 (MLX5_RXP_IDMA_BASE_ADDRESS + \
-			      MLX5_RXP_CSR_WIDTH * 17)
-#define MLX5_RXP_IDMA_FOFLR2 (MLX5_RXP_IDMA_BASE_ADDRESS + \
-			      MLX5_RXP_CSR_WIDTH * 18)
-#define MLX5_RXP_IDMA_FUFLR0 (MLX5_RXP_IDMA_BASE_ADDRESS + \
-			      MLX5_RXP_CSR_WIDTH * 24)
-#define MLX5_RXP_IDMA_FUFLR1 (MLX5_RXP_IDMA_BASE_ADDRESS + \
-			      MLX5_RXP_CSR_WIDTH * 25)
-#define MLX5_RXP_IDMA_FUFLR2 (MLX5_RXP_IDMA_BASE_ADDRESS + \
-			      MLX5_RXP_CSR_WIDTH * 26)
-
-#define MLX5_RXP_IDMA_QCSR_BASE	(MLX5_RXP_IDMA_BASE_ADDRESS + \
-				 MLX5_RXP_CSR_WIDTH * 128)
-#define MLX5_RXP_IDMA_QCSR_RST_MSK 0x0001
-#define MLX5_RXP_IDMA_QCSR_PDONE_MSK 0x0002
-#define MLX5_RXP_IDMA_QCSR_INIT_MSK 0x0004
-#define MLX5_RXP_IDMA_QCSR_EN_MSK 0x0008
-#define MLX5_RXP_IDMA_QDPTR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \
-				  MLX5_RXP_CSR_WIDTH * 192)
-#define MLX5_RXP_IDMA_QTPTR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \
-				  MLX5_RXP_CSR_WIDTH * 256)
-#define MLX5_RXP_IDMA_QDRPTR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \
-				   MLX5_RXP_CSR_WIDTH * 320)
-#define MLX5_RXP_IDMA_QDRALR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \
-				   MLX5_RXP_CSR_WIDTH * 384)
-#define MLX5_RXP_IDMA_QDRAHR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \
-				   MLX5_RXP_CSR_WIDTH * 385)
-
-/* EDMA CSRs */
-#define MLX5_RXP_EDMA_ISR (MLX5_RXP_EDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 0)
-#define MLX5_RXP_EDMA_IMR (MLX5_RXP_EDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 1)
-#define MLX5_RXP_EDMA_CSR (MLX5_RXP_EDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 4)
-#define MLX5_RXP_EDMA_CSR_RST_MSK 0x0001
-#define MLX5_RXP_EDMA_CSR_PDONE_MSK 0x0002
-#define MLX5_RXP_EDMA_CSR_INIT_MSK 0x0004
-#define MLX5_RXP_EDMA_CSR_EN_MSK 0x0008
-#define MLX5_RXP_EDMA_QCR (MLX5_RXP_EDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 5)
-#define MLX5_RXP_EDMA_QCR_QAVAIL_MSK 0x00FF
-#define MLX5_RXP_EDMA_QCR_QEN_MSK 0xFF00
-#define MLX5_RXP_EDMA_DCR (MLX5_RXP_EDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 6)
-#define MLX5_RXP_EDMA_DWCTR (MLX5_RXP_EDMA_BASE_ADDRESS + \
-			     MLX5_RXP_CSR_WIDTH * 7)
-#define MLX5_RXP_EDMA_DWTOR (MLX5_RXP_EDMA_BASE_ADDRESS + \
-			     MLX5_RXP_CSR_WIDTH * 8)
-#define MLX5_RXP_EDMA_DFCR (MLX5_RXP_EDMA_BASE_ADDRESS + \
-			    MLX5_RXP_CSR_WIDTH * 10)
-#define MLX5_RXP_EDMA_FOFLR0 (MLX5_RXP_EDMA_BASE_ADDRESS + \
-			      MLX5_RXP_CSR_WIDTH * 16)
-#define MLX5_RXP_EDMA_FOFLR1 (MLX5_RXP_EDMA_BASE_ADDRESS + \
-			      MLX5_RXP_CSR_WIDTH * 17)
-#define MLX5_RXP_EDMA_FOFLR2 (MLX5_RXP_EDMA_BASE_ADDRESS + \
-			      MLX5_RXP_CSR_WIDTH * 18)
-#define MLX5_RXP_EDMA_FUFLR0 (MLX5_RXP_EDMA_BASE_ADDRESS + \
-			      MLX5_RXP_CSR_WIDTH * 24)
-#define MLX5_RXP_EDMA_FUFLR1 (MLX5_RXP_EDMA_BASE_ADDRESS +\
-			      MLX5_RXP_CSR_WIDTH * 25)
-#define MLX5_RXP_EDMA_FUFLR2 (MLX5_RXP_EDMA_BASE_ADDRESS + \
-			      MLX5_RXP_CSR_WIDTH * 26)
-
-#define MLX5_RXP_EDMA_QCSR_BASE	(MLX5_RXP_EDMA_BASE_ADDRESS + \
-				 MLX5_RXP_CSR_WIDTH * 128)
-#define MLX5_RXP_EDMA_QCSR_RST_MSK 0x0001
-#define MLX5_RXP_EDMA_QCSR_PDONE_MSK 0x0002
-#define MLX5_RXP_EDMA_QCSR_INIT_MSK 0x0004
-#define MLX5_RXP_EDMA_QCSR_EN_MSK 0x0008
-#define MLX5_RXP_EDMA_QTPTR_BASE (MLX5_RXP_EDMA_BASE_ADDRESS + \
-				  MLX5_RXP_CSR_WIDTH * 256)
-#define MLX5_RXP_EDMA_QDRPTR_BASE (MLX5_RXP_EDMA_BASE_ADDRESS + \
-				   MLX5_RXP_CSR_WIDTH * 320)
-#define MLX5_RXP_EDMA_QDRALR_BASE (MLX5_RXP_EDMA_BASE_ADDRESS + \
-				   MLX5_RXP_CSR_WIDTH * 384)
-#define MLX5_RXP_EDMA_QDRAHR_BASE (MLX5_RXP_EDMA_BASE_ADDRESS + \
-				   MLX5_RXP_CSR_WIDTH * 385)
-
-/* Main CSRs */
-#define MLX5_RXP_CSR_IDENTIFIER	(MLX5_RXP_CSR_BASE_ADDRESS + \
-				 MLX5_RXP_CSR_WIDTH * 0)
-#define MLX5_RXP_CSR_REVISION (MLX5_RXP_CSR_BASE_ADDRESS + \
-			       MLX5_RXP_CSR_WIDTH * 1)
-#define MLX5_RXP_CSR_CAPABILITY_0 (MLX5_RXP_CSR_BASE_ADDRESS + \
-				   MLX5_RXP_CSR_WIDTH * 2)
-#define MLX5_RXP_CSR_CAPABILITY_1 (MLX5_RXP_CSR_BASE_ADDRESS + \
-				   MLX5_RXP_CSR_WIDTH * 3)
-#define MLX5_RXP_CSR_CAPABILITY_2 (MLX5_RXP_CSR_BASE_ADDRESS + \
-				   MLX5_RXP_CSR_WIDTH * 4)
-#define MLX5_RXP_CSR_CAPABILITY_3 (MLX5_RXP_CSR_BASE_ADDRESS + \
-				   MLX5_RXP_CSR_WIDTH * 5)
-#define MLX5_RXP_CSR_CAPABILITY_4 (MLX5_RXP_CSR_BASE_ADDRESS + \
-				   MLX5_RXP_CSR_WIDTH * 6)
-#define MLX5_RXP_CSR_CAPABILITY_5 (MLX5_RXP_CSR_BASE_ADDRESS + \
-				   MLX5_RXP_CSR_WIDTH * 7)
-#define MLX5_RXP_CSR_CAPABILITY_6 (MLX5_RXP_CSR_BASE_ADDRESS + \
-				   MLX5_RXP_CSR_WIDTH * 8)
-#define MLX5_RXP_CSR_CAPABILITY_7 (MLX5_RXP_CSR_BASE_ADDRESS + \
-				   MLX5_RXP_CSR_WIDTH * 9)
-#define MLX5_RXP_CSR_STATUS (MLX5_RXP_CSR_BASE_ADDRESS + \
-				   MLX5_RXP_CSR_WIDTH * 10)
-#define MLX5_RXP_CSR_STATUS_INIT_DONE 0x0001
-#define MLX5_RXP_CSR_STATUS_GOING 0x0008
-#define MLX5_RXP_CSR_STATUS_IDLE 0x0040
-#define MLX5_RXP_CSR_STATUS_TRACKER_OK 0x0080
-#define MLX5_RXP_CSR_STATUS_TRIAL_TIMEOUT 0x0100
-#define MLX5_RXP_CSR_FIFO_STATUS_0 (MLX5_RXP_CSR_BASE_ADDRESS + \
-				    MLX5_RXP_CSR_WIDTH * 11)
-#define MLX5_RXP_CSR_FIFO_STATUS_1 (MLX5_RXP_CSR_BASE_ADDRESS + \
-				    MLX5_RXP_CSR_WIDTH * 12)
-#define MLX5_RXP_CSR_JOB_DDOS_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \
-				     MLX5_RXP_CSR_WIDTH * 13)
-/* 14 + 15 reserved */
-#define MLX5_RXP_CSR_CORE_CLK_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \
-				     MLX5_RXP_CSR_WIDTH * 16)
-#define MLX5_RXP_CSR_WRITE_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \
-				  MLX5_RXP_CSR_WIDTH * 17)
-#define MLX5_RXP_CSR_JOB_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \
-				MLX5_RXP_CSR_WIDTH * 18)
-#define MLX5_RXP_CSR_JOB_ERROR_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \
-				      MLX5_RXP_CSR_WIDTH * 19)
-#define MLX5_RXP_CSR_JOB_BYTE_COUNT0 (MLX5_RXP_CSR_BASE_ADDRESS + \
-				      MLX5_RXP_CSR_WIDTH * 20)
-#define MLX5_RXP_CSR_JOB_BYTE_COUNT1 (MLX5_RXP_CSR_BASE_ADDRESS + \
-				      MLX5_RXP_CSR_WIDTH * 21)
-#define MLX5_RXP_CSR_RESPONSE_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \
-				     MLX5_RXP_CSR_WIDTH * 22)
-#define MLX5_RXP_CSR_MATCH_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \
-				  MLX5_RXP_CSR_WIDTH * 23)
-#define MLX5_RXP_CSR_CTRL (MLX5_RXP_CSR_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 24)
-#define MLX5_RXP_CSR_CTRL_INIT 0x0001
-#define MLX5_RXP_CSR_CTRL_GO 0x0008
-#define MLX5_RXP_CSR_MAX_MATCH (MLX5_RXP_CSR_BASE_ADDRESS + \
-				MLX5_RXP_CSR_WIDTH * 25)
-#define MLX5_RXP_CSR_MAX_PREFIX	(MLX5_RXP_CSR_BASE_ADDRESS + \
-				 MLX5_RXP_CSR_WIDTH * 26)
-#define MLX5_RXP_CSR_MAX_PRI_THREAD (MLX5_RXP_CSR_BASE_ADDRESS + \
-				     MLX5_RXP_CSR_WIDTH * 27)
-#define MLX5_RXP_CSR_MAX_LATENCY (MLX5_RXP_CSR_BASE_ADDRESS + \
-				  MLX5_RXP_CSR_WIDTH * 28)
-#define MLX5_RXP_CSR_SCRATCH_1 (MLX5_RXP_CSR_BASE_ADDRESS + \
-				MLX5_RXP_CSR_WIDTH * 29)
-#define MLX5_RXP_CSR_CLUSTER_MASK (MLX5_RXP_CSR_BASE_ADDRESS + \
-				   MLX5_RXP_CSR_WIDTH * 30)
-#define MLX5_RXP_CSR_INTRA_CLUSTER_MASK (MLX5_RXP_CSR_BASE_ADDRESS + \
-					 MLX5_RXP_CSR_WIDTH * 31)
-
-/* Runtime Rule Update CSRs */
-/* 0 + 1 reserved */
-#define MLX5_RXP_RTRU_CSR_CAPABILITY (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
-				      MLX5_RXP_CSR_WIDTH * 2)
-/* 3-9 reserved */
-#define MLX5_RXP_RTRU_CSR_STATUS (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
-				  MLX5_RXP_CSR_WIDTH * 10)
-#define MLX5_RXP_RTRU_CSR_STATUS_UPDATE_DONE 0x0002
-#define MLX5_RXP_RTRU_CSR_STATUS_IM_INIT_DONE 0x0010
-#define MLX5_RXP_RTRU_CSR_STATUS_L1C_INIT_DONE 0x0020
-#define MLX5_RXP_RTRU_CSR_STATUS_L2C_INIT_DONE 0x0040
-#define MLX5_RXP_RTRU_CSR_STATUS_EM_INIT_DONE 0x0080
-#define MLX5_RXP_RTRU_CSR_FIFO_STAT (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
-				     MLX5_RXP_CSR_WIDTH * 11)
-/* 12-15 reserved */
-#define MLX5_RXP_RTRU_CSR_CHECKSUM_0 (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
-				      MLX5_RXP_CSR_WIDTH * 16)
-#define MLX5_RXP_RTRU_CSR_CHECKSUM_1 (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
-				      MLX5_RXP_CSR_WIDTH * 17)
-#define MLX5_RXP_RTRU_CSR_CHECKSUM_2 (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
-				      MLX5_RXP_CSR_WIDTH * 18)
-/* 19 + 20 reserved */
-#define MLX5_RXP_RTRU_CSR_RTRU_COUNT (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
-				      MLX5_RXP_CSR_WIDTH * 21)
-#define MLX5_RXP_RTRU_CSR_ROF_REV (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
-				   MLX5_RXP_CSR_WIDTH * 22)
-/* 23 reserved */
-#define MLX5_RXP_RTRU_CSR_CTRL (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
-				MLX5_RXP_CSR_WIDTH * 24)
-#define MLX5_RXP_RTRU_CSR_CTRL_INIT 0x0001
-#define MLX5_RXP_RTRU_CSR_CTRL_GO 0x0002
-#define MLX5_RXP_RTRU_CSR_CTRL_SIP 0x0004
-#define MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_MASK (3 << 4)
-#define MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_IM_L1_L2_EM (0 << 4)
-#define MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_IM_L1_L2 (1 << 4)
-#define MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_L1_L2 (2 << 4)
-#define MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_EM (3 << 4)
-#define MLX5_RXP_RTRU_CSR_ADDR (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
-				MLX5_RXP_CSR_WIDTH * 25)
-#define MLX5_RXP_RTRU_CSR_DATA_0 (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
-				  MLX5_RXP_CSR_WIDTH * 26)
-#define MLX5_RXP_RTRU_CSR_DATA_1 (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \
-				  MLX5_RXP_CSR_WIDTH * 27)
-/* 28-31 reserved */
-
-/* Statistics CSRs */
-#define MLX5_RXP_STATS_CSR_CLUSTER (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \
-				    MLX5_RXP_CSR_WIDTH * 0)
-#define MLX5_RXP_STATS_CSR_L2_CACHE (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \
-				     MLX5_RXP_CSR_WIDTH * 24)
-#define MLX5_RXP_STATS_CSR_MPFE_FIFO (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \
-				      MLX5_RXP_CSR_WIDTH * 25)
-#define MLX5_RXP_STATS_CSR_PE (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \
-			       MLX5_RXP_CSR_WIDTH * 28)
-#define MLX5_RXP_STATS_CSR_CP (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \
-			       MLX5_RXP_CSR_WIDTH * 30)
-#define MLX5_RXP_STATS_CSR_DP (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \
-			       MLX5_RXP_CSR_WIDTH * 31)
-
-/* Sysmon Stats CSRs */
-#define MLX5_RXP_SYSMON_CSR_T_FPGA (MLX5_RXP_SYSMON_BASE_ADDRESS + \
-				    MLX5_RXP_CSR_WIDTH * 0)
-#define MLX5_RXP_SYSMON_CSR_V_VCCINT (MLX5_RXP_SYSMON_BASE_ADDRESS + \
-				      MLX5_RXP_CSR_WIDTH * 1)
-#define MLX5_RXP_SYSMON_CSR_V_VCCAUX (MLX5_RXP_SYSMON_BASE_ADDRESS + \
-				      MLX5_RXP_CSR_WIDTH * 2)
-#define MLX5_RXP_SYSMON_CSR_T_U1 (MLX5_RXP_SYSMON_BASE_ADDRESS + \
-				  MLX5_RXP_CSR_WIDTH * 20)
-#define MLX5_RXP_SYSMON_CSR_I_EDG12V (MLX5_RXP_SYSMON_BASE_ADDRESS + \
-				      MLX5_RXP_CSR_WIDTH * 21)
-#define MLX5_RXP_SYSMON_CSR_I_VCC3V3 (MLX5_RXP_SYSMON_BASE_ADDRESS + \
-				      MLX5_RXP_CSR_WIDTH * 22)
-#define MLX5_RXP_SYSMON_CSR_I_VCC2V5 (MLX5_RXP_SYSMON_BASE_ADDRESS + \
-				      MLX5_RXP_CSR_WIDTH * 23)
-#define MLX5_RXP_SYSMON_CSR_T_U2 (MLX5_RXP_SYSMON_BASE_ADDRESS + \
-				  MLX5_RXP_CSR_WIDTH * 28)
-#define MLX5_RXP_SYSMON_CSR_I_AUX12V (MLX5_RXP_SYSMON_BASE_ADDRESS + \
-				      MLX5_RXP_CSR_WIDTH * 29)
-#define MLX5_RXP_SYSMON_CSR_I_VCC1V8 (MLX5_RXP_SYSMON_BASE_ADDRESS + \
-				      MLX5_RXP_CSR_WIDTH * 30)
-#define MLX5_RXP_SYSMON_CSR_I_VDDR3 (MLX5_RXP_SYSMON_BASE_ADDRESS + \
-				     MLX5_RXP_CSR_WIDTH * 31)
-
-/* In Service Programming CSRs */
-
-/* RXP-F1 and RXP-ZYNQ specific CSRs */
-#define MLX5_RXP_MQ_CP_BASE (0x0500ul)
-#define MLX5_RXP_MQ_CP_CAPABILITY_BASE (MLX5_RXP_MQ_CP_BASE + \
-					2 * MLX5_RXP_CSR_WIDTH)
-#define MLX5_RXP_MQ_CP_CAPABILITY_0 (MLX5_RXP_MQ_CP_CAPABILITY_BASE + \
-				     0 * MLX5_RXP_CSR_WIDTH)
-#define MLX5_RXP_MQ_CP_CAPABILITY_1 (MLX5_RXP_MQ_CP_CAPABILITY_BASE + \
-				     1 * MLX5_RXP_CSR_WIDTH)
-#define MLX5_RXP_MQ_CP_CAPABILITY_2 (MLX5_RXP_MQ_CP_CAPABILITY_BASE + \
-				     2 * MLX5_RXP_CSR_WIDTH)
-#define MLX5_RXP_MQ_CP_CAPABILITY_3 (MLX5_RXP_MQ_CP_CAPABILITY_BASE + \
-				     3 * MLX5_RXP_CSR_WIDTH)
-#define MLX5_RXP_MQ_CP_FIFO_STATUS_BASE (MLX5_RXP_MQ_CP_BASE + \
-					 11 * MLX5_RXP_CSR_WIDTH)
-#define MLX5_RXP_MQ_CP_FIFO_STATUS_C0 (MLX5_RXP_MQ_CP_FIFO_STATUS_BASE + \
-				       0 * MLX5_RXP_CSR_WIDTH)
-#define MLX5_RXP_MQ_CP_FIFO_STATUS_C1 (MLX5_RXP_MQ_CP_FIFO_STATUS_BASE + \
-				       1 * MLX5_RXP_CSR_WIDTH)
-#define MLX5_RXP_MQ_CP_FIFO_STATUS_C2 (MLX5_RXP_MQ_CP_FIFO_STATUS_BASE + \
-				       2 * MLX5_RXP_CSR_WIDTH)
-#define MLX5_RXP_MQ_CP_FIFO_STATUS_C3 (MLX5_RXP_MQ_CP_FIFO_STATUS_BASE + \
-				       3 * MLX5_RXP_CSR_WIDTH)
-
-/* Royalty tracker / licensing related CSRs */
-#define MLX5_RXPL__CSR_IDENT (MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS + \
-			      0 * MLX5_RXP_CSR_WIDTH)
-#define MLX5_RXPL__IDENTIFIER 0x4c505852 /* MLX5_RXPL_ */
-#define MLX5_RXPL__CSR_CAPABILITY (MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS + \
-				   2 * MLX5_RXP_CSR_WIDTH)
-#define MLX5_RXPL__TYPE_MASK 0xFF
-#define MLX5_RXPL__TYPE_NONE 0
-#define MLX5_RXPL__TYPE_MAXIM 1
-#define MLX5_RXPL__TYPE_XILINX_DNA 2
-#define MLX5_RXPL__CSR_STATUS (MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS + \
-			       10 * MLX5_RXP_CSR_WIDTH)
-#define MLX5_RXPL__CSR_IDENT_0 (MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS + \
-				16 * MLX5_RXP_CSR_WIDTH)
-#define MLX5_RXPL__CSR_KEY_0 (MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS + \
-			      24 * MLX5_RXP_CSR_WIDTH)
-
-#endif /* _MLX5_RXP_CSRS_H_ */
-- 
2.25.1

Re: [dpdk-dev] [PATCH 07/10] regex/mlx5: removed redundant rxp csr file

[Ori Kam]

Hi Francis,

> -----Original Message-----
> From: Francis Kelly <fkelly@nvidia.com>
> Sent: Friday, October 22, 2021 6:46 PM
> Subject: [PATCH 07/10] regex/mlx5: removed redundant rxp csr file
> 
> The mlx5_rxp_csrs.h file has been deprecated as
> its contents has now been moved to FW.
> 
> Signed-off-by: Francis Kelly <fkelly@nvidia.com>
> ---
Acked-by: Ori Kam <orika@nvidia.com>
Best,
Ori

[dpdk-dev] [PATCH 08/10] regex/mlx5: fix uninitialized QP destroy

[Francis Kelly]

From: Ady Agbarih <adypodoman@gmail.com>

The number of QPs for a device are setup during the
 configuration phase, when the user calls
 rte_regexdev_configure(). The mlx5 regex driver then
 pre-allocates QPs, however those QPs are not
 setup/ready for sending jobs. The user has to configure
 each QP using rte_regexdev_queue_pair_setup(). When
 stopping the device the driver destroys all QPs that
 were preallocated assuming that they are all setup. This
 results in an attempt to destroy an uninitialized QP,
 leading to a NULL dereference error.

In order to solve this issue we first check that the
 QP jobs array has been initialized before attempting
 to destroy the QP.

Fixes: 35f8f6c8dbee ("regex/mlx5: add cleanup code")
Cc: orika@nvidia.com

Signed-off-by: Ady Agbarih <adypodoman@gmail.com>
---
 drivers/regex/mlx5/mlx5_regex_control.c  | 3 +++
 drivers/regex/mlx5/mlx5_regex_fastpath.c | 7 ++++---
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/regex/mlx5/mlx5_regex_control.c b/drivers/regex/mlx5/mlx5_regex_control.c
index 3e0a0cdd71..52f66ecce8 100644
--- a/drivers/regex/mlx5/mlx5_regex_control.c
+++ b/drivers/regex/mlx5/mlx5_regex_control.c
@@ -283,6 +283,9 @@ mlx5_regex_clean_ctrl(struct rte_regexdev *dev)
 		return;
 	for (qp_ind = 0; qp_ind < priv->nb_queues; qp_ind++) {
 		qp = &priv->qps[qp_ind];
+		/* Check if mlx5_regex_qp_setup() was called for this QP */
+		if (!qp->jobs)
+			continue;
 		mlx5_regexdev_teardown_fastpath(priv, qp_ind);
 		mlx5_mr_btree_free(&qp->mr_ctrl.cache_bh);
 		for (i = 0; i < qp->nb_obj; i++)
diff --git a/drivers/regex/mlx5/mlx5_regex_fastpath.c b/drivers/regex/mlx5/mlx5_regex_fastpath.c
index 0833b2817e..26b4cc5c82 100644
--- a/drivers/regex/mlx5/mlx5_regex_fastpath.c
+++ b/drivers/regex/mlx5/mlx5_regex_fastpath.c
@@ -739,6 +739,7 @@ mlx5_regexdev_setup_fastpath(struct mlx5_regex_priv *priv, uint32_t qp_id)
 	err = setup_buffers(priv, qp);
 	if (err) {
 		rte_free(qp->jobs);
+		qp->jobs = NULL;
 		return err;
 	}
 
@@ -791,14 +792,14 @@ mlx5_regexdev_teardown_fastpath(struct mlx5_regex_priv *priv, uint32_t qp_id)
 	struct mlx5_regex_qp *qp = &priv->qps[qp_id];
 	uint32_t i;
 
-	if (qp) {
+	if (qp->jobs) {
 		for (i = 0; i < qp->nb_desc; i++) {
 			if (qp->jobs[i].imkey)
 				claim_zero(mlx5_devx_cmd_destroy
 							(qp->jobs[i].imkey));
 		}
 		free_buffers(qp);
-		if (qp->jobs)
-			rte_free(qp->jobs);
+		rte_free(qp->jobs);
+		qp->jobs = NULL;
 	}
 }
-- 
2.25.1

Re: [dpdk-dev] [PATCH 08/10] regex/mlx5: fix uninitialized QP destroy

[Ori Kam]

Hi Francis,

> -----Original Message-----
> From: Francis Kelly <fkelly@nvidia.com>
> Sent: Friday, October 22, 2021 6:46 PM
> Subject: [PATCH 08/10] regex/mlx5: fix uninitialized QP destroy
> 
> From: Ady Agbarih <adypodoman@gmail.com>
> 
> The number of QPs for a device are setup during the
>  configuration phase, when the user calls
>  rte_regexdev_configure(). The mlx5 regex driver then
>  pre-allocates QPs, however those QPs are not
>  setup/ready for sending jobs. The user has to configure
>  each QP using rte_regexdev_queue_pair_setup(). When
>  stopping the device the driver destroys all QPs that
>  were preallocated assuming that they are all setup. This
>  results in an attempt to destroy an uninitialized QP,
>  leading to a NULL dereference error.
> 
> In order to solve this issue we first check that the
>  QP jobs array has been initialized before attempting
>  to destroy the QP.
> 
> Fixes: 35f8f6c8dbee ("regex/mlx5: add cleanup code")
> Cc: orika@nvidia.com
> 
> Signed-off-by: Ady Agbarih <adypodoman@gmail.com>
> ---

Acked-by: Ori Kam <orika@nvidia.com>
Best,
Ori

[dpdk-dev] [PATCH 09/10] regex/mlx5: prevent QP double setup

[Francis Kelly]

From: Ady Agbarih <adypodoman@gmail.com>

When mlx5_regex_qp_setup() is called make sure
 the provided QP is not already setup.

Signed-off-by: Ady Agbarih <adypodoman@gmail.com>
---
 drivers/regex/mlx5/mlx5_regex_control.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/regex/mlx5/mlx5_regex_control.c b/drivers/regex/mlx5/mlx5_regex_control.c
index 52f66ecce8..17573c2e74 100644
--- a/drivers/regex/mlx5/mlx5_regex_control.c
+++ b/drivers/regex/mlx5/mlx5_regex_control.c
@@ -207,6 +207,12 @@ mlx5_regex_qp_setup(struct rte_regexdev *dev, uint16_t qp_ind,
 	uint16_t log_desc;
 
 	qp = &priv->qps[qp_ind];
+	if (qp->jobs) {
+		DRV_LOG(ERR, "Attempting to setup QP a second time.");
+		rte_errno = EINVAL;
+		return -rte_errno;
+	}
+
 	qp->flags = cfg->qp_conf_flags;
 	log_desc = rte_log2_u32(cfg->nb_desc);
 	/*
-- 
2.25.1

Re: [dpdk-dev] [PATCH 09/10] regex/mlx5: prevent QP double setup

[Ori Kam]

> -----Original Message-----
> From: Francis Kelly <fkelly@nvidia.com>
> Sent: Friday, October 22, 2021 6:46 PM
> Subject: [PATCH 09/10] regex/mlx5: prevent QP double setup
> 
> From: Ady Agbarih <adypodoman@gmail.com>
> 
> When mlx5_regex_qp_setup() is called make sure
>  the provided QP is not already setup.
> 
> Signed-off-by: Ady Agbarih <adypodoman@gmail.com>
> ---
>  drivers/regex/mlx5/mlx5_regex_control.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/regex/mlx5/mlx5_regex_control.c b/drivers/regex/mlx5/mlx5_regex_control.c
> index 52f66ecce8..17573c2e74 100644
> --- a/drivers/regex/mlx5/mlx5_regex_control.c
> +++ b/drivers/regex/mlx5/mlx5_regex_control.c
> @@ -207,6 +207,12 @@ mlx5_regex_qp_setup(struct rte_regexdev *dev, uint16_t qp_ind,
>  	uint16_t log_desc;
> 
>  	qp = &priv->qps[qp_ind];
> +	if (qp->jobs) {
> +		DRV_LOG(ERR, "Attempting to setup QP a second time.");
> +		rte_errno = EINVAL;
> +		return -rte_errno;
> +	}
> +
>  	qp->flags = cfg->qp_conf_flags;
>  	log_desc = rte_log2_u32(cfg->nb_desc);
>  	/*
> --
> 2.25.1

Acked-by: Ori Kam <orika@nvidia.com>
Best,
Ori

[dpdk-dev] [PATCH 10/10] doc: updated release notes and mlx5 file

[Francis Kelly]

Provided further description within documentation regarding
the RXP to CRSpace changes.

Signed-off-by: Francis Kelly <fkelly@nvidia.com>
---
 doc/guides/regexdevs/mlx5.rst          | 2 +-
 doc/guides/rel_notes/release_21_11.rst | 3 +++
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/doc/guides/regexdevs/mlx5.rst b/doc/guides/regexdevs/mlx5.rst
index 7c3a7c84bb..b2bf0afd01 100644
--- a/doc/guides/regexdevs/mlx5.rst
+++ b/doc/guides/regexdevs/mlx5.rst
@@ -55,7 +55,7 @@ Prerequisites
 Limitations
 -----------
 
-- The firmware version must be equal to or lower than XX.30.1004
+- The firmware version must be greater than XX.31.0364
 
 Run-time configuration
 ~~~~~~~~~~~~~~~~~~~~~~
diff --git a/doc/guides/rel_notes/release_21_11.rst b/doc/guides/rel_notes/release_21_11.rst
index 74776ca069..042348fae6 100644
--- a/doc/guides/rel_notes/release_21_11.rst
+++ b/doc/guides/rel_notes/release_21_11.rst
@@ -240,6 +240,9 @@ New Features
   * Added tests to verify tunnel header verification in IPsec inbound.
   * Added tests to verify inner checksum.
 
+* **Updated Mellanox mlx5 driver.**
+
+  * Added support for new ROF file format.
 
 Removed Items
 -------------
-- 
2.25.1

Re: [dpdk-dev] [PATCH 10/10] doc: updated release notes and mlx5 file

[Ori Kam]

> -----Original Message-----
> From: Francis Kelly <fkelly@nvidia.com>
> Sent: Friday, October 22, 2021 6:46 PM
> Subject: [PATCH 10/10] doc: updated release notes and mlx5 file
> 
> Provided further description within documentation regarding
> the RXP to CRSpace changes.
> 
> Signed-off-by: Francis Kelly <fkelly@nvidia.com>
> ---
>  doc/guides/regexdevs/mlx5.rst          | 2 +-
>  doc/guides/rel_notes/release_21_11.rst | 3 +++
>  2 files changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/doc/guides/regexdevs/mlx5.rst b/doc/guides/regexdevs/mlx5.rst
> index 7c3a7c84bb..b2bf0afd01 100644
> --- a/doc/guides/regexdevs/mlx5.rst
> +++ b/doc/guides/regexdevs/mlx5.rst
> @@ -55,7 +55,7 @@ Prerequisites
>  Limitations
>  -----------
> 
> -- The firmware version must be equal to or lower than XX.30.1004
> +- The firmware version must be greater than XX.31.0364
> 
>  Run-time configuration
>  ~~~~~~~~~~~~~~~~~~~~~~
> diff --git a/doc/guides/rel_notes/release_21_11.rst b/doc/guides/rel_notes/release_21_11.rst
> index 74776ca069..042348fae6 100644
> --- a/doc/guides/rel_notes/release_21_11.rst
> +++ b/doc/guides/rel_notes/release_21_11.rst
> @@ -240,6 +240,9 @@ New Features
>    * Added tests to verify tunnel header verification in IPsec inbound.
>    * Added tests to verify inner checksum.
> 
> +* **Updated Mellanox mlx5 driver.**
> +
> +  * Added support for new ROF file format.
> 
>  Removed Items
>  -------------
> --
> 2.25.1

Acked-by: Ori Kam <orika@nvidia.com>
Best,
Ori

Re: [dpdk-dev] [PATCH 10/10] doc: updated release notes and mlx5 file

[Thomas Monjalon]

A cover letter is missing for this series.

> > Provided further description within documentation regarding
> > the RXP to CRSpace changes.

This patch should be squashed with the relevant code change.

> > --- a/doc/guides/rel_notes/release_21_11.rst
> > +++ b/doc/guides/rel_notes/release_21_11.rst
> > +* **Updated Mellanox mlx5 driver.**

regex should be mentioned

> > +
> > +  * Added support for new ROF file format.
> 
> Acked-by: Ori Kam <orika@nvidia.com>

I had to rebase the series after the MR changes.

The patch 8 is fixing the patch 2.
We should not do that in a series, so I squashed them,
updating explanations and authors.

With above fixes, applied, thanks.

Re: [dpdk-dev] [PATCH 01/10] common/mlx5: update PRM definitions for regex availability

[Ori Kam]

Hi Francis,

> -----Original Message-----
> From: Francis Kelly <fkelly@nvidia.com>
> Sent: Friday, October 22, 2021 6:46 PM
> To: Thomas Monjalon <tmonjalon@nvidia.com>; Matan Azrad <matan@nvidia.com>; Slava Ovsiienko
> <viacheslavo@nvidia.com>; Ori Kam <orika@nvidia.com>
> Cc: JAMES HUNTER <jamhunter@nvidia.com>; Ady Agbarih <aagbarih@nvidia.com>; dev@dpdk.org;
> Ady Agbarih <adypodoman@gmail.com>
> Subject: [PATCH 01/10] common/mlx5: update PRM definitions for regex availability
> 
> From: Ady Agbarih <adypodoman@gmail.com>
> 
> Update PRM hca capabilities definitions as follows:
> regexp_version field added - specifies whether BF2 or BF3
> regexp field removed
> regexp_params field moved
> regexp_log_crspace_size field removed
> regexp_mmo added - specifies if using regex mmo wqe is supported
> 
> Allow regex only if both regexp_params and regexp_mmo are set,
> instead of checking regexp_mmo only.
> 
> Check version through the new capability field regexp_version instead
> of reading crspace register.
> 
> Signed-off-by: Ady Agbarih <adypodoman@gmail.com>
> ---

Acked-by: Ori Kam <orika@nvidia.com>
Best,
Ori