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From: Fabian Vogt <fabian@ritter-vogt.de>
To: Linus Walleij <linus.walleij@linaro.org>
Cc: Daniel Tang <dt.tangr@gmail.com>,
	dri-devel@lists.freedesktop.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 1/3] RFT: drm/pl111: Support grayscale
Date: Tue, 23 Jul 2019 17:19:03 +0200	[thread overview]
Message-ID: <1709073.y2qmsckc0Q@linux-e202.suse.de> (raw)
In-Reply-To: <20190723133755.22677-2-linus.walleij@linaro.org>

Hi,

I gave the series a try (virtual CX and TP so far, will do on a real CX later):
OOPS with a nullptr deref during probe.
This diff which just moves some lines around fixes that and the LCD appears to
work properly.

Once I verified the 24bit depth and clock speed config on HW as well, I can
give you my Tested-by, or would you prefer that I resubmit your series with the
fix below?

Thanks,
Fabian

---
diff --git a/drivers/gpu/drm/pl111/pl111_display.c b/drivers/gpu/drm/pl111/pl111_display.c
index 587b4d148c18..bd84d7a5a0f4 100644
--- a/drivers/gpu/drm/pl111/pl111_display.c
+++ b/drivers/gpu/drm/pl111/pl111_display.c
@@ -133,10 +133,6 @@ static void pl111_display_enable(struct drm_simple_display_pipe *pipe,
 	u32 cpl, tim2;
 	int ret;
 
-	if (connector->display_info.num_bus_formats == 1 &&
-	    connector->display_info.bus_formats[0] == MEDIA_BUS_FMT_Y8_1X8)
-		grayscale = true;
-
 	ret = clk_set_rate(priv->clk, mode->clock * 1000);
 	if (ret) {
 		dev_err(drm->dev,
@@ -191,6 +187,10 @@ static void pl111_display_enable(struct drm_simple_display_pipe *pipe,
 		    DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
 			tim2 |= TIM2_IPC;
 
+		if (connector->display_info.num_bus_formats == 1 &&
+		    connector->display_info.bus_formats[0] == MEDIA_BUS_FMT_Y8_1X8)
+			grayscale = true;
+
 		/*
 		 * The AC pin bias frequency is set to max count when using
 		 * grayscale so at least once in a while we will reverse





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WARNING: multiple messages have this Message-ID (diff)
From: Fabian Vogt <fabian@ritter-vogt.de>
To: Linus Walleij <linus.walleij@linaro.org>
Cc: Daniel Tang <dt.tangr@gmail.com>,
	dri-devel@lists.freedesktop.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 1/3] RFT: drm/pl111: Support grayscale
Date: Tue, 23 Jul 2019 17:19:03 +0200	[thread overview]
Message-ID: <1709073.y2qmsckc0Q@linux-e202.suse.de> (raw)
In-Reply-To: <20190723133755.22677-2-linus.walleij@linaro.org>

Hi,

I gave the series a try (virtual CX and TP so far, will do on a real CX later):
OOPS with a nullptr deref during probe.
This diff which just moves some lines around fixes that and the LCD appears to
work properly.

Once I verified the 24bit depth and clock speed config on HW as well, I can
give you my Tested-by, or would you prefer that I resubmit your series with the
fix below?

Thanks,
Fabian

---
diff --git a/drivers/gpu/drm/pl111/pl111_display.c b/drivers/gpu/drm/pl111/pl111_display.c
index 587b4d148c18..bd84d7a5a0f4 100644
--- a/drivers/gpu/drm/pl111/pl111_display.c
+++ b/drivers/gpu/drm/pl111/pl111_display.c
@@ -133,10 +133,6 @@ static void pl111_display_enable(struct drm_simple_display_pipe *pipe,
 	u32 cpl, tim2;
 	int ret;
 
-	if (connector->display_info.num_bus_formats == 1 &&
-	    connector->display_info.bus_formats[0] == MEDIA_BUS_FMT_Y8_1X8)
-		grayscale = true;
-
 	ret = clk_set_rate(priv->clk, mode->clock * 1000);
 	if (ret) {
 		dev_err(drm->dev,
@@ -191,6 +187,10 @@ static void pl111_display_enable(struct drm_simple_display_pipe *pipe,
 		    DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
 			tim2 |= TIM2_IPC;
 
+		if (connector->display_info.num_bus_formats == 1 &&
+		    connector->display_info.bus_formats[0] == MEDIA_BUS_FMT_Y8_1X8)
+			grayscale = true;
+
 		/*
 		 * The AC pin bias frequency is set to max count when using
 		 * grayscale so at least once in a while we will reverse

  reply	other threads:[~2019-07-23 15:19 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-23 13:37 [PATCH 0/3] RFT: PL111 DRM conversion of nspire Linus Walleij
2019-07-23 13:37 ` Linus Walleij
2019-07-23 13:37 ` [PATCH 1/3] RFT: drm/pl111: Support grayscale Linus Walleij
2019-07-23 13:37   ` Linus Walleij
2019-07-23 15:19   ` Fabian Vogt [this message]
2019-07-23 15:19     ` Fabian Vogt
2019-07-24 12:33     ` Linus Walleij
2019-07-24 12:33       ` Linus Walleij
2019-07-25 19:26       ` Fabian Vogt
2019-07-25 19:26         ` Fabian Vogt
2019-08-03  9:51         ` Linus Walleij
2019-08-03  9:51           ` Linus Walleij
2019-08-04 20:13           ` Fabian Vogt
2019-08-04 20:13             ` Fabian Vogt
2019-07-23 16:22   ` [1/3] " David Lechner
2019-07-23 16:22     ` David Lechner
2019-07-23 17:25   ` [PATCH 1/3] " Adam Jackson
2019-07-23 17:25     ` Adam Jackson
2019-07-23 21:06     ` Daniel Vetter
2019-07-23 21:06       ` Daniel Vetter
2019-07-24 12:52       ` Linus Walleij
2019-07-24 12:52         ` Linus Walleij
2019-07-24 14:06         ` Daniel Vetter
2019-07-24 14:06           ` Daniel Vetter
2019-07-23 13:37 ` [PATCH 2/3] RTF: drm/panel: simple: Add TI nspire panels Linus Walleij
2019-07-23 13:37   ` Linus Walleij
2019-07-23 17:54   ` Sam Ravnborg
2019-07-23 17:54     ` Sam Ravnborg
2019-07-24 13:58     ` Linus Walleij
2019-07-24 13:58       ` Linus Walleij
2019-07-24 18:53       ` Sam Ravnborg
2019-07-24 18:53         ` Sam Ravnborg
2019-07-23 13:37 ` [PATCH 3/3] RFT: ARM: nspire: Move CLCD set-up to device tree Linus Walleij
2019-07-23 13:37   ` Linus Walleij
2019-07-23 18:10 ` [PATCH 0/3] RFT: PL111 DRM conversion of nspire Sam Ravnborg
2019-07-23 18:10   ` Sam Ravnborg
2019-07-24 12:28   ` Linus Walleij
2019-07-24 12:28     ` Linus Walleij
2019-07-24 12:47     ` Pawel Moll
2019-07-24 12:47       ` Pawel Moll
2019-07-24 12:53       ` Linus Walleij
2019-07-24 12:53         ` Linus Walleij

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