From: patchwork-bot+linux-riscv@kernel.org
To: Charlie Jenkins <charlie@rivosinc.com>
Cc: linux-riscv@lists.infradead.org, paul.walmsley@sifive.com,
palmer@dabbelt.com, aou@eecs.berkeley.edu, guoren@kernel.org,
conor@kernel.org, conor.dooley@microchip.com,
cleger@rivosinc.com, evan@rivosinc.com, palmer@rivosinc.com,
linux-kernel@vger.kernel.org, alexghiti@rivosinc.com,
ajones@ventanamicro.com
Subject: Re: [PATCH v4 0/2] riscv: Extension parsing fixes
Date: Wed, 22 May 2024 23:51:47 +0000 [thread overview]
Message-ID: <171642190760.9409.9505694012625639228.git-patchwork-notify@kernel.org> (raw)
In-Reply-To: <20240502-cpufeature_fixes-v4-0-b3d1a088722d@rivosinc.com>
Hello:
This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@rivosinc.com>:
On Thu, 02 May 2024 21:50:49 -0700 you wrote:
> This series contains two minor fixes for the extension parsing in
> cpufeature.c.
>
> Some T-Head boards without vector 1.0 support report "v" in the isa
> string in their DT which will cause the kernel to run vector code. The
> code to blacklist "v" from these boards was doing so by using
> riscv_cached_mvendorid() which has not been populated at the time of
> extension parsing. This fix instead greedily reads the mvendorid CSR of
> the boot hart to determine if the cpu is from T-Head.
>
> [...]
Here is the summary with links:
- [v4,1/2] riscv: cpufeature: Fix thead vector hwcap removal
https://git.kernel.org/riscv/c/e482eab4d1eb
- [v4,2/2] riscv: cpufeature: Fix extension subset checking
https://git.kernel.org/riscv/c/e67e98ee8952
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
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WARNING: multiple messages have this Message-ID (diff)
From: patchwork-bot+linux-riscv@kernel.org
To: Charlie Jenkins <charlie@rivosinc.com>
Cc: linux-riscv@lists.infradead.org, paul.walmsley@sifive.com,
palmer@dabbelt.com, aou@eecs.berkeley.edu, guoren@kernel.org,
conor@kernel.org, conor.dooley@microchip.com,
cleger@rivosinc.com, evan@rivosinc.com, palmer@rivosinc.com,
linux-kernel@vger.kernel.org, alexghiti@rivosinc.com,
ajones@ventanamicro.com
Subject: Re: [PATCH v4 0/2] riscv: Extension parsing fixes
Date: Wed, 22 May 2024 23:51:47 +0000 [thread overview]
Message-ID: <171642190760.9409.9505694012625639228.git-patchwork-notify@kernel.org> (raw)
In-Reply-To: <20240502-cpufeature_fixes-v4-0-b3d1a088722d@rivosinc.com>
Hello:
This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@rivosinc.com>:
On Thu, 02 May 2024 21:50:49 -0700 you wrote:
> This series contains two minor fixes for the extension parsing in
> cpufeature.c.
>
> Some T-Head boards without vector 1.0 support report "v" in the isa
> string in their DT which will cause the kernel to run vector code. The
> code to blacklist "v" from these boards was doing so by using
> riscv_cached_mvendorid() which has not been populated at the time of
> extension parsing. This fix instead greedily reads the mvendorid CSR of
> the boot hart to determine if the cpu is from T-Head.
>
> [...]
Here is the summary with links:
- [v4,1/2] riscv: cpufeature: Fix thead vector hwcap removal
https://git.kernel.org/riscv/c/e482eab4d1eb
- [v4,2/2] riscv: cpufeature: Fix extension subset checking
https://git.kernel.org/riscv/c/e67e98ee8952
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
next prev parent reply other threads:[~2024-05-22 23:52 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-03 4:50 [PATCH v4 0/2] riscv: Extension parsing fixes Charlie Jenkins
2024-05-03 4:50 ` Charlie Jenkins
2024-05-03 4:50 ` [PATCH v4 1/2] riscv: cpufeature: Fix thead vector hwcap removal Charlie Jenkins
2024-05-03 4:50 ` Charlie Jenkins
2024-05-03 4:50 ` [PATCH v4 2/2] riscv: cpufeature: Fix extension subset checking Charlie Jenkins
2024-05-03 4:50 ` Charlie Jenkins
2024-05-22 23:51 ` patchwork-bot+linux-riscv [this message]
2024-05-22 23:51 ` [PATCH v4 0/2] riscv: Extension parsing fixes patchwork-bot+linux-riscv
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