* [PATCH V2] riscv: Implement smp_cond_load8/16() with Zawrs
@ 2024-12-17 1:39 ` guoren
0 siblings, 0 replies; 6+ messages in thread
From: guoren @ 2024-12-17 1:39 UTC (permalink / raw)
To: paul.walmsley, palmer, guoren, bjorn, conor, leobras, alexghiti,
christoph.muellner
Cc: linux-riscv, linux-kernel, parri.andrea, ajones, ericchancf,
Guo Ren
From: Guo Ren <guoren@linux.alibaba.com>
RISC-V code uses the queued spinlock implementation, which calls
the macros smp_cond_load_acquire for one byte. So, complement the
implementation of byte and halfword versions.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
Cc: Andrew Jones <ajones@ventanamicro.com>
---
Changes in V2:
- Fixup mask typo (0xf -> 0xff, 0xff -> 0xffff) by Andrew.
---
arch/riscv/include/asm/cmpxchg.h | 38 +++++++++++++++++++++++++++++---
1 file changed, 35 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h
index 4cadc56220fe..aa4410beb065 100644
--- a/arch/riscv/include/asm/cmpxchg.h
+++ b/arch/riscv/include/asm/cmpxchg.h
@@ -365,16 +365,48 @@ static __always_inline void __cmpwait(volatile void *ptr,
{
unsigned long tmp;
+ u32 *__ptr32b;
+ ulong __s, __val, __mask;
+
asm goto(ALTERNATIVE("j %l[no_zawrs]", "nop",
0, RISCV_ISA_EXT_ZAWRS, 1)
: : : : no_zawrs);
switch (size) {
case 1:
- fallthrough;
+ __ptr32b = (u32 *)((ulong)(ptr) & ~0x3);
+ __s = ((ulong)(ptr) & 0x3) * BITS_PER_BYTE;
+ __val = val << __s;
+ __mask = 0xff << __s;
+
+ asm volatile(
+ " lr.w %0, %1\n"
+ " and %0, %0, %3\n"
+ " xor %0, %0, %2\n"
+ " bnez %0, 1f\n"
+ ZAWRS_WRS_NTO "\n"
+ "1:"
+ : "=&r" (tmp), "+A" (*(__ptr32b))
+ : "r" (__val), "r" (__mask)
+ : "memory");
+ break;
case 2:
- /* RISC-V doesn't have lr instructions on byte and half-word. */
- goto no_zawrs;
+ __ptr32b = (u32 *)((ulong)(ptr) & ~0x3);
+ __s = ((ulong)(ptr) & 0x2) * BITS_PER_BYTE;
+ __val = val << __s;
+ __mask = 0xffff << __s;
+
+ asm volatile(
+ " lr.w %0, %1\n"
+ " and %0, %0, %3\n"
+ " xor %0, %0, %2\n"
+ " bnez %0, 1f\n"
+ ZAWRS_WRS_NTO "\n"
+ "1:"
+ : "=&r" (tmp), "+A" (*(__ptr32b))
+ : "r" (__val), "r" (__mask)
+ : "memory");
+ break;
case 4:
asm volatile(
" lr.w %0, %1\n"
--
2.40.1
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linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH V2] riscv: Implement smp_cond_load8/16() with Zawrs
@ 2024-12-17 1:39 ` guoren
0 siblings, 0 replies; 6+ messages in thread
From: guoren @ 2024-12-17 1:39 UTC (permalink / raw)
To: paul.walmsley, palmer, guoren, bjorn, conor, leobras, alexghiti,
christoph.muellner
Cc: linux-riscv, linux-kernel, parri.andrea, ajones, ericchancf,
Guo Ren
From: Guo Ren <guoren@linux.alibaba.com>
RISC-V code uses the queued spinlock implementation, which calls
the macros smp_cond_load_acquire for one byte. So, complement the
implementation of byte and halfword versions.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
Cc: Andrew Jones <ajones@ventanamicro.com>
---
Changes in V2:
- Fixup mask typo (0xf -> 0xff, 0xff -> 0xffff) by Andrew.
---
arch/riscv/include/asm/cmpxchg.h | 38 +++++++++++++++++++++++++++++---
1 file changed, 35 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h
index 4cadc56220fe..aa4410beb065 100644
--- a/arch/riscv/include/asm/cmpxchg.h
+++ b/arch/riscv/include/asm/cmpxchg.h
@@ -365,16 +365,48 @@ static __always_inline void __cmpwait(volatile void *ptr,
{
unsigned long tmp;
+ u32 *__ptr32b;
+ ulong __s, __val, __mask;
+
asm goto(ALTERNATIVE("j %l[no_zawrs]", "nop",
0, RISCV_ISA_EXT_ZAWRS, 1)
: : : : no_zawrs);
switch (size) {
case 1:
- fallthrough;
+ __ptr32b = (u32 *)((ulong)(ptr) & ~0x3);
+ __s = ((ulong)(ptr) & 0x3) * BITS_PER_BYTE;
+ __val = val << __s;
+ __mask = 0xff << __s;
+
+ asm volatile(
+ " lr.w %0, %1\n"
+ " and %0, %0, %3\n"
+ " xor %0, %0, %2\n"
+ " bnez %0, 1f\n"
+ ZAWRS_WRS_NTO "\n"
+ "1:"
+ : "=&r" (tmp), "+A" (*(__ptr32b))
+ : "r" (__val), "r" (__mask)
+ : "memory");
+ break;
case 2:
- /* RISC-V doesn't have lr instructions on byte and half-word. */
- goto no_zawrs;
+ __ptr32b = (u32 *)((ulong)(ptr) & ~0x3);
+ __s = ((ulong)(ptr) & 0x2) * BITS_PER_BYTE;
+ __val = val << __s;
+ __mask = 0xffff << __s;
+
+ asm volatile(
+ " lr.w %0, %1\n"
+ " and %0, %0, %3\n"
+ " xor %0, %0, %2\n"
+ " bnez %0, 1f\n"
+ ZAWRS_WRS_NTO "\n"
+ "1:"
+ : "=&r" (tmp), "+A" (*(__ptr32b))
+ : "r" (__val), "r" (__mask)
+ : "memory");
+ break;
case 4:
asm volatile(
" lr.w %0, %1\n"
--
2.40.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH V2] riscv: Implement smp_cond_load8/16() with Zawrs
2024-12-17 1:39 ` guoren
@ 2024-12-17 13:03 ` Andrew Jones
-1 siblings, 0 replies; 6+ messages in thread
From: Andrew Jones @ 2024-12-17 13:03 UTC (permalink / raw)
To: guoren
Cc: paul.walmsley, palmer, bjorn, conor, leobras, alexghiti,
christoph.muellner, linux-riscv, linux-kernel, parri.andrea,
ericchancf, Guo Ren
On Mon, Dec 16, 2024 at 08:39:10PM -0500, guoren@kernel.org wrote:
> From: Guo Ren <guoren@linux.alibaba.com>
>
> RISC-V code uses the queued spinlock implementation, which calls
> the macros smp_cond_load_acquire for one byte. So, complement the
> implementation of byte and halfword versions.
>
> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> Signed-off-by: Guo Ren <guoren@kernel.org>
> Cc: Andrew Jones <ajones@ventanamicro.com>
> ---
> Changes in V2:
> - Fixup mask typo (0xf -> 0xff, 0xff -> 0xffff) by Andrew.
> ---
> arch/riscv/include/asm/cmpxchg.h | 38 +++++++++++++++++++++++++++++---
> 1 file changed, 35 insertions(+), 3 deletions(-)
>
> diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h
> index 4cadc56220fe..aa4410beb065 100644
> --- a/arch/riscv/include/asm/cmpxchg.h
> +++ b/arch/riscv/include/asm/cmpxchg.h
> @@ -365,16 +365,48 @@ static __always_inline void __cmpwait(volatile void *ptr,
> {
> unsigned long tmp;
>
> + u32 *__ptr32b;
> + ulong __s, __val, __mask;
> +
> asm goto(ALTERNATIVE("j %l[no_zawrs]", "nop",
> 0, RISCV_ISA_EXT_ZAWRS, 1)
> : : : : no_zawrs);
>
> switch (size) {
> case 1:
> - fallthrough;
> + __ptr32b = (u32 *)((ulong)(ptr) & ~0x3);
> + __s = ((ulong)(ptr) & 0x3) * BITS_PER_BYTE;
> + __val = val << __s;
> + __mask = 0xff << __s;
> +
> + asm volatile(
> + " lr.w %0, %1\n"
> + " and %0, %0, %3\n"
> + " xor %0, %0, %2\n"
> + " bnez %0, 1f\n"
> + ZAWRS_WRS_NTO "\n"
> + "1:"
> + : "=&r" (tmp), "+A" (*(__ptr32b))
> + : "r" (__val), "r" (__mask)
> + : "memory");
> + break;
> case 2:
> - /* RISC-V doesn't have lr instructions on byte and half-word. */
> - goto no_zawrs;
> + __ptr32b = (u32 *)((ulong)(ptr) & ~0x3);
> + __s = ((ulong)(ptr) & 0x2) * BITS_PER_BYTE;
> + __val = val << __s;
> + __mask = 0xffff << __s;
> +
> + asm volatile(
> + " lr.w %0, %1\n"
> + " and %0, %0, %3\n"
> + " xor %0, %0, %2\n"
> + " bnez %0, 1f\n"
> + ZAWRS_WRS_NTO "\n"
> + "1:"
> + : "=&r" (tmp), "+A" (*(__ptr32b))
> + : "r" (__val), "r" (__mask)
> + : "memory");
> + break;
> case 4:
> asm volatile(
> " lr.w %0, %1\n"
> --
> 2.40.1
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH V2] riscv: Implement smp_cond_load8/16() with Zawrs
@ 2024-12-17 13:03 ` Andrew Jones
0 siblings, 0 replies; 6+ messages in thread
From: Andrew Jones @ 2024-12-17 13:03 UTC (permalink / raw)
To: guoren
Cc: paul.walmsley, palmer, bjorn, conor, leobras, alexghiti,
christoph.muellner, linux-riscv, linux-kernel, parri.andrea,
ericchancf, Guo Ren
On Mon, Dec 16, 2024 at 08:39:10PM -0500, guoren@kernel.org wrote:
> From: Guo Ren <guoren@linux.alibaba.com>
>
> RISC-V code uses the queued spinlock implementation, which calls
> the macros smp_cond_load_acquire for one byte. So, complement the
> implementation of byte and halfword versions.
>
> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> Signed-off-by: Guo Ren <guoren@kernel.org>
> Cc: Andrew Jones <ajones@ventanamicro.com>
> ---
> Changes in V2:
> - Fixup mask typo (0xf -> 0xff, 0xff -> 0xffff) by Andrew.
> ---
> arch/riscv/include/asm/cmpxchg.h | 38 +++++++++++++++++++++++++++++---
> 1 file changed, 35 insertions(+), 3 deletions(-)
>
> diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h
> index 4cadc56220fe..aa4410beb065 100644
> --- a/arch/riscv/include/asm/cmpxchg.h
> +++ b/arch/riscv/include/asm/cmpxchg.h
> @@ -365,16 +365,48 @@ static __always_inline void __cmpwait(volatile void *ptr,
> {
> unsigned long tmp;
>
> + u32 *__ptr32b;
> + ulong __s, __val, __mask;
> +
> asm goto(ALTERNATIVE("j %l[no_zawrs]", "nop",
> 0, RISCV_ISA_EXT_ZAWRS, 1)
> : : : : no_zawrs);
>
> switch (size) {
> case 1:
> - fallthrough;
> + __ptr32b = (u32 *)((ulong)(ptr) & ~0x3);
> + __s = ((ulong)(ptr) & 0x3) * BITS_PER_BYTE;
> + __val = val << __s;
> + __mask = 0xff << __s;
> +
> + asm volatile(
> + " lr.w %0, %1\n"
> + " and %0, %0, %3\n"
> + " xor %0, %0, %2\n"
> + " bnez %0, 1f\n"
> + ZAWRS_WRS_NTO "\n"
> + "1:"
> + : "=&r" (tmp), "+A" (*(__ptr32b))
> + : "r" (__val), "r" (__mask)
> + : "memory");
> + break;
> case 2:
> - /* RISC-V doesn't have lr instructions on byte and half-word. */
> - goto no_zawrs;
> + __ptr32b = (u32 *)((ulong)(ptr) & ~0x3);
> + __s = ((ulong)(ptr) & 0x2) * BITS_PER_BYTE;
> + __val = val << __s;
> + __mask = 0xffff << __s;
> +
> + asm volatile(
> + " lr.w %0, %1\n"
> + " and %0, %0, %3\n"
> + " xor %0, %0, %2\n"
> + " bnez %0, 1f\n"
> + ZAWRS_WRS_NTO "\n"
> + "1:"
> + : "=&r" (tmp), "+A" (*(__ptr32b))
> + : "r" (__val), "r" (__mask)
> + : "memory");
> + break;
> case 4:
> asm volatile(
> " lr.w %0, %1\n"
> --
> 2.40.1
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH V2] riscv: Implement smp_cond_load8/16() with Zawrs
2024-12-17 1:39 ` guoren
@ 2025-03-27 3:25 ` patchwork-bot+linux-riscv
-1 siblings, 0 replies; 6+ messages in thread
From: patchwork-bot+linux-riscv @ 2025-03-27 3:25 UTC (permalink / raw)
To: Guo Ren
Cc: linux-riscv, paul.walmsley, palmer, bjorn, conor, leobras,
alexghiti, christoph.muellner, linux-kernel, parri.andrea, ajones,
ericchancf, guoren
Hello:
This patch was applied to riscv/linux.git (for-next)
by Alexandre Ghiti <alexghiti@rivosinc.com>:
On Mon, 16 Dec 2024 20:39:10 -0500 you wrote:
> From: Guo Ren <guoren@linux.alibaba.com>
>
> RISC-V code uses the queued spinlock implementation, which calls
> the macros smp_cond_load_acquire for one byte. So, complement the
> implementation of byte and halfword versions.
>
> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> Signed-off-by: Guo Ren <guoren@kernel.org>
> Cc: Andrew Jones <ajones@ventanamicro.com>
>
> [...]
Here is the summary with links:
- [V2] riscv: Implement smp_cond_load8/16() with Zawrs
https://git.kernel.org/riscv/c/d9708b1931fc
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH V2] riscv: Implement smp_cond_load8/16() with Zawrs
@ 2025-03-27 3:25 ` patchwork-bot+linux-riscv
0 siblings, 0 replies; 6+ messages in thread
From: patchwork-bot+linux-riscv @ 2025-03-27 3:25 UTC (permalink / raw)
To: Guo Ren
Cc: linux-riscv, paul.walmsley, palmer, bjorn, conor, leobras,
alexghiti, christoph.muellner, linux-kernel, parri.andrea, ajones,
ericchancf, guoren
Hello:
This patch was applied to riscv/linux.git (for-next)
by Alexandre Ghiti <alexghiti@rivosinc.com>:
On Mon, 16 Dec 2024 20:39:10 -0500 you wrote:
> From: Guo Ren <guoren@linux.alibaba.com>
>
> RISC-V code uses the queued spinlock implementation, which calls
> the macros smp_cond_load_acquire for one byte. So, complement the
> implementation of byte and halfword versions.
>
> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> Signed-off-by: Guo Ren <guoren@kernel.org>
> Cc: Andrew Jones <ajones@ventanamicro.com>
>
> [...]
Here is the summary with links:
- [V2] riscv: Implement smp_cond_load8/16() with Zawrs
https://git.kernel.org/riscv/c/d9708b1931fc
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2025-03-27 4:39 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2024-12-17 1:39 [PATCH V2] riscv: Implement smp_cond_load8/16() with Zawrs guoren
2024-12-17 1:39 ` guoren
2024-12-17 13:03 ` Andrew Jones
2024-12-17 13:03 ` Andrew Jones
2025-03-27 3:25 ` patchwork-bot+linux-riscv
2025-03-27 3:25 ` patchwork-bot+linux-riscv
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