* [PATCH] arm64: dts: nuvoton: Add pinctrl
@ 2025-05-15 6:45 Andrew Jeffery
2025-05-21 22:31 ` patchwork-bot+linux-soc
0 siblings, 1 reply; 5+ messages in thread
From: Andrew Jeffery @ 2025-05-15 6:45 UTC (permalink / raw)
To: soc; +Cc: joel
From: "William A. Kennington III" <william@wkennington.com>
This is critical to support multifunction pins shared between devices as
well as generic GPIOs.
Signed-off-by: William A. Kennington III <william@wkennington.com>
Link: https://patch.msgid.link/20250416015902.2091251-1-william@wkennington.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
---
Hello SoC maintainers,
This is the single accepted change in the BMC tree for the Nuvoton ARM64
devicetrees (NPCM8XX) for v6.16. There were others on the lists but they
were sent as independent series and caused conflicts. We'll leave those
for next cycle when they're in better shape.
Cheers,
Andrew
---
.../boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 65 ++++++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
index ecd171b2feba488b486cdc72708420fca6fc11c8..fead4dde590dfff3f7d28a47c2b883462a6e51eb 100644
--- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
+++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
@@ -176,4 +176,69 @@ watchdog2: watchdog@a01c {
};
};
};
+
+ pinctrl: pinctrl@f0010000 {
+ compatible = "nuvoton,npcm845-pinctrl";
+ ranges = <0x0 0x0 0xf0010000 0x8000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ nuvoton,sysgcr = <&gcr>;
+ status = "okay";
+ gpio0: gpio@f0010000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x0 0xB0>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ };
+ gpio1: gpio@f0011000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x1000 0xB0>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 32 32>;
+ };
+ gpio2: gpio@f0012000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x2000 0xB0>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 64 32>;
+ };
+ gpio3: gpio@f0013000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x3000 0xB0>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 96 32>;
+ };
+ gpio4: gpio@f0014000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x4000 0xB0>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 128 32>;
+ };
+ gpio5: gpio@f0015000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x5000 0xB0>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 160 32>;
+ };
+ gpio6: gpio@f0016000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x6000 0xB0>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 192 32>;
+ };
+ gpio7: gpio@f0017000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x7000 0xB0>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 224 32>;
+ };
+ };
};
---
base-commit: 0af2f6be1b4281385b618cb86ad946eded089ac8
change-id: 20250515-nuvoton-arm64-dt-8488b3a2cbf2
Best regards,
--
Andrew Jeffery <andrew@codeconstruct.com.au>
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH] arm64: dts: nuvoton: Add pinctrl
@ 2025-04-16 1:59 ` William A. Kennington III
0 siblings, 0 replies; 5+ messages in thread
From: William A. Kennington III @ 2025-04-16 1:59 UTC (permalink / raw)
To: Avi Fishman, Tomer Maimon, Tali Perry, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: devicetree, openbmc, linux-kernel, William A. Kennington III
This is critical to support multifunction pins shared between devices as
well as generic GPIOs.
Signed-off-by: William A. Kennington III <william@wkennington.com>
---
.../dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 65 +++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
index b2595f5c146b..dd1351698e77 100644
--- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
+++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
@@ -207,4 +207,69 @@ watchdog2: watchdog@a01c {
};
};
};
+
+ pinctrl: pinctrl@f0010000 {
+ compatible = "nuvoton,npcm845-pinctrl";
+ ranges = <0x0 0x0 0xf0010000 0x8000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ nuvoton,sysgcr = <&gcr>;
+ status = "okay";
+ gpio0: gpio@f0010000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x0 0xB0>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ };
+ gpio1: gpio@f0011000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x1000 0xB0>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 32 32>;
+ };
+ gpio2: gpio@f0012000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x2000 0xB0>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 64 32>;
+ };
+ gpio3: gpio@f0013000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x3000 0xB0>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 96 32>;
+ };
+ gpio4: gpio@f0014000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x4000 0xB0>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 128 32>;
+ };
+ gpio5: gpio@f0015000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x5000 0xB0>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 160 32>;
+ };
+ gpio6: gpio@f0016000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x6000 0xB0>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 192 32>;
+ };
+ gpio7: gpio@f0017000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x7000 0xB0>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 224 32>;
+ };
+ };
};
--
2.49.0.604.gff1f9ca942-goog
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH] arm64: dts: nuvoton: Add pinctrl
@ 2025-04-16 1:59 ` William A. Kennington III
0 siblings, 0 replies; 5+ messages in thread
From: William A. Kennington III @ 2025-04-16 1:59 UTC (permalink / raw)
To: Avi Fishman, Tomer Maimon, Tali Perry, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: openbmc, devicetree, linux-kernel, William A. Kennington III
This is critical to support multifunction pins shared between devices as
well as generic GPIOs.
Signed-off-by: William A. Kennington III <william@wkennington.com>
---
.../dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 65 +++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
index b2595f5c146b..dd1351698e77 100644
--- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
+++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
@@ -207,4 +207,69 @@ watchdog2: watchdog@a01c {
};
};
};
+
+ pinctrl: pinctrl@f0010000 {
+ compatible = "nuvoton,npcm845-pinctrl";
+ ranges = <0x0 0x0 0xf0010000 0x8000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ nuvoton,sysgcr = <&gcr>;
+ status = "okay";
+ gpio0: gpio@f0010000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x0 0xB0>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ };
+ gpio1: gpio@f0011000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x1000 0xB0>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 32 32>;
+ };
+ gpio2: gpio@f0012000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x2000 0xB0>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 64 32>;
+ };
+ gpio3: gpio@f0013000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x3000 0xB0>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 96 32>;
+ };
+ gpio4: gpio@f0014000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x4000 0xB0>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 128 32>;
+ };
+ gpio5: gpio@f0015000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x5000 0xB0>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 160 32>;
+ };
+ gpio6: gpio@f0016000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x6000 0xB0>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 192 32>;
+ };
+ gpio7: gpio@f0017000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x7000 0xB0>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 224 32>;
+ };
+ };
};
--
2.49.0.604.gff1f9ca942-goog
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH] arm64: dts: nuvoton: Add pinctrl
2025-04-16 1:59 ` William A. Kennington III
(?)
@ 2025-05-07 2:39 ` Andrew Jeffery
-1 siblings, 0 replies; 5+ messages in thread
From: Andrew Jeffery @ 2025-05-07 2:39 UTC (permalink / raw)
To: Avi Fishman, Tomer Maimon, Tali Perry, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, William A. Kennington III
Cc: openbmc, devicetree, linux-kernel
On Tue, 15 Apr 2025 18:59:02 -0700, William A. Kennington III wrote:
> This is critical to support multifunction pins shared between devices as
> well as generic GPIOs.
>
>
Thanks, I've applied this to be picked up through the BMC tree.
--
Andrew Jeffery <andrew@codeconstruct.com.au>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2025-05-21 22:31 UTC | newest]
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2025-05-15 6:45 [PATCH] arm64: dts: nuvoton: Add pinctrl Andrew Jeffery
2025-05-21 22:31 ` patchwork-bot+linux-soc
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2025-04-16 1:59 William A. Kennington III
2025-04-16 1:59 ` William A. Kennington III
2025-05-07 2:39 ` Andrew Jeffery
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