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From: patchwork-bot+linux-riscv@kernel.org
To: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2VyIDxjbGVnZXJAcml2b3NpbmMuY29tPg==?=@aws-us-west-2-korg-oddjob-rhel9-1.codeaurora.org
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	linux-kselftest@vger.kernel.org, palmer@dabbelt.com,
	paul.walmsley@sifive.com, shuah@kernel.org, alex@ghiti.fr,
	schwab@suse.de
Subject: Re: [PATCH v5] selftests: riscv: add misaligned access testing
Date: Wed, 06 Aug 2025 17:15:52 +0000	[thread overview]
Message-ID: <175450055200.2863135.7169449906797738792.git-patchwork-notify@kernel.org> (raw)
In-Reply-To: <20250711131925.112485-1-cleger@rivosinc.com>

Hello:

This patch was applied to riscv/linux.git (for-next)
by Alexandre Ghiti <alexghiti@rivosinc.com>:

On Fri, 11 Jul 2025 13:19:24 +0000 you wrote:
> This selftest tests all the currently emulated instructions (except for
> the RV32 compressed ones which are left as a future exercise for a RV32
> user). For the FPU instructions, all the FPU registers are tested.
> 
> Signed-off-by: Clément Léger <cleger@rivosinc.com>
> 
> 
> [...]

Here is the summary with links:
  - [v5] selftests: riscv: add misaligned access testing
    https://git.kernel.org/riscv/c/bf6594367a92

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html



WARNING: multiple messages have this Message-ID (diff)
From: patchwork-bot+linux-riscv@kernel.org
To: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2VyIDxjbGVnZXJAcml2b3NpbmMuY29tPg==?=@aws-us-west-2-korg-oddjob-rhel9-1.codeaurora.org
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	linux-kselftest@vger.kernel.org, palmer@dabbelt.com,
	paul.walmsley@sifive.com, shuah@kernel.org, alex@ghiti.fr,
	schwab@suse.de
Subject: Re: [PATCH v5] selftests: riscv: add misaligned access testing
Date: Wed, 06 Aug 2025 17:15:52 +0000	[thread overview]
Message-ID: <175450055200.2863135.7169449906797738792.git-patchwork-notify@kernel.org> (raw)
In-Reply-To: <20250711131925.112485-1-cleger@rivosinc.com>

Hello:

This patch was applied to riscv/linux.git (for-next)
by Alexandre Ghiti <alexghiti@rivosinc.com>:

On Fri, 11 Jul 2025 13:19:24 +0000 you wrote:
> This selftest tests all the currently emulated instructions (except for
> the RV32 compressed ones which are left as a future exercise for a RV32
> user). For the FPU instructions, all the FPU registers are tested.
> 
> Signed-off-by: Clément Léger <cleger@rivosinc.com>
> 
> 
> [...]

Here is the summary with links:
  - [v5] selftests: riscv: add misaligned access testing
    https://git.kernel.org/riscv/c/bf6594367a92

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html



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linux-riscv@lists.infradead.org
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  parent reply	other threads:[~2025-08-06 17:15 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-11 13:19 [PATCH v5] selftests: riscv: add misaligned access testing Clément Léger
2025-07-11 13:19 ` Clément Léger
2025-07-17  8:06 ` Alexandre Ghiti
2025-07-17  8:06   ` Alexandre Ghiti
2025-08-06 17:15 ` patchwork-bot+linux-riscv [this message]
2025-08-06 17:15   ` patchwork-bot+linux-riscv

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