From: "Timur Kristóf" <timur.kristof@gmail.com>
To: amd-gfx@lists.freedesktop.org,
Alex Deucher <alexander.deucher@amd.com>,
christian.koenig@amd.com, pierre-eric.pelloux-prayer@amd.com,
Natalie Vock <natalie.vock@gmx.de>,
Tvrtko Ursulin <tursulin@ursulin.net>
Subject: Re: [PATCH 07/11] drm/amdgpu/gfx6: Properly enable/disable priv_req and priv_inst interrupts
Date: Wed, 15 Jul 2026 21:23:07 +0200 [thread overview]
Message-ID: <178429166.VBMTVartND@timur-max> (raw)
In-Reply-To: <d56d2eef-0bd1-4289-b315-8ecb7f5d01eb@ursulin.net>
On 2026. július 15., szerda 13:22:21 közép-európai nyári idő Tvrtko Ursulin
wrote:
> On 15/07/2026 11:53, Timur Kristóf wrote:
> > On 2026. július 15., szerda 12:19:40 közép-európai nyári idő Tvrtko
> > Ursulin
> >
> > wrote:
> >> On 13/07/2026 14:07, Timur Kristóf wrote:
> >>> These were used without ever calling get()/put() on them.
> >>
> >>> Implement it like on GFX7-8:
> >> Used as in how? Are they even enabled without this change and if not
> >> then does this patch fixes something other than being prep work for soft
> >> reset?
> >
> > If you open gfx_v6_0.c and search for priv_reg or priv_inst, you can see
> > that the interrupts are used in the same manner as gfx7 and newer, but
> > without get() and put().
>
> Yes, they are used in code. Are they used in reality was my question. :)
Looking at the code I think the original intention was to wire up these
interrupts. I think the hardware actually supports these interrupts and the
author of the code simply forgot to call get() and put().
If you are not convinced, maybe Alex or Christian can confirm whether the
interrupt actually exists on this HW generation. If it turns out it doesn't
exist then we should just delete this code.
> I ask because it appears that without amdgpu_irq_get() they may not even
> get enabled so never received. Yes or no? Consequences if yes?
Yes, that sounds correct. The consequence is that the interrupt will now be
enabled and the HW will tell us about some illegal register access and some
illegal instructions when it happens.
To give you additional context: for the purpose of diagnosing issues related
to GPU hangs and recovery, all additional information helps. If the CP has
interrupts to tell us about some error cases, we should absolutely use that.
Side note: from the register definitions it looks like the HW actually supports
other interrupts which would be interesting to enable in the future.
In this patch I just wanted to fix up the two that were already in the code.
>
> >>> * Call amdgpu_irq_get() from gfx_v6_0_late_init()
> >>> * Call amdgpu_irq_put() from gfx_v6_0_hw_fini()
> >>>
> >>> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
> >>> ---
> >>>
> >>> drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 19 +++++++++++++++++++
> >>> 1 file changed, 19 insertions(+)
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> >>> b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index 5b570a4b5c01..1c7cd265fbca
> >>> 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> >>> @@ -3131,6 +3131,22 @@ static int gfx_v6_0_early_init(struct
> >>> amdgpu_ip_block *ip_block)>
> >>>
> >>> return 0;
> >>>
> >>> }
> >>>
> >>> +static int gfx_v6_0_late_init(struct amdgpu_ip_block *ip_block)
> >>> +{
> >>> + struct amdgpu_device *adev = ip_block->adev;
> >>> + int r;
> >>> +
> >>> + r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
> >>> + if (r)
> >>> + return r;
> >>> +
> >>> + r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
> >>> + if (r)
> >>> + return r;
> >>> +
> >>> + return 0;
> >>> +}
> >>> +
> >>>
> >>> static int gfx_v6_0_sw_init(struct amdgpu_ip_block *ip_block)
> >>> {
> >>>
> >>> struct amdgpu_ring *ring;
> >>>
> >>> @@ -3243,6 +3259,8 @@ static int gfx_v6_0_hw_fini(struct amdgpu_ip_block
> >>> *ip_block)>
> >>>
> >>> {
> >>>
> >>> struct amdgpu_device *adev = ip_block->adev;
> >>>
> >>> + amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
> >>> + amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
> >>>
> >>> gfx_v6_0_cp_enable(adev, false);
> >>> adev->gfx.rlc.funcs->stop(adev);
> >>> gfx_v6_0_fini_pg(adev);
> >>>
> >>> @@ -3532,6 +3550,7 @@ static void gfx_v6_0_emit_mem_sync(struct
> >>> amdgpu_ring *ring)>
> >>>
> >>> static const struct amd_ip_funcs gfx_v6_0_ip_funcs = {
> >>>
> >>> .name = "gfx_v6_0",
> >>> .early_init = gfx_v6_0_early_init,
> >>>
> >>> + .late_init = gfx_v6_0_late_init,
> >>>
> >>> .sw_init = gfx_v6_0_sw_init,
> >>> .sw_fini = gfx_v6_0_sw_fini,
> >>> .hw_init = gfx_v6_0_hw_init,
next prev parent reply other threads:[~2026-07-15 19:23 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-13 13:06 [PATCH 00/11] drm/amdgpu/gfx6: Use GFX IP block soft reset on GFX6 Timur Kristóf
2026-07-13 13:06 ` [PATCH 01/11] drm/amdgpu/gfx6: Improve emit_cntxcntl() Timur Kristóf
2026-07-13 13:07 ` [PATCH 02/11] drm/amdgpu/gfx6: Fixup emitting SWITCH_BUFFER packets Timur Kristóf
2026-07-13 13:07 ` [PATCH 03/11] drm/amdgpu/gfx6: Use PFP on the compute queues too Timur Kristóf
2026-07-13 13:07 ` [PATCH 04/11] drm/amdgpu/gfx6: Initialize compute rings before CP start Timur Kristóf
2026-07-13 13:07 ` [PATCH 05/11] drm/amdgpu/gfx6: Clean up rings during reset Timur Kristóf
2026-07-13 13:07 ` [PATCH 06/11] drm/amdgpu/gfx6: Execute CLEAR_STATE when initializing compute rings Timur Kristóf
2026-07-13 13:07 ` [PATCH 07/11] drm/amdgpu/gfx6: Properly enable/disable priv_req and priv_inst interrupts Timur Kristóf
2026-07-15 10:19 ` Tvrtko Ursulin
2026-07-15 10:53 ` Timur Kristóf
2026-07-15 11:22 ` Tvrtko Ursulin
2026-07-15 19:23 ` Timur Kristóf [this message]
2026-07-13 13:07 ` [PATCH 08/11] drm/amdgpu/gfx6: Adjust how harvested TCCs are set up Timur Kristóf
2026-07-13 13:07 ` [PATCH 09/11] drm/amdgpu/gfx6: Use COND_EXEC Timur Kristóf
2026-07-13 13:07 ` [PATCH 10/11] drm/amdgpu/gfx6: Add IP block soft reset implementation Timur Kristóf
2026-07-13 13:07 ` [PATCH 11/11] drm/amdgpu/gfx6: Enable IP block soft reset as a GPU recovery method Timur Kristóf
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