* [PATCH v5 00/11] soc: rockchip: power-domain: add rk3568 powerdomains @ 2021-03-26 9:15 ` Elaine Zhang 0 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:15 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Fix power-controller node names for dtbs_check. Convert power domain documentation to json-schema. Add a meaningful power domain name. Support power domain function for RK3568 Soc. Change in V5: [PATCH v5 1/11]: New. [PATCH v5 2/11]: New. [PATCH v5 3/11]: New. [PATCH v5 4/11]: New. [PATCH v5 5/11]: New. [PATCH v5 6/11]: New. [PATCH v5 7/11]: New. [PATCH v5 8/11]: No change. Same as [PATCH v4 1/4]. [PATCH v5 9/11]: [PATCH v4 2/4] Fix up yaml code styles. [PATCH v5 10/11]: No change. Same as [PATCH v4 3/4]. [PATCH v5 11/11]: [PATCH v4 4/4] add a meaningful power domain name for RK3568 Soc. Change in V4: [PATCH v4 1/4]: No change. [PATCH v4 2/4]: Fix up yaml code styles. Remove the new compatible to [PATCH v4 3/4] [PATCH v4 3/4]: Adding new compatible for RK3568 Soc. [PATCH v4 4/4]: No change. Same as [PATCH v3 3/3]. Change in V3: [PATCH v3 1/3]: No change. [PATCH v3 2/3]: Fix up the code styles and add rk3568 base on: https://patchwork.kernel.org/project/linux-rockchip/patch/20210225102643.653095-1-enric.balletbo@collabora.com/ [PATCH v3 3/3]: No change. Change in V2: [PATCH v2 1/3]: No change. [PATCH v2 2/3]: Fix up yaml code styles. [PATCH v2 3/3]: No change. Elaine Zhang (11): arm: dts: rockchip: Fix power-controller node names for rk3066a arm: dts: rockchip: Fix power-controller node names for rk3188 arm: dts: rockchip: Fix power-controller node names for rk3288 arm64: dts: rockchip: Fix power-controller node names for px30 arm64: dts: rockchip: Fix power-controller node names for rk3328 arm64: dts: rockchip: Fix power-controller node names for rk3399 soc: rockchip: pm-domains: Add a meaningful power domain name dt-bindings: add power-domain header for RK3568 SoCs dt-bindings: power: rockchip: Convert to json-schema dt-bindings: power: rockchip: Add bindings for RK3568 Soc soc: rockchip: power-domain: add rk3568 powerdomains .../power/rockchip,power-controller.yaml | 293 ++++++++++++++++++ .../bindings/soc/rockchip/power_domain.txt | 136 -------- arch/arm/boot/dts/rk3066a.dtsi | 6 +- arch/arm/boot/dts/rk3188.dtsi | 6 +- arch/arm/boot/dts/rk3288.dtsi | 8 +- arch/arm64/boot/dts/rockchip/px30.dtsi | 16 +- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 +- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 40 +-- drivers/soc/rockchip/pm_domains.c | 248 ++++++++------- include/dt-bindings/power/rk3568-power.h | 32 ++ 10 files changed, 509 insertions(+), 282 deletions(-) create mode 100644 Documentation/devicetree/bindings/power/rockchip,power-controller.yaml delete mode 100644 Documentation/devicetree/bindings/soc/rockchip/power_domain.txt create mode 100644 include/dt-bindings/power/rk3568-power.h -- 2.17.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v5 00/11] soc: rockchip: power-domain: add rk3568 powerdomains @ 2021-03-26 9:15 ` Elaine Zhang 0 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:15 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Fix power-controller node names for dtbs_check. Convert power domain documentation to json-schema. Add a meaningful power domain name. Support power domain function for RK3568 Soc. Change in V5: [PATCH v5 1/11]: New. [PATCH v5 2/11]: New. [PATCH v5 3/11]: New. [PATCH v5 4/11]: New. [PATCH v5 5/11]: New. [PATCH v5 6/11]: New. [PATCH v5 7/11]: New. [PATCH v5 8/11]: No change. Same as [PATCH v4 1/4]. [PATCH v5 9/11]: [PATCH v4 2/4] Fix up yaml code styles. [PATCH v5 10/11]: No change. Same as [PATCH v4 3/4]. [PATCH v5 11/11]: [PATCH v4 4/4] add a meaningful power domain name for RK3568 Soc. Change in V4: [PATCH v4 1/4]: No change. [PATCH v4 2/4]: Fix up yaml code styles. Remove the new compatible to [PATCH v4 3/4] [PATCH v4 3/4]: Adding new compatible for RK3568 Soc. [PATCH v4 4/4]: No change. Same as [PATCH v3 3/3]. Change in V3: [PATCH v3 1/3]: No change. [PATCH v3 2/3]: Fix up the code styles and add rk3568 base on: https://patchwork.kernel.org/project/linux-rockchip/patch/20210225102643.653095-1-enric.balletbo@collabora.com/ [PATCH v3 3/3]: No change. Change in V2: [PATCH v2 1/3]: No change. [PATCH v2 2/3]: Fix up yaml code styles. [PATCH v2 3/3]: No change. Elaine Zhang (11): arm: dts: rockchip: Fix power-controller node names for rk3066a arm: dts: rockchip: Fix power-controller node names for rk3188 arm: dts: rockchip: Fix power-controller node names for rk3288 arm64: dts: rockchip: Fix power-controller node names for px30 arm64: dts: rockchip: Fix power-controller node names for rk3328 arm64: dts: rockchip: Fix power-controller node names for rk3399 soc: rockchip: pm-domains: Add a meaningful power domain name dt-bindings: add power-domain header for RK3568 SoCs dt-bindings: power: rockchip: Convert to json-schema dt-bindings: power: rockchip: Add bindings for RK3568 Soc soc: rockchip: power-domain: add rk3568 powerdomains .../power/rockchip,power-controller.yaml | 293 ++++++++++++++++++ .../bindings/soc/rockchip/power_domain.txt | 136 -------- arch/arm/boot/dts/rk3066a.dtsi | 6 +- arch/arm/boot/dts/rk3188.dtsi | 6 +- arch/arm/boot/dts/rk3288.dtsi | 8 +- arch/arm64/boot/dts/rockchip/px30.dtsi | 16 +- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 +- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 40 +-- drivers/soc/rockchip/pm_domains.c | 248 ++++++++------- include/dt-bindings/power/rk3568-power.h | 32 ++ 10 files changed, 509 insertions(+), 282 deletions(-) create mode 100644 Documentation/devicetree/bindings/power/rockchip,power-controller.yaml delete mode 100644 Documentation/devicetree/bindings/soc/rockchip/power_domain.txt create mode 100644 include/dt-bindings/power/rk3568-power.h -- 2.17.1 ^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v5 00/11] soc: rockchip: power-domain: add rk3568 powerdomains @ 2021-03-26 9:15 ` Elaine Zhang 0 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:15 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Fix power-controller node names for dtbs_check. Convert power domain documentation to json-schema. Add a meaningful power domain name. Support power domain function for RK3568 Soc. Change in V5: [PATCH v5 1/11]: New. [PATCH v5 2/11]: New. [PATCH v5 3/11]: New. [PATCH v5 4/11]: New. [PATCH v5 5/11]: New. [PATCH v5 6/11]: New. [PATCH v5 7/11]: New. [PATCH v5 8/11]: No change. Same as [PATCH v4 1/4]. [PATCH v5 9/11]: [PATCH v4 2/4] Fix up yaml code styles. [PATCH v5 10/11]: No change. Same as [PATCH v4 3/4]. [PATCH v5 11/11]: [PATCH v4 4/4] add a meaningful power domain name for RK3568 Soc. Change in V4: [PATCH v4 1/4]: No change. [PATCH v4 2/4]: Fix up yaml code styles. Remove the new compatible to [PATCH v4 3/4] [PATCH v4 3/4]: Adding new compatible for RK3568 Soc. [PATCH v4 4/4]: No change. Same as [PATCH v3 3/3]. Change in V3: [PATCH v3 1/3]: No change. [PATCH v3 2/3]: Fix up the code styles and add rk3568 base on: https://patchwork.kernel.org/project/linux-rockchip/patch/20210225102643.653095-1-enric.balletbo@collabora.com/ [PATCH v3 3/3]: No change. Change in V2: [PATCH v2 1/3]: No change. [PATCH v2 2/3]: Fix up yaml code styles. [PATCH v2 3/3]: No change. Elaine Zhang (11): arm: dts: rockchip: Fix power-controller node names for rk3066a arm: dts: rockchip: Fix power-controller node names for rk3188 arm: dts: rockchip: Fix power-controller node names for rk3288 arm64: dts: rockchip: Fix power-controller node names for px30 arm64: dts: rockchip: Fix power-controller node names for rk3328 arm64: dts: rockchip: Fix power-controller node names for rk3399 soc: rockchip: pm-domains: Add a meaningful power domain name dt-bindings: add power-domain header for RK3568 SoCs dt-bindings: power: rockchip: Convert to json-schema dt-bindings: power: rockchip: Add bindings for RK3568 Soc soc: rockchip: power-domain: add rk3568 powerdomains .../power/rockchip,power-controller.yaml | 293 ++++++++++++++++++ .../bindings/soc/rockchip/power_domain.txt | 136 -------- arch/arm/boot/dts/rk3066a.dtsi | 6 +- arch/arm/boot/dts/rk3188.dtsi | 6 +- arch/arm/boot/dts/rk3288.dtsi | 8 +- arch/arm64/boot/dts/rockchip/px30.dtsi | 16 +- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 +- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 40 +-- drivers/soc/rockchip/pm_domains.c | 248 ++++++++------- include/dt-bindings/power/rk3568-power.h | 32 ++ 10 files changed, 509 insertions(+), 282 deletions(-) create mode 100644 Documentation/devicetree/bindings/power/rockchip,power-controller.yaml delete mode 100644 Documentation/devicetree/bindings/soc/rockchip/power_domain.txt create mode 100644 include/dt-bindings/power/rk3568-power.h -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v5 01/11] arm: dts: rockchip: Fix power-controller node names for rk3066a 2021-03-26 9:15 ` Elaine Zhang (?) @ 2021-03-26 9:15 ` Elaine Zhang -1 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:15 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Use more generic names (as recommended in the device tree specification or the binding documentation) Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- arch/arm/boot/dts/rk3066a.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 252750c97f97..bbc3bff50856 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -755,7 +755,7 @@ #address-cells = <1>; #size-cells = <0>; - pd_vio@RK3066_PD_VIO { + power-domain@RK3066_PD_VIO { reg = <RK3066_PD_VIO>; clocks = <&cru ACLK_LCDC0>, <&cru ACLK_LCDC1>, @@ -782,7 +782,7 @@ <&qos_rga>; }; - pd_video@RK3066_PD_VIDEO { + power-domain@RK3066_PD_VIDEO { reg = <RK3066_PD_VIDEO>; clocks = <&cru ACLK_VDPU>, <&cru ACLK_VEPU>, @@ -791,7 +791,7 @@ pm_qos = <&qos_vpu>; }; - pd_gpu@RK3066_PD_GPU { + power-domain@RK3066_PD_GPU { reg = <RK3066_PD_GPU>; clocks = <&cru ACLK_GPU>; pm_qos = <&qos_gpu>; -- 2.17.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v5 01/11] arm: dts: rockchip: Fix power-controller node names for rk3066a @ 2021-03-26 9:15 ` Elaine Zhang 0 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:15 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Use more generic names (as recommended in the device tree specification or the binding documentation) Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- arch/arm/boot/dts/rk3066a.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 252750c97f97..bbc3bff50856 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -755,7 +755,7 @@ #address-cells = <1>; #size-cells = <0>; - pd_vio@RK3066_PD_VIO { + power-domain@RK3066_PD_VIO { reg = <RK3066_PD_VIO>; clocks = <&cru ACLK_LCDC0>, <&cru ACLK_LCDC1>, @@ -782,7 +782,7 @@ <&qos_rga>; }; - pd_video@RK3066_PD_VIDEO { + power-domain@RK3066_PD_VIDEO { reg = <RK3066_PD_VIDEO>; clocks = <&cru ACLK_VDPU>, <&cru ACLK_VEPU>, @@ -791,7 +791,7 @@ pm_qos = <&qos_vpu>; }; - pd_gpu@RK3066_PD_GPU { + power-domain@RK3066_PD_GPU { reg = <RK3066_PD_GPU>; clocks = <&cru ACLK_GPU>; pm_qos = <&qos_gpu>; -- 2.17.1 ^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v5 01/11] arm: dts: rockchip: Fix power-controller node names for rk3066a @ 2021-03-26 9:15 ` Elaine Zhang 0 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:15 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Use more generic names (as recommended in the device tree specification or the binding documentation) Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- arch/arm/boot/dts/rk3066a.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 252750c97f97..bbc3bff50856 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -755,7 +755,7 @@ #address-cells = <1>; #size-cells = <0>; - pd_vio@RK3066_PD_VIO { + power-domain@RK3066_PD_VIO { reg = <RK3066_PD_VIO>; clocks = <&cru ACLK_LCDC0>, <&cru ACLK_LCDC1>, @@ -782,7 +782,7 @@ <&qos_rga>; }; - pd_video@RK3066_PD_VIDEO { + power-domain@RK3066_PD_VIDEO { reg = <RK3066_PD_VIDEO>; clocks = <&cru ACLK_VDPU>, <&cru ACLK_VEPU>, @@ -791,7 +791,7 @@ pm_qos = <&qos_vpu>; }; - pd_gpu@RK3066_PD_GPU { + power-domain@RK3066_PD_GPU { reg = <RK3066_PD_GPU>; clocks = <&cru ACLK_GPU>; pm_qos = <&qos_gpu>; -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 75+ messages in thread
* Re: [PATCH v5 01/11] arm: dts: rockchip: Fix power-controller node names for rk3066a 2021-03-26 9:15 ` Elaine Zhang (?) @ 2021-03-26 9:40 ` Enric Balletbo Serra -1 siblings, 0 replies; 75+ messages in thread From: Enric Balletbo Serra @ 2021-03-26 9:40 UTC (permalink / raw) To: Elaine Zhang Cc: Rob Herring, Heiko Stübner, devicetree@vger.kernel.org, Linux ARM, open list:ARM/Rockchip SoC..., linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao i Missatge de Elaine Zhang <zhangqing@rock-chips.com> del dia dv., 26 de març 2021 a les 10:17: > > Use more generic names (as recommended in the device tree specification > or the binding documentation) > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > --- > arch/arm/boot/dts/rk3066a.dtsi | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi > index 252750c97f97..bbc3bff50856 100644 > --- a/arch/arm/boot/dts/rk3066a.dtsi > +++ b/arch/arm/boot/dts/rk3066a.dtsi > @@ -755,7 +755,7 @@ > #address-cells = <1>; > #size-cells = <0>; > > - pd_vio@RK3066_PD_VIO { > + power-domain@RK3066_PD_VIO { > reg = <RK3066_PD_VIO>; > clocks = <&cru ACLK_LCDC0>, > <&cru ACLK_LCDC1>, > @@ -782,7 +782,7 @@ > <&qos_rga>; > }; > > - pd_video@RK3066_PD_VIDEO { > + power-domain@RK3066_PD_VIDEO { > reg = <RK3066_PD_VIDEO>; > clocks = <&cru ACLK_VDPU>, > <&cru ACLK_VEPU>, > @@ -791,7 +791,7 @@ > pm_qos = <&qos_vpu>; > }; > > - pd_gpu@RK3066_PD_GPU { > + power-domain@RK3066_PD_GPU { > reg = <RK3066_PD_GPU>; > clocks = <&cru ACLK_GPU>; > pm_qos = <&qos_gpu>; > -- > 2.17.1 > > > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v5 01/11] arm: dts: rockchip: Fix power-controller node names for rk3066a @ 2021-03-26 9:40 ` Enric Balletbo Serra 0 siblings, 0 replies; 75+ messages in thread From: Enric Balletbo Serra @ 2021-03-26 9:40 UTC (permalink / raw) To: Elaine Zhang Cc: Rob Herring, Heiko Stübner, devicetree@vger.kernel.org, Linux ARM, open list:ARM/Rockchip SoC..., linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao i Missatge de Elaine Zhang <zhangqing@rock-chips.com> del dia dv., 26 de març 2021 a les 10:17: > > Use more generic names (as recommended in the device tree specification > or the binding documentation) > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > --- > arch/arm/boot/dts/rk3066a.dtsi | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi > index 252750c97f97..bbc3bff50856 100644 > --- a/arch/arm/boot/dts/rk3066a.dtsi > +++ b/arch/arm/boot/dts/rk3066a.dtsi > @@ -755,7 +755,7 @@ > #address-cells = <1>; > #size-cells = <0>; > > - pd_vio@RK3066_PD_VIO { > + power-domain@RK3066_PD_VIO { > reg = <RK3066_PD_VIO>; > clocks = <&cru ACLK_LCDC0>, > <&cru ACLK_LCDC1>, > @@ -782,7 +782,7 @@ > <&qos_rga>; > }; > > - pd_video@RK3066_PD_VIDEO { > + power-domain@RK3066_PD_VIDEO { > reg = <RK3066_PD_VIDEO>; > clocks = <&cru ACLK_VDPU>, > <&cru ACLK_VEPU>, > @@ -791,7 +791,7 @@ > pm_qos = <&qos_vpu>; > }; > > - pd_gpu@RK3066_PD_GPU { > + power-domain@RK3066_PD_GPU { > reg = <RK3066_PD_GPU>; > clocks = <&cru ACLK_GPU>; > pm_qos = <&qos_gpu>; > -- > 2.17.1 > > > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v5 01/11] arm: dts: rockchip: Fix power-controller node names for rk3066a @ 2021-03-26 9:40 ` Enric Balletbo Serra 0 siblings, 0 replies; 75+ messages in thread From: Enric Balletbo Serra @ 2021-03-26 9:40 UTC (permalink / raw) To: Elaine Zhang Cc: Rob Herring, Heiko Stübner, devicetree@vger.kernel.org, Linux ARM, open list:ARM/Rockchip SoC..., linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao i Missatge de Elaine Zhang <zhangqing@rock-chips.com> del dia dv., 26 de març 2021 a les 10:17: > > Use more generic names (as recommended in the device tree specification > or the binding documentation) > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > --- > arch/arm/boot/dts/rk3066a.dtsi | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi > index 252750c97f97..bbc3bff50856 100644 > --- a/arch/arm/boot/dts/rk3066a.dtsi > +++ b/arch/arm/boot/dts/rk3066a.dtsi > @@ -755,7 +755,7 @@ > #address-cells = <1>; > #size-cells = <0>; > > - pd_vio@RK3066_PD_VIO { > + power-domain@RK3066_PD_VIO { > reg = <RK3066_PD_VIO>; > clocks = <&cru ACLK_LCDC0>, > <&cru ACLK_LCDC1>, > @@ -782,7 +782,7 @@ > <&qos_rga>; > }; > > - pd_video@RK3066_PD_VIDEO { > + power-domain@RK3066_PD_VIDEO { > reg = <RK3066_PD_VIDEO>; > clocks = <&cru ACLK_VDPU>, > <&cru ACLK_VEPU>, > @@ -791,7 +791,7 @@ > pm_qos = <&qos_vpu>; > }; > > - pd_gpu@RK3066_PD_GPU { > + power-domain@RK3066_PD_GPU { > reg = <RK3066_PD_GPU>; > clocks = <&cru ACLK_GPU>; > pm_qos = <&qos_gpu>; > -- > 2.17.1 > > > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v5 02/11] arm: dts: rockchip: Fix power-controller node names for rk3188 2021-03-26 9:15 ` Elaine Zhang (?) @ 2021-03-26 9:15 ` Elaine Zhang -1 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:15 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Use more generic names (as recommended in the device tree specification or the binding documentation) Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- arch/arm/boot/dts/rk3188.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 2298a8d840ba..5db32fdbe6e7 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -699,7 +699,7 @@ #address-cells = <1>; #size-cells = <0>; - pd_vio@RK3188_PD_VIO { + power-domain@RK3188_PD_VIO { reg = <RK3188_PD_VIO>; clocks = <&cru ACLK_LCDC0>, <&cru ACLK_LCDC1>, @@ -721,7 +721,7 @@ <&qos_rga>; }; - pd_video@RK3188_PD_VIDEO { + power-domain@RK3188_PD_VIDEO { reg = <RK3188_PD_VIDEO>; clocks = <&cru ACLK_VDPU>, <&cru ACLK_VEPU>, @@ -730,7 +730,7 @@ pm_qos = <&qos_vpu>; }; - pd_gpu@RK3188_PD_GPU { + power-domain@RK3188_PD_GPU { reg = <RK3188_PD_GPU>; clocks = <&cru ACLK_GPU>; pm_qos = <&qos_gpu>; -- 2.17.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v5 02/11] arm: dts: rockchip: Fix power-controller node names for rk3188 @ 2021-03-26 9:15 ` Elaine Zhang 0 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:15 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Use more generic names (as recommended in the device tree specification or the binding documentation) Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- arch/arm/boot/dts/rk3188.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 2298a8d840ba..5db32fdbe6e7 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -699,7 +699,7 @@ #address-cells = <1>; #size-cells = <0>; - pd_vio@RK3188_PD_VIO { + power-domain@RK3188_PD_VIO { reg = <RK3188_PD_VIO>; clocks = <&cru ACLK_LCDC0>, <&cru ACLK_LCDC1>, @@ -721,7 +721,7 @@ <&qos_rga>; }; - pd_video@RK3188_PD_VIDEO { + power-domain@RK3188_PD_VIDEO { reg = <RK3188_PD_VIDEO>; clocks = <&cru ACLK_VDPU>, <&cru ACLK_VEPU>, @@ -730,7 +730,7 @@ pm_qos = <&qos_vpu>; }; - pd_gpu@RK3188_PD_GPU { + power-domain@RK3188_PD_GPU { reg = <RK3188_PD_GPU>; clocks = <&cru ACLK_GPU>; pm_qos = <&qos_gpu>; -- 2.17.1 ^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v5 02/11] arm: dts: rockchip: Fix power-controller node names for rk3188 @ 2021-03-26 9:15 ` Elaine Zhang 0 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:15 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Use more generic names (as recommended in the device tree specification or the binding documentation) Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- arch/arm/boot/dts/rk3188.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 2298a8d840ba..5db32fdbe6e7 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -699,7 +699,7 @@ #address-cells = <1>; #size-cells = <0>; - pd_vio@RK3188_PD_VIO { + power-domain@RK3188_PD_VIO { reg = <RK3188_PD_VIO>; clocks = <&cru ACLK_LCDC0>, <&cru ACLK_LCDC1>, @@ -721,7 +721,7 @@ <&qos_rga>; }; - pd_video@RK3188_PD_VIDEO { + power-domain@RK3188_PD_VIDEO { reg = <RK3188_PD_VIDEO>; clocks = <&cru ACLK_VDPU>, <&cru ACLK_VEPU>, @@ -730,7 +730,7 @@ pm_qos = <&qos_vpu>; }; - pd_gpu@RK3188_PD_GPU { + power-domain@RK3188_PD_GPU { reg = <RK3188_PD_GPU>; clocks = <&cru ACLK_GPU>; pm_qos = <&qos_gpu>; -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 75+ messages in thread
* Re: [PATCH v5 02/11] arm: dts: rockchip: Fix power-controller node names for rk3188 2021-03-26 9:15 ` Elaine Zhang (?) @ 2021-03-26 9:40 ` Enric Balletbo Serra -1 siblings, 0 replies; 75+ messages in thread From: Enric Balletbo Serra @ 2021-03-26 9:40 UTC (permalink / raw) To: Elaine Zhang Cc: Rob Herring, Heiko Stübner, devicetree@vger.kernel.org, Linux ARM, open list:ARM/Rockchip SoC..., linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao Missatge de Elaine Zhang <zhangqing@rock-chips.com> del dia dv., 26 de març 2021 a les 10:17: > > Use more generic names (as recommended in the device tree specification > or the binding documentation) > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > --- > arch/arm/boot/dts/rk3188.dtsi | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi > index 2298a8d840ba..5db32fdbe6e7 100644 > --- a/arch/arm/boot/dts/rk3188.dtsi > +++ b/arch/arm/boot/dts/rk3188.dtsi > @@ -699,7 +699,7 @@ > #address-cells = <1>; > #size-cells = <0>; > > - pd_vio@RK3188_PD_VIO { > + power-domain@RK3188_PD_VIO { > reg = <RK3188_PD_VIO>; > clocks = <&cru ACLK_LCDC0>, > <&cru ACLK_LCDC1>, > @@ -721,7 +721,7 @@ > <&qos_rga>; > }; > > - pd_video@RK3188_PD_VIDEO { > + power-domain@RK3188_PD_VIDEO { > reg = <RK3188_PD_VIDEO>; > clocks = <&cru ACLK_VDPU>, > <&cru ACLK_VEPU>, > @@ -730,7 +730,7 @@ > pm_qos = <&qos_vpu>; > }; > > - pd_gpu@RK3188_PD_GPU { > + power-domain@RK3188_PD_GPU { > reg = <RK3188_PD_GPU>; > clocks = <&cru ACLK_GPU>; > pm_qos = <&qos_gpu>; > -- > 2.17.1 > > > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v5 02/11] arm: dts: rockchip: Fix power-controller node names for rk3188 @ 2021-03-26 9:40 ` Enric Balletbo Serra 0 siblings, 0 replies; 75+ messages in thread From: Enric Balletbo Serra @ 2021-03-26 9:40 UTC (permalink / raw) To: Elaine Zhang Cc: Rob Herring, Heiko Stübner, devicetree@vger.kernel.org, Linux ARM, open list:ARM/Rockchip SoC..., linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao Missatge de Elaine Zhang <zhangqing@rock-chips.com> del dia dv., 26 de març 2021 a les 10:17: > > Use more generic names (as recommended in the device tree specification > or the binding documentation) > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > --- > arch/arm/boot/dts/rk3188.dtsi | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi > index 2298a8d840ba..5db32fdbe6e7 100644 > --- a/arch/arm/boot/dts/rk3188.dtsi > +++ b/arch/arm/boot/dts/rk3188.dtsi > @@ -699,7 +699,7 @@ > #address-cells = <1>; > #size-cells = <0>; > > - pd_vio@RK3188_PD_VIO { > + power-domain@RK3188_PD_VIO { > reg = <RK3188_PD_VIO>; > clocks = <&cru ACLK_LCDC0>, > <&cru ACLK_LCDC1>, > @@ -721,7 +721,7 @@ > <&qos_rga>; > }; > > - pd_video@RK3188_PD_VIDEO { > + power-domain@RK3188_PD_VIDEO { > reg = <RK3188_PD_VIDEO>; > clocks = <&cru ACLK_VDPU>, > <&cru ACLK_VEPU>, > @@ -730,7 +730,7 @@ > pm_qos = <&qos_vpu>; > }; > > - pd_gpu@RK3188_PD_GPU { > + power-domain@RK3188_PD_GPU { > reg = <RK3188_PD_GPU>; > clocks = <&cru ACLK_GPU>; > pm_qos = <&qos_gpu>; > -- > 2.17.1 > > > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v5 02/11] arm: dts: rockchip: Fix power-controller node names for rk3188 @ 2021-03-26 9:40 ` Enric Balletbo Serra 0 siblings, 0 replies; 75+ messages in thread From: Enric Balletbo Serra @ 2021-03-26 9:40 UTC (permalink / raw) To: Elaine Zhang Cc: Rob Herring, Heiko Stübner, devicetree@vger.kernel.org, Linux ARM, open list:ARM/Rockchip SoC..., linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao Missatge de Elaine Zhang <zhangqing@rock-chips.com> del dia dv., 26 de març 2021 a les 10:17: > > Use more generic names (as recommended in the device tree specification > or the binding documentation) > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > --- > arch/arm/boot/dts/rk3188.dtsi | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi > index 2298a8d840ba..5db32fdbe6e7 100644 > --- a/arch/arm/boot/dts/rk3188.dtsi > +++ b/arch/arm/boot/dts/rk3188.dtsi > @@ -699,7 +699,7 @@ > #address-cells = <1>; > #size-cells = <0>; > > - pd_vio@RK3188_PD_VIO { > + power-domain@RK3188_PD_VIO { > reg = <RK3188_PD_VIO>; > clocks = <&cru ACLK_LCDC0>, > <&cru ACLK_LCDC1>, > @@ -721,7 +721,7 @@ > <&qos_rga>; > }; > > - pd_video@RK3188_PD_VIDEO { > + power-domain@RK3188_PD_VIDEO { > reg = <RK3188_PD_VIDEO>; > clocks = <&cru ACLK_VDPU>, > <&cru ACLK_VEPU>, > @@ -730,7 +730,7 @@ > pm_qos = <&qos_vpu>; > }; > > - pd_gpu@RK3188_PD_GPU { > + power-domain@RK3188_PD_GPU { > reg = <RK3188_PD_GPU>; > clocks = <&cru ACLK_GPU>; > pm_qos = <&qos_gpu>; > -- > 2.17.1 > > > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v5 03/11] arm: dts: rockchip: Fix power-controller node names for rk3288 2021-03-26 9:15 ` Elaine Zhang (?) @ 2021-03-26 9:15 ` Elaine Zhang -1 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:15 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Use more generic names (as recommended in the device tree specification or the binding documentation) Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- arch/arm/boot/dts/rk3288.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index ea7416c31f9b..6f4d7929e351 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -769,7 +769,7 @@ * *_HDMI HDMI * *_MIPI_* MIPI */ - pd_vio@RK3288_PD_VIO { + power-domain@RK3288_PD_VIO { reg = <RK3288_PD_VIO>; clocks = <&cru ACLK_IEP>, <&cru ACLK_ISP>, @@ -811,7 +811,7 @@ * Note: The following 3 are HEVC(H.265) clocks, * and on the ACLK_HEVC_NIU (NOC). */ - pd_hevc@RK3288_PD_HEVC { + power-domain@RK3288_PD_HEVC { reg = <RK3288_PD_HEVC>; clocks = <&cru ACLK_HEVC>, <&cru SCLK_HEVC_CABAC>, @@ -825,7 +825,7 @@ * (video endecoder & decoder) clocks that on the * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC). */ - pd_video@RK3288_PD_VIDEO { + power-domain@RK3288_PD_VIDEO { reg = <RK3288_PD_VIDEO>; clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; @@ -836,7 +836,7 @@ * Note: ACLK_GPU is the GPU clock, * and on the ACLK_GPU_NIU (NOC). */ - pd_gpu@RK3288_PD_GPU { + power-domain@RK3288_PD_GPU { reg = <RK3288_PD_GPU>; clocks = <&cru ACLK_GPU>; pm_qos = <&qos_gpu_r>, -- 2.17.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v5 03/11] arm: dts: rockchip: Fix power-controller node names for rk3288 @ 2021-03-26 9:15 ` Elaine Zhang 0 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:15 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Use more generic names (as recommended in the device tree specification or the binding documentation) Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- arch/arm/boot/dts/rk3288.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index ea7416c31f9b..6f4d7929e351 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -769,7 +769,7 @@ * *_HDMI HDMI * *_MIPI_* MIPI */ - pd_vio@RK3288_PD_VIO { + power-domain@RK3288_PD_VIO { reg = <RK3288_PD_VIO>; clocks = <&cru ACLK_IEP>, <&cru ACLK_ISP>, @@ -811,7 +811,7 @@ * Note: The following 3 are HEVC(H.265) clocks, * and on the ACLK_HEVC_NIU (NOC). */ - pd_hevc@RK3288_PD_HEVC { + power-domain@RK3288_PD_HEVC { reg = <RK3288_PD_HEVC>; clocks = <&cru ACLK_HEVC>, <&cru SCLK_HEVC_CABAC>, @@ -825,7 +825,7 @@ * (video endecoder & decoder) clocks that on the * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC). */ - pd_video@RK3288_PD_VIDEO { + power-domain@RK3288_PD_VIDEO { reg = <RK3288_PD_VIDEO>; clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; @@ -836,7 +836,7 @@ * Note: ACLK_GPU is the GPU clock, * and on the ACLK_GPU_NIU (NOC). */ - pd_gpu@RK3288_PD_GPU { + power-domain@RK3288_PD_GPU { reg = <RK3288_PD_GPU>; clocks = <&cru ACLK_GPU>; pm_qos = <&qos_gpu_r>, -- 2.17.1 ^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v5 03/11] arm: dts: rockchip: Fix power-controller node names for rk3288 @ 2021-03-26 9:15 ` Elaine Zhang 0 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:15 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Use more generic names (as recommended in the device tree specification or the binding documentation) Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- arch/arm/boot/dts/rk3288.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index ea7416c31f9b..6f4d7929e351 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -769,7 +769,7 @@ * *_HDMI HDMI * *_MIPI_* MIPI */ - pd_vio@RK3288_PD_VIO { + power-domain@RK3288_PD_VIO { reg = <RK3288_PD_VIO>; clocks = <&cru ACLK_IEP>, <&cru ACLK_ISP>, @@ -811,7 +811,7 @@ * Note: The following 3 are HEVC(H.265) clocks, * and on the ACLK_HEVC_NIU (NOC). */ - pd_hevc@RK3288_PD_HEVC { + power-domain@RK3288_PD_HEVC { reg = <RK3288_PD_HEVC>; clocks = <&cru ACLK_HEVC>, <&cru SCLK_HEVC_CABAC>, @@ -825,7 +825,7 @@ * (video endecoder & decoder) clocks that on the * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC). */ - pd_video@RK3288_PD_VIDEO { + power-domain@RK3288_PD_VIDEO { reg = <RK3288_PD_VIDEO>; clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; @@ -836,7 +836,7 @@ * Note: ACLK_GPU is the GPU clock, * and on the ACLK_GPU_NIU (NOC). */ - pd_gpu@RK3288_PD_GPU { + power-domain@RK3288_PD_GPU { reg = <RK3288_PD_GPU>; clocks = <&cru ACLK_GPU>; pm_qos = <&qos_gpu_r>, -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 75+ messages in thread
* Re: [PATCH v5 03/11] arm: dts: rockchip: Fix power-controller node names for rk3288 2021-03-26 9:15 ` Elaine Zhang (?) @ 2021-03-26 9:40 ` Enric Balletbo Serra -1 siblings, 0 replies; 75+ messages in thread From: Enric Balletbo Serra @ 2021-03-26 9:40 UTC (permalink / raw) To: Elaine Zhang Cc: Rob Herring, Heiko Stübner, devicetree@vger.kernel.org, Linux ARM, open list:ARM/Rockchip SoC..., linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao Missatge de Elaine Zhang <zhangqing@rock-chips.com> del dia dv., 26 de març 2021 a les 10:16: > > Use more generic names (as recommended in the device tree specification > or the binding documentation) > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > --- > arch/arm/boot/dts/rk3288.dtsi | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi > index ea7416c31f9b..6f4d7929e351 100644 > --- a/arch/arm/boot/dts/rk3288.dtsi > +++ b/arch/arm/boot/dts/rk3288.dtsi > @@ -769,7 +769,7 @@ > * *_HDMI HDMI > * *_MIPI_* MIPI > */ > - pd_vio@RK3288_PD_VIO { > + power-domain@RK3288_PD_VIO { > reg = <RK3288_PD_VIO>; > clocks = <&cru ACLK_IEP>, > <&cru ACLK_ISP>, > @@ -811,7 +811,7 @@ > * Note: The following 3 are HEVC(H.265) clocks, > * and on the ACLK_HEVC_NIU (NOC). > */ > - pd_hevc@RK3288_PD_HEVC { > + power-domain@RK3288_PD_HEVC { > reg = <RK3288_PD_HEVC>; > clocks = <&cru ACLK_HEVC>, > <&cru SCLK_HEVC_CABAC>, > @@ -825,7 +825,7 @@ > * (video endecoder & decoder) clocks that on the > * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC). > */ > - pd_video@RK3288_PD_VIDEO { > + power-domain@RK3288_PD_VIDEO { > reg = <RK3288_PD_VIDEO>; > clocks = <&cru ACLK_VCODEC>, > <&cru HCLK_VCODEC>; > @@ -836,7 +836,7 @@ > * Note: ACLK_GPU is the GPU clock, > * and on the ACLK_GPU_NIU (NOC). > */ > - pd_gpu@RK3288_PD_GPU { > + power-domain@RK3288_PD_GPU { > reg = <RK3288_PD_GPU>; > clocks = <&cru ACLK_GPU>; > pm_qos = <&qos_gpu_r>, > -- > 2.17.1 > > > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v5 03/11] arm: dts: rockchip: Fix power-controller node names for rk3288 @ 2021-03-26 9:40 ` Enric Balletbo Serra 0 siblings, 0 replies; 75+ messages in thread From: Enric Balletbo Serra @ 2021-03-26 9:40 UTC (permalink / raw) To: Elaine Zhang Cc: Rob Herring, Heiko Stübner, devicetree@vger.kernel.org, Linux ARM, open list:ARM/Rockchip SoC..., linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao Missatge de Elaine Zhang <zhangqing@rock-chips.com> del dia dv., 26 de març 2021 a les 10:16: > > Use more generic names (as recommended in the device tree specification > or the binding documentation) > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > --- > arch/arm/boot/dts/rk3288.dtsi | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi > index ea7416c31f9b..6f4d7929e351 100644 > --- a/arch/arm/boot/dts/rk3288.dtsi > +++ b/arch/arm/boot/dts/rk3288.dtsi > @@ -769,7 +769,7 @@ > * *_HDMI HDMI > * *_MIPI_* MIPI > */ > - pd_vio@RK3288_PD_VIO { > + power-domain@RK3288_PD_VIO { > reg = <RK3288_PD_VIO>; > clocks = <&cru ACLK_IEP>, > <&cru ACLK_ISP>, > @@ -811,7 +811,7 @@ > * Note: The following 3 are HEVC(H.265) clocks, > * and on the ACLK_HEVC_NIU (NOC). > */ > - pd_hevc@RK3288_PD_HEVC { > + power-domain@RK3288_PD_HEVC { > reg = <RK3288_PD_HEVC>; > clocks = <&cru ACLK_HEVC>, > <&cru SCLK_HEVC_CABAC>, > @@ -825,7 +825,7 @@ > * (video endecoder & decoder) clocks that on the > * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC). > */ > - pd_video@RK3288_PD_VIDEO { > + power-domain@RK3288_PD_VIDEO { > reg = <RK3288_PD_VIDEO>; > clocks = <&cru ACLK_VCODEC>, > <&cru HCLK_VCODEC>; > @@ -836,7 +836,7 @@ > * Note: ACLK_GPU is the GPU clock, > * and on the ACLK_GPU_NIU (NOC). > */ > - pd_gpu@RK3288_PD_GPU { > + power-domain@RK3288_PD_GPU { > reg = <RK3288_PD_GPU>; > clocks = <&cru ACLK_GPU>; > pm_qos = <&qos_gpu_r>, > -- > 2.17.1 > > > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v5 03/11] arm: dts: rockchip: Fix power-controller node names for rk3288 @ 2021-03-26 9:40 ` Enric Balletbo Serra 0 siblings, 0 replies; 75+ messages in thread From: Enric Balletbo Serra @ 2021-03-26 9:40 UTC (permalink / raw) To: Elaine Zhang Cc: Rob Herring, Heiko Stübner, devicetree@vger.kernel.org, Linux ARM, open list:ARM/Rockchip SoC..., linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao Missatge de Elaine Zhang <zhangqing@rock-chips.com> del dia dv., 26 de març 2021 a les 10:16: > > Use more generic names (as recommended in the device tree specification > or the binding documentation) > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > --- > arch/arm/boot/dts/rk3288.dtsi | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi > index ea7416c31f9b..6f4d7929e351 100644 > --- a/arch/arm/boot/dts/rk3288.dtsi > +++ b/arch/arm/boot/dts/rk3288.dtsi > @@ -769,7 +769,7 @@ > * *_HDMI HDMI > * *_MIPI_* MIPI > */ > - pd_vio@RK3288_PD_VIO { > + power-domain@RK3288_PD_VIO { > reg = <RK3288_PD_VIO>; > clocks = <&cru ACLK_IEP>, > <&cru ACLK_ISP>, > @@ -811,7 +811,7 @@ > * Note: The following 3 are HEVC(H.265) clocks, > * and on the ACLK_HEVC_NIU (NOC). > */ > - pd_hevc@RK3288_PD_HEVC { > + power-domain@RK3288_PD_HEVC { > reg = <RK3288_PD_HEVC>; > clocks = <&cru ACLK_HEVC>, > <&cru SCLK_HEVC_CABAC>, > @@ -825,7 +825,7 @@ > * (video endecoder & decoder) clocks that on the > * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC). > */ > - pd_video@RK3288_PD_VIDEO { > + power-domain@RK3288_PD_VIDEO { > reg = <RK3288_PD_VIDEO>; > clocks = <&cru ACLK_VCODEC>, > <&cru HCLK_VCODEC>; > @@ -836,7 +836,7 @@ > * Note: ACLK_GPU is the GPU clock, > * and on the ACLK_GPU_NIU (NOC). > */ > - pd_gpu@RK3288_PD_GPU { > + power-domain@RK3288_PD_GPU { > reg = <RK3288_PD_GPU>; > clocks = <&cru ACLK_GPU>; > pm_qos = <&qos_gpu_r>, > -- > 2.17.1 > > > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v5 04/11] arm64: dts: rockchip: Fix power-controller node names for px30 2021-03-26 9:15 ` Elaine Zhang (?) @ 2021-03-26 9:15 ` Elaine Zhang -1 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:15 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Use more generic names (as recommended in the device tree specification or the binding documentation) Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- arch/arm64/boot/dts/rockchip/px30.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index c45b0cfcae09..fb3a863e0caf 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -247,20 +247,20 @@ #size-cells = <0>; /* These power domains are grouped by VD_LOGIC */ - pd_usb@PX30_PD_USB { + power-domain@PX30_PD_USB { reg = <PX30_PD_USB>; clocks = <&cru HCLK_HOST>, <&cru HCLK_OTG>, <&cru SCLK_OTG_ADP>; pm_qos = <&qos_usb_host>, <&qos_usb_otg>; }; - pd_sdcard@PX30_PD_SDCARD { + power-domain@PX30_PD_SDCARD { reg = <PX30_PD_SDCARD>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; pm_qos = <&qos_sdmmc>; }; - pd_gmac@PX30_PD_GMAC { + power-domain@PX30_PD_GMAC { reg = <PX30_PD_GMAC>; clocks = <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, @@ -268,7 +268,7 @@ <&cru SCLK_GMAC_RX_TX>; pm_qos = <&qos_gmac>; }; - pd_mmc_nand@PX30_PD_MMC_NAND { + power-domain@PX30_PD_MMC_NAND { reg = <PX30_PD_MMC_NAND>; clocks = <&cru HCLK_NANDC>, <&cru HCLK_EMMC>, @@ -281,14 +281,14 @@ pm_qos = <&qos_emmc>, <&qos_nand>, <&qos_sdio>, <&qos_sfc>; }; - pd_vpu@PX30_PD_VPU { + power-domain@PX30_PD_VPU { reg = <PX30_PD_VPU>; clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>, <&cru SCLK_CORE_VPU>; pm_qos = <&qos_vpu>, <&qos_vpu_r128>; }; - pd_vo@PX30_PD_VO { + power-domain@PX30_PD_VO { reg = <PX30_PD_VO>; clocks = <&cru ACLK_RGA>, <&cru ACLK_VOPB>, @@ -304,7 +304,7 @@ pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, <&qos_vop_m0>, <&qos_vop_m1>; }; - pd_vi@PX30_PD_VI { + power-domain@PX30_PD_VI { reg = <PX30_PD_VI>; clocks = <&cru ACLK_CIF>, <&cru ACLK_ISP>, @@ -315,7 +315,7 @@ <&qos_isp_wr>, <&qos_isp_m1>, <&qos_vip>; }; - pd_gpu@PX30_PD_GPU { + power-domain@PX30_PD_GPU { reg = <PX30_PD_GPU>; clocks = <&cru SCLK_GPU>; pm_qos = <&qos_gpu>; -- 2.17.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v5 04/11] arm64: dts: rockchip: Fix power-controller node names for px30 @ 2021-03-26 9:15 ` Elaine Zhang 0 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:15 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Use more generic names (as recommended in the device tree specification or the binding documentation) Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- arch/arm64/boot/dts/rockchip/px30.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index c45b0cfcae09..fb3a863e0caf 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -247,20 +247,20 @@ #size-cells = <0>; /* These power domains are grouped by VD_LOGIC */ - pd_usb@PX30_PD_USB { + power-domain@PX30_PD_USB { reg = <PX30_PD_USB>; clocks = <&cru HCLK_HOST>, <&cru HCLK_OTG>, <&cru SCLK_OTG_ADP>; pm_qos = <&qos_usb_host>, <&qos_usb_otg>; }; - pd_sdcard@PX30_PD_SDCARD { + power-domain@PX30_PD_SDCARD { reg = <PX30_PD_SDCARD>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; pm_qos = <&qos_sdmmc>; }; - pd_gmac@PX30_PD_GMAC { + power-domain@PX30_PD_GMAC { reg = <PX30_PD_GMAC>; clocks = <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, @@ -268,7 +268,7 @@ <&cru SCLK_GMAC_RX_TX>; pm_qos = <&qos_gmac>; }; - pd_mmc_nand@PX30_PD_MMC_NAND { + power-domain@PX30_PD_MMC_NAND { reg = <PX30_PD_MMC_NAND>; clocks = <&cru HCLK_NANDC>, <&cru HCLK_EMMC>, @@ -281,14 +281,14 @@ pm_qos = <&qos_emmc>, <&qos_nand>, <&qos_sdio>, <&qos_sfc>; }; - pd_vpu@PX30_PD_VPU { + power-domain@PX30_PD_VPU { reg = <PX30_PD_VPU>; clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>, <&cru SCLK_CORE_VPU>; pm_qos = <&qos_vpu>, <&qos_vpu_r128>; }; - pd_vo@PX30_PD_VO { + power-domain@PX30_PD_VO { reg = <PX30_PD_VO>; clocks = <&cru ACLK_RGA>, <&cru ACLK_VOPB>, @@ -304,7 +304,7 @@ pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, <&qos_vop_m0>, <&qos_vop_m1>; }; - pd_vi@PX30_PD_VI { + power-domain@PX30_PD_VI { reg = <PX30_PD_VI>; clocks = <&cru ACLK_CIF>, <&cru ACLK_ISP>, @@ -315,7 +315,7 @@ <&qos_isp_wr>, <&qos_isp_m1>, <&qos_vip>; }; - pd_gpu@PX30_PD_GPU { + power-domain@PX30_PD_GPU { reg = <PX30_PD_GPU>; clocks = <&cru SCLK_GPU>; pm_qos = <&qos_gpu>; -- 2.17.1 ^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v5 04/11] arm64: dts: rockchip: Fix power-controller node names for px30 @ 2021-03-26 9:15 ` Elaine Zhang 0 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:15 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Use more generic names (as recommended in the device tree specification or the binding documentation) Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- arch/arm64/boot/dts/rockchip/px30.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index c45b0cfcae09..fb3a863e0caf 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -247,20 +247,20 @@ #size-cells = <0>; /* These power domains are grouped by VD_LOGIC */ - pd_usb@PX30_PD_USB { + power-domain@PX30_PD_USB { reg = <PX30_PD_USB>; clocks = <&cru HCLK_HOST>, <&cru HCLK_OTG>, <&cru SCLK_OTG_ADP>; pm_qos = <&qos_usb_host>, <&qos_usb_otg>; }; - pd_sdcard@PX30_PD_SDCARD { + power-domain@PX30_PD_SDCARD { reg = <PX30_PD_SDCARD>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; pm_qos = <&qos_sdmmc>; }; - pd_gmac@PX30_PD_GMAC { + power-domain@PX30_PD_GMAC { reg = <PX30_PD_GMAC>; clocks = <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, @@ -268,7 +268,7 @@ <&cru SCLK_GMAC_RX_TX>; pm_qos = <&qos_gmac>; }; - pd_mmc_nand@PX30_PD_MMC_NAND { + power-domain@PX30_PD_MMC_NAND { reg = <PX30_PD_MMC_NAND>; clocks = <&cru HCLK_NANDC>, <&cru HCLK_EMMC>, @@ -281,14 +281,14 @@ pm_qos = <&qos_emmc>, <&qos_nand>, <&qos_sdio>, <&qos_sfc>; }; - pd_vpu@PX30_PD_VPU { + power-domain@PX30_PD_VPU { reg = <PX30_PD_VPU>; clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>, <&cru SCLK_CORE_VPU>; pm_qos = <&qos_vpu>, <&qos_vpu_r128>; }; - pd_vo@PX30_PD_VO { + power-domain@PX30_PD_VO { reg = <PX30_PD_VO>; clocks = <&cru ACLK_RGA>, <&cru ACLK_VOPB>, @@ -304,7 +304,7 @@ pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, <&qos_vop_m0>, <&qos_vop_m1>; }; - pd_vi@PX30_PD_VI { + power-domain@PX30_PD_VI { reg = <PX30_PD_VI>; clocks = <&cru ACLK_CIF>, <&cru ACLK_ISP>, @@ -315,7 +315,7 @@ <&qos_isp_wr>, <&qos_isp_m1>, <&qos_vip>; }; - pd_gpu@PX30_PD_GPU { + power-domain@PX30_PD_GPU { reg = <PX30_PD_GPU>; clocks = <&cru SCLK_GPU>; pm_qos = <&qos_gpu>; -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 75+ messages in thread
* Re: [PATCH v5 04/11] arm64: dts: rockchip: Fix power-controller node names for px30 2021-03-26 9:15 ` Elaine Zhang (?) @ 2021-03-26 9:41 ` Enric Balletbo Serra -1 siblings, 0 replies; 75+ messages in thread From: Enric Balletbo Serra @ 2021-03-26 9:41 UTC (permalink / raw) To: Elaine Zhang Cc: Rob Herring, Heiko Stübner, devicetree@vger.kernel.org, Linux ARM, open list:ARM/Rockchip SoC..., linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao Missatge de Elaine Zhang <zhangqing@rock-chips.com> del dia dv., 26 de març 2021 a les 10:17: > > Use more generic names (as recommended in the device tree specification > or the binding documentation) > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > --- > arch/arm64/boot/dts/rockchip/px30.dtsi | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi > index c45b0cfcae09..fb3a863e0caf 100644 > --- a/arch/arm64/boot/dts/rockchip/px30.dtsi > +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi > @@ -247,20 +247,20 @@ > #size-cells = <0>; > > /* These power domains are grouped by VD_LOGIC */ > - pd_usb@PX30_PD_USB { > + power-domain@PX30_PD_USB { > reg = <PX30_PD_USB>; > clocks = <&cru HCLK_HOST>, > <&cru HCLK_OTG>, > <&cru SCLK_OTG_ADP>; > pm_qos = <&qos_usb_host>, <&qos_usb_otg>; > }; > - pd_sdcard@PX30_PD_SDCARD { > + power-domain@PX30_PD_SDCARD { > reg = <PX30_PD_SDCARD>; > clocks = <&cru HCLK_SDMMC>, > <&cru SCLK_SDMMC>; > pm_qos = <&qos_sdmmc>; > }; > - pd_gmac@PX30_PD_GMAC { > + power-domain@PX30_PD_GMAC { > reg = <PX30_PD_GMAC>; > clocks = <&cru ACLK_GMAC>, > <&cru PCLK_GMAC>, > @@ -268,7 +268,7 @@ > <&cru SCLK_GMAC_RX_TX>; > pm_qos = <&qos_gmac>; > }; > - pd_mmc_nand@PX30_PD_MMC_NAND { > + power-domain@PX30_PD_MMC_NAND { > reg = <PX30_PD_MMC_NAND>; > clocks = <&cru HCLK_NANDC>, > <&cru HCLK_EMMC>, > @@ -281,14 +281,14 @@ > pm_qos = <&qos_emmc>, <&qos_nand>, > <&qos_sdio>, <&qos_sfc>; > }; > - pd_vpu@PX30_PD_VPU { > + power-domain@PX30_PD_VPU { > reg = <PX30_PD_VPU>; > clocks = <&cru ACLK_VPU>, > <&cru HCLK_VPU>, > <&cru SCLK_CORE_VPU>; > pm_qos = <&qos_vpu>, <&qos_vpu_r128>; > }; > - pd_vo@PX30_PD_VO { > + power-domain@PX30_PD_VO { > reg = <PX30_PD_VO>; > clocks = <&cru ACLK_RGA>, > <&cru ACLK_VOPB>, > @@ -304,7 +304,7 @@ > pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, > <&qos_vop_m0>, <&qos_vop_m1>; > }; > - pd_vi@PX30_PD_VI { > + power-domain@PX30_PD_VI { > reg = <PX30_PD_VI>; > clocks = <&cru ACLK_CIF>, > <&cru ACLK_ISP>, > @@ -315,7 +315,7 @@ > <&qos_isp_wr>, <&qos_isp_m1>, > <&qos_vip>; > }; > - pd_gpu@PX30_PD_GPU { > + power-domain@PX30_PD_GPU { > reg = <PX30_PD_GPU>; > clocks = <&cru SCLK_GPU>; > pm_qos = <&qos_gpu>; > -- > 2.17.1 > > > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v5 04/11] arm64: dts: rockchip: Fix power-controller node names for px30 @ 2021-03-26 9:41 ` Enric Balletbo Serra 0 siblings, 0 replies; 75+ messages in thread From: Enric Balletbo Serra @ 2021-03-26 9:41 UTC (permalink / raw) To: Elaine Zhang Cc: Rob Herring, Heiko Stübner, devicetree@vger.kernel.org, Linux ARM, open list:ARM/Rockchip SoC..., linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao Missatge de Elaine Zhang <zhangqing@rock-chips.com> del dia dv., 26 de març 2021 a les 10:17: > > Use more generic names (as recommended in the device tree specification > or the binding documentation) > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > --- > arch/arm64/boot/dts/rockchip/px30.dtsi | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi > index c45b0cfcae09..fb3a863e0caf 100644 > --- a/arch/arm64/boot/dts/rockchip/px30.dtsi > +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi > @@ -247,20 +247,20 @@ > #size-cells = <0>; > > /* These power domains are grouped by VD_LOGIC */ > - pd_usb@PX30_PD_USB { > + power-domain@PX30_PD_USB { > reg = <PX30_PD_USB>; > clocks = <&cru HCLK_HOST>, > <&cru HCLK_OTG>, > <&cru SCLK_OTG_ADP>; > pm_qos = <&qos_usb_host>, <&qos_usb_otg>; > }; > - pd_sdcard@PX30_PD_SDCARD { > + power-domain@PX30_PD_SDCARD { > reg = <PX30_PD_SDCARD>; > clocks = <&cru HCLK_SDMMC>, > <&cru SCLK_SDMMC>; > pm_qos = <&qos_sdmmc>; > }; > - pd_gmac@PX30_PD_GMAC { > + power-domain@PX30_PD_GMAC { > reg = <PX30_PD_GMAC>; > clocks = <&cru ACLK_GMAC>, > <&cru PCLK_GMAC>, > @@ -268,7 +268,7 @@ > <&cru SCLK_GMAC_RX_TX>; > pm_qos = <&qos_gmac>; > }; > - pd_mmc_nand@PX30_PD_MMC_NAND { > + power-domain@PX30_PD_MMC_NAND { > reg = <PX30_PD_MMC_NAND>; > clocks = <&cru HCLK_NANDC>, > <&cru HCLK_EMMC>, > @@ -281,14 +281,14 @@ > pm_qos = <&qos_emmc>, <&qos_nand>, > <&qos_sdio>, <&qos_sfc>; > }; > - pd_vpu@PX30_PD_VPU { > + power-domain@PX30_PD_VPU { > reg = <PX30_PD_VPU>; > clocks = <&cru ACLK_VPU>, > <&cru HCLK_VPU>, > <&cru SCLK_CORE_VPU>; > pm_qos = <&qos_vpu>, <&qos_vpu_r128>; > }; > - pd_vo@PX30_PD_VO { > + power-domain@PX30_PD_VO { > reg = <PX30_PD_VO>; > clocks = <&cru ACLK_RGA>, > <&cru ACLK_VOPB>, > @@ -304,7 +304,7 @@ > pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, > <&qos_vop_m0>, <&qos_vop_m1>; > }; > - pd_vi@PX30_PD_VI { > + power-domain@PX30_PD_VI { > reg = <PX30_PD_VI>; > clocks = <&cru ACLK_CIF>, > <&cru ACLK_ISP>, > @@ -315,7 +315,7 @@ > <&qos_isp_wr>, <&qos_isp_m1>, > <&qos_vip>; > }; > - pd_gpu@PX30_PD_GPU { > + power-domain@PX30_PD_GPU { > reg = <PX30_PD_GPU>; > clocks = <&cru SCLK_GPU>; > pm_qos = <&qos_gpu>; > -- > 2.17.1 > > > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v5 04/11] arm64: dts: rockchip: Fix power-controller node names for px30 @ 2021-03-26 9:41 ` Enric Balletbo Serra 0 siblings, 0 replies; 75+ messages in thread From: Enric Balletbo Serra @ 2021-03-26 9:41 UTC (permalink / raw) To: Elaine Zhang Cc: Rob Herring, Heiko Stübner, devicetree@vger.kernel.org, Linux ARM, open list:ARM/Rockchip SoC..., linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao Missatge de Elaine Zhang <zhangqing@rock-chips.com> del dia dv., 26 de març 2021 a les 10:17: > > Use more generic names (as recommended in the device tree specification > or the binding documentation) > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > --- > arch/arm64/boot/dts/rockchip/px30.dtsi | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi > index c45b0cfcae09..fb3a863e0caf 100644 > --- a/arch/arm64/boot/dts/rockchip/px30.dtsi > +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi > @@ -247,20 +247,20 @@ > #size-cells = <0>; > > /* These power domains are grouped by VD_LOGIC */ > - pd_usb@PX30_PD_USB { > + power-domain@PX30_PD_USB { > reg = <PX30_PD_USB>; > clocks = <&cru HCLK_HOST>, > <&cru HCLK_OTG>, > <&cru SCLK_OTG_ADP>; > pm_qos = <&qos_usb_host>, <&qos_usb_otg>; > }; > - pd_sdcard@PX30_PD_SDCARD { > + power-domain@PX30_PD_SDCARD { > reg = <PX30_PD_SDCARD>; > clocks = <&cru HCLK_SDMMC>, > <&cru SCLK_SDMMC>; > pm_qos = <&qos_sdmmc>; > }; > - pd_gmac@PX30_PD_GMAC { > + power-domain@PX30_PD_GMAC { > reg = <PX30_PD_GMAC>; > clocks = <&cru ACLK_GMAC>, > <&cru PCLK_GMAC>, > @@ -268,7 +268,7 @@ > <&cru SCLK_GMAC_RX_TX>; > pm_qos = <&qos_gmac>; > }; > - pd_mmc_nand@PX30_PD_MMC_NAND { > + power-domain@PX30_PD_MMC_NAND { > reg = <PX30_PD_MMC_NAND>; > clocks = <&cru HCLK_NANDC>, > <&cru HCLK_EMMC>, > @@ -281,14 +281,14 @@ > pm_qos = <&qos_emmc>, <&qos_nand>, > <&qos_sdio>, <&qos_sfc>; > }; > - pd_vpu@PX30_PD_VPU { > + power-domain@PX30_PD_VPU { > reg = <PX30_PD_VPU>; > clocks = <&cru ACLK_VPU>, > <&cru HCLK_VPU>, > <&cru SCLK_CORE_VPU>; > pm_qos = <&qos_vpu>, <&qos_vpu_r128>; > }; > - pd_vo@PX30_PD_VO { > + power-domain@PX30_PD_VO { > reg = <PX30_PD_VO>; > clocks = <&cru ACLK_RGA>, > <&cru ACLK_VOPB>, > @@ -304,7 +304,7 @@ > pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, > <&qos_vop_m0>, <&qos_vop_m1>; > }; > - pd_vi@PX30_PD_VI { > + power-domain@PX30_PD_VI { > reg = <PX30_PD_VI>; > clocks = <&cru ACLK_CIF>, > <&cru ACLK_ISP>, > @@ -315,7 +315,7 @@ > <&qos_isp_wr>, <&qos_isp_m1>, > <&qos_vip>; > }; > - pd_gpu@PX30_PD_GPU { > + power-domain@PX30_PD_GPU { > reg = <PX30_PD_GPU>; > clocks = <&cru SCLK_GPU>; > pm_qos = <&qos_gpu>; > -- > 2.17.1 > > > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v5 05/11] arm64: dts: rockchip: Fix power-controller node names for rk3328 2021-03-26 9:15 ` Elaine Zhang (?) @ 2021-03-26 9:17 ` Elaine Zhang -1 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:17 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Use more generic names (as recommended in the device tree specification or the binding documentation) Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index 063ed0adbec4..084acfd597af 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -303,13 +303,13 @@ #address-cells = <1>; #size-cells = <0>; - pd_hevc@RK3328_PD_HEVC { + power-domain@RK3328_PD_HEVC { reg = <RK3328_PD_HEVC>; }; - pd_video@RK3328_PD_VIDEO { + power-domain@RK3328_PD_VIDEO { reg = <RK3328_PD_VIDEO>; }; - pd_vpu@RK3328_PD_VPU { + power-domain@RK3328_PD_VPU { reg = <RK3328_PD_VPU>; clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; }; -- 2.17.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v5 05/11] arm64: dts: rockchip: Fix power-controller node names for rk3328 @ 2021-03-26 9:17 ` Elaine Zhang 0 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:17 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Use more generic names (as recommended in the device tree specification or the binding documentation) Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index 063ed0adbec4..084acfd597af 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -303,13 +303,13 @@ #address-cells = <1>; #size-cells = <0>; - pd_hevc@RK3328_PD_HEVC { + power-domain@RK3328_PD_HEVC { reg = <RK3328_PD_HEVC>; }; - pd_video@RK3328_PD_VIDEO { + power-domain@RK3328_PD_VIDEO { reg = <RK3328_PD_VIDEO>; }; - pd_vpu@RK3328_PD_VPU { + power-domain@RK3328_PD_VPU { reg = <RK3328_PD_VPU>; clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; }; -- 2.17.1 ^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v5 05/11] arm64: dts: rockchip: Fix power-controller node names for rk3328 @ 2021-03-26 9:17 ` Elaine Zhang 0 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:17 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Use more generic names (as recommended in the device tree specification or the binding documentation) Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index 063ed0adbec4..084acfd597af 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -303,13 +303,13 @@ #address-cells = <1>; #size-cells = <0>; - pd_hevc@RK3328_PD_HEVC { + power-domain@RK3328_PD_HEVC { reg = <RK3328_PD_HEVC>; }; - pd_video@RK3328_PD_VIDEO { + power-domain@RK3328_PD_VIDEO { reg = <RK3328_PD_VIDEO>; }; - pd_vpu@RK3328_PD_VPU { + power-domain@RK3328_PD_VPU { reg = <RK3328_PD_VPU>; clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; }; -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 75+ messages in thread
* Re: [PATCH v5 05/11] arm64: dts: rockchip: Fix power-controller node names for rk3328 2021-03-26 9:17 ` Elaine Zhang (?) @ 2021-03-26 9:41 ` Enric Balletbo Serra -1 siblings, 0 replies; 75+ messages in thread From: Enric Balletbo Serra @ 2021-03-26 9:41 UTC (permalink / raw) To: Elaine Zhang Cc: Rob Herring, Heiko Stübner, devicetree@vger.kernel.org, Linux ARM, open list:ARM/Rockchip SoC..., linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao Missatge de Elaine Zhang <zhangqing@rock-chips.com> del dia dv., 26 de març 2021 a les 10:17: > > Use more generic names (as recommended in the device tree specification > or the binding documentation) > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > --- > arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi > index 063ed0adbec4..084acfd597af 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi > @@ -303,13 +303,13 @@ > #address-cells = <1>; > #size-cells = <0>; > > - pd_hevc@RK3328_PD_HEVC { > + power-domain@RK3328_PD_HEVC { > reg = <RK3328_PD_HEVC>; > }; > - pd_video@RK3328_PD_VIDEO { > + power-domain@RK3328_PD_VIDEO { > reg = <RK3328_PD_VIDEO>; > }; > - pd_vpu@RK3328_PD_VPU { > + power-domain@RK3328_PD_VPU { > reg = <RK3328_PD_VPU>; > clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; > }; > -- > 2.17.1 > > > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v5 05/11] arm64: dts: rockchip: Fix power-controller node names for rk3328 @ 2021-03-26 9:41 ` Enric Balletbo Serra 0 siblings, 0 replies; 75+ messages in thread From: Enric Balletbo Serra @ 2021-03-26 9:41 UTC (permalink / raw) To: Elaine Zhang Cc: Rob Herring, Heiko Stübner, devicetree@vger.kernel.org, Linux ARM, open list:ARM/Rockchip SoC..., linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao Missatge de Elaine Zhang <zhangqing@rock-chips.com> del dia dv., 26 de març 2021 a les 10:17: > > Use more generic names (as recommended in the device tree specification > or the binding documentation) > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > --- > arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi > index 063ed0adbec4..084acfd597af 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi > @@ -303,13 +303,13 @@ > #address-cells = <1>; > #size-cells = <0>; > > - pd_hevc@RK3328_PD_HEVC { > + power-domain@RK3328_PD_HEVC { > reg = <RK3328_PD_HEVC>; > }; > - pd_video@RK3328_PD_VIDEO { > + power-domain@RK3328_PD_VIDEO { > reg = <RK3328_PD_VIDEO>; > }; > - pd_vpu@RK3328_PD_VPU { > + power-domain@RK3328_PD_VPU { > reg = <RK3328_PD_VPU>; > clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; > }; > -- > 2.17.1 > > > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v5 05/11] arm64: dts: rockchip: Fix power-controller node names for rk3328 @ 2021-03-26 9:41 ` Enric Balletbo Serra 0 siblings, 0 replies; 75+ messages in thread From: Enric Balletbo Serra @ 2021-03-26 9:41 UTC (permalink / raw) To: Elaine Zhang Cc: Rob Herring, Heiko Stübner, devicetree@vger.kernel.org, Linux ARM, open list:ARM/Rockchip SoC..., linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao Missatge de Elaine Zhang <zhangqing@rock-chips.com> del dia dv., 26 de març 2021 a les 10:17: > > Use more generic names (as recommended in the device tree specification > or the binding documentation) > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > --- > arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi > index 063ed0adbec4..084acfd597af 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi > @@ -303,13 +303,13 @@ > #address-cells = <1>; > #size-cells = <0>; > > - pd_hevc@RK3328_PD_HEVC { > + power-domain@RK3328_PD_HEVC { > reg = <RK3328_PD_HEVC>; > }; > - pd_video@RK3328_PD_VIDEO { > + power-domain@RK3328_PD_VIDEO { > reg = <RK3328_PD_VIDEO>; > }; > - pd_vpu@RK3328_PD_VPU { > + power-domain@RK3328_PD_VPU { > reg = <RK3328_PD_VPU>; > clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; > }; > -- > 2.17.1 > > > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v5 06/11] arm64: dts: rockchip: Fix power-controller node names for rk3399 2021-03-26 9:15 ` Elaine Zhang (?) @ 2021-03-26 9:17 ` Elaine Zhang -1 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:17 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Use more generic names (as recommended in the device tree specification or the binding documentation) Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 40 ++++++++++++------------ 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index edbbf35fe19e..142f5593d48b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -971,26 +971,26 @@ #size-cells = <0>; /* These power domains are grouped by VD_CENTER */ - pd_iep@RK3399_PD_IEP { + power-domain@RK3399_PD_IEP { reg = <RK3399_PD_IEP>; clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; pm_qos = <&qos_iep>; }; - pd_rga@RK3399_PD_RGA { + power-domain@RK3399_PD_RGA { reg = <RK3399_PD_RGA>; clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>; pm_qos = <&qos_rga_r>, <&qos_rga_w>; }; - pd_vcodec@RK3399_PD_VCODEC { + power-domain@RK3399_PD_VCODEC { reg = <RK3399_PD_VCODEC>; clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; pm_qos = <&qos_video_m0>; }; - pd_vdu@RK3399_PD_VDU { + power-domain@RK3399_PD_VDU { reg = <RK3399_PD_VDU>; clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; @@ -999,94 +999,94 @@ }; /* These power domains are grouped by VD_GPU */ - pd_gpu@RK3399_PD_GPU { + power-domain@RK3399_PD_GPU { reg = <RK3399_PD_GPU>; clocks = <&cru ACLK_GPU>; pm_qos = <&qos_gpu>; }; /* These power domains are grouped by VD_LOGIC */ - pd_edp@RK3399_PD_EDP { + power-domain@RK3399_PD_EDP { reg = <RK3399_PD_EDP>; clocks = <&cru PCLK_EDP_CTRL>; }; - pd_emmc@RK3399_PD_EMMC { + power-domain@RK3399_PD_EMMC { reg = <RK3399_PD_EMMC>; clocks = <&cru ACLK_EMMC>; pm_qos = <&qos_emmc>; }; - pd_gmac@RK3399_PD_GMAC { + power-domain@RK3399_PD_GMAC { reg = <RK3399_PD_GMAC>; clocks = <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; pm_qos = <&qos_gmac>; }; - pd_sd@RK3399_PD_SD { + power-domain@RK3399_PD_SD { reg = <RK3399_PD_SD>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; pm_qos = <&qos_sd>; }; - pd_sdioaudio@RK3399_PD_SDIOAUDIO { + power-domain@RK3399_PD_SDIOAUDIO { reg = <RK3399_PD_SDIOAUDIO>; clocks = <&cru HCLK_SDIO>; pm_qos = <&qos_sdioaudio>; }; - pd_tcpc0@RK3399_PD_TCPD0 { + power-domain@RK3399_PD_TCPD0 { reg = <RK3399_PD_TCPD0>; clocks = <&cru SCLK_UPHY0_TCPDCORE>, <&cru SCLK_UPHY0_TCPDPHY_REF>; }; - pd_tcpc1@RK3399_PD_TCPD1 { + power-domain@RK3399_PD_TCPD1 { reg = <RK3399_PD_TCPD1>; clocks = <&cru SCLK_UPHY1_TCPDCORE>, <&cru SCLK_UPHY1_TCPDPHY_REF>; }; - pd_usb3@RK3399_PD_USB3 { + power-domain@RK3399_PD_USB3 { reg = <RK3399_PD_USB3>; clocks = <&cru ACLK_USB3>; pm_qos = <&qos_usb_otg0>, <&qos_usb_otg1>; }; - pd_vio@RK3399_PD_VIO { + power-domain@RK3399_PD_VIO { reg = <RK3399_PD_VIO>; #address-cells = <1>; #size-cells = <0>; - pd_hdcp@RK3399_PD_HDCP { + power-domain@RK3399_PD_HDCP { reg = <RK3399_PD_HDCP>; clocks = <&cru ACLK_HDCP>, <&cru HCLK_HDCP>, <&cru PCLK_HDCP>; pm_qos = <&qos_hdcp>; }; - pd_isp0@RK3399_PD_ISP0 { + power-domain@RK3399_PD_ISP0 { reg = <RK3399_PD_ISP0>; clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>; pm_qos = <&qos_isp0_m0>, <&qos_isp0_m1>; }; - pd_isp1@RK3399_PD_ISP1 { + power-domain@RK3399_PD_ISP1 { reg = <RK3399_PD_ISP1>; clocks = <&cru ACLK_ISP1>, <&cru HCLK_ISP1>; pm_qos = <&qos_isp1_m0>, <&qos_isp1_m1>; }; - pd_vo@RK3399_PD_VO { + power-domain@RK3399_PD_VO { reg = <RK3399_PD_VO>; #address-cells = <1>; #size-cells = <0>; - pd_vopb@RK3399_PD_VOPB { + power-domain@RK3399_PD_VOPB { reg = <RK3399_PD_VOPB>; clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; pm_qos = <&qos_vop_big_r>, <&qos_vop_big_w>; }; - pd_vopl@RK3399_PD_VOPL { + power-domain@RK3399_PD_VOPL { reg = <RK3399_PD_VOPL>; clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; -- 2.17.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v5 06/11] arm64: dts: rockchip: Fix power-controller node names for rk3399 @ 2021-03-26 9:17 ` Elaine Zhang 0 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:17 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Use more generic names (as recommended in the device tree specification or the binding documentation) Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 40 ++++++++++++------------ 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index edbbf35fe19e..142f5593d48b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -971,26 +971,26 @@ #size-cells = <0>; /* These power domains are grouped by VD_CENTER */ - pd_iep@RK3399_PD_IEP { + power-domain@RK3399_PD_IEP { reg = <RK3399_PD_IEP>; clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; pm_qos = <&qos_iep>; }; - pd_rga@RK3399_PD_RGA { + power-domain@RK3399_PD_RGA { reg = <RK3399_PD_RGA>; clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>; pm_qos = <&qos_rga_r>, <&qos_rga_w>; }; - pd_vcodec@RK3399_PD_VCODEC { + power-domain@RK3399_PD_VCODEC { reg = <RK3399_PD_VCODEC>; clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; pm_qos = <&qos_video_m0>; }; - pd_vdu@RK3399_PD_VDU { + power-domain@RK3399_PD_VDU { reg = <RK3399_PD_VDU>; clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; @@ -999,94 +999,94 @@ }; /* These power domains are grouped by VD_GPU */ - pd_gpu@RK3399_PD_GPU { + power-domain@RK3399_PD_GPU { reg = <RK3399_PD_GPU>; clocks = <&cru ACLK_GPU>; pm_qos = <&qos_gpu>; }; /* These power domains are grouped by VD_LOGIC */ - pd_edp@RK3399_PD_EDP { + power-domain@RK3399_PD_EDP { reg = <RK3399_PD_EDP>; clocks = <&cru PCLK_EDP_CTRL>; }; - pd_emmc@RK3399_PD_EMMC { + power-domain@RK3399_PD_EMMC { reg = <RK3399_PD_EMMC>; clocks = <&cru ACLK_EMMC>; pm_qos = <&qos_emmc>; }; - pd_gmac@RK3399_PD_GMAC { + power-domain@RK3399_PD_GMAC { reg = <RK3399_PD_GMAC>; clocks = <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; pm_qos = <&qos_gmac>; }; - pd_sd@RK3399_PD_SD { + power-domain@RK3399_PD_SD { reg = <RK3399_PD_SD>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; pm_qos = <&qos_sd>; }; - pd_sdioaudio@RK3399_PD_SDIOAUDIO { + power-domain@RK3399_PD_SDIOAUDIO { reg = <RK3399_PD_SDIOAUDIO>; clocks = <&cru HCLK_SDIO>; pm_qos = <&qos_sdioaudio>; }; - pd_tcpc0@RK3399_PD_TCPD0 { + power-domain@RK3399_PD_TCPD0 { reg = <RK3399_PD_TCPD0>; clocks = <&cru SCLK_UPHY0_TCPDCORE>, <&cru SCLK_UPHY0_TCPDPHY_REF>; }; - pd_tcpc1@RK3399_PD_TCPD1 { + power-domain@RK3399_PD_TCPD1 { reg = <RK3399_PD_TCPD1>; clocks = <&cru SCLK_UPHY1_TCPDCORE>, <&cru SCLK_UPHY1_TCPDPHY_REF>; }; - pd_usb3@RK3399_PD_USB3 { + power-domain@RK3399_PD_USB3 { reg = <RK3399_PD_USB3>; clocks = <&cru ACLK_USB3>; pm_qos = <&qos_usb_otg0>, <&qos_usb_otg1>; }; - pd_vio@RK3399_PD_VIO { + power-domain@RK3399_PD_VIO { reg = <RK3399_PD_VIO>; #address-cells = <1>; #size-cells = <0>; - pd_hdcp@RK3399_PD_HDCP { + power-domain@RK3399_PD_HDCP { reg = <RK3399_PD_HDCP>; clocks = <&cru ACLK_HDCP>, <&cru HCLK_HDCP>, <&cru PCLK_HDCP>; pm_qos = <&qos_hdcp>; }; - pd_isp0@RK3399_PD_ISP0 { + power-domain@RK3399_PD_ISP0 { reg = <RK3399_PD_ISP0>; clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>; pm_qos = <&qos_isp0_m0>, <&qos_isp0_m1>; }; - pd_isp1@RK3399_PD_ISP1 { + power-domain@RK3399_PD_ISP1 { reg = <RK3399_PD_ISP1>; clocks = <&cru ACLK_ISP1>, <&cru HCLK_ISP1>; pm_qos = <&qos_isp1_m0>, <&qos_isp1_m1>; }; - pd_vo@RK3399_PD_VO { + power-domain@RK3399_PD_VO { reg = <RK3399_PD_VO>; #address-cells = <1>; #size-cells = <0>; - pd_vopb@RK3399_PD_VOPB { + power-domain@RK3399_PD_VOPB { reg = <RK3399_PD_VOPB>; clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; pm_qos = <&qos_vop_big_r>, <&qos_vop_big_w>; }; - pd_vopl@RK3399_PD_VOPL { + power-domain@RK3399_PD_VOPL { reg = <RK3399_PD_VOPL>; clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; -- 2.17.1 ^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v5 06/11] arm64: dts: rockchip: Fix power-controller node names for rk3399 @ 2021-03-26 9:17 ` Elaine Zhang 0 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:17 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Use more generic names (as recommended in the device tree specification or the binding documentation) Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 40 ++++++++++++------------ 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index edbbf35fe19e..142f5593d48b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -971,26 +971,26 @@ #size-cells = <0>; /* These power domains are grouped by VD_CENTER */ - pd_iep@RK3399_PD_IEP { + power-domain@RK3399_PD_IEP { reg = <RK3399_PD_IEP>; clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; pm_qos = <&qos_iep>; }; - pd_rga@RK3399_PD_RGA { + power-domain@RK3399_PD_RGA { reg = <RK3399_PD_RGA>; clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>; pm_qos = <&qos_rga_r>, <&qos_rga_w>; }; - pd_vcodec@RK3399_PD_VCODEC { + power-domain@RK3399_PD_VCODEC { reg = <RK3399_PD_VCODEC>; clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; pm_qos = <&qos_video_m0>; }; - pd_vdu@RK3399_PD_VDU { + power-domain@RK3399_PD_VDU { reg = <RK3399_PD_VDU>; clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; @@ -999,94 +999,94 @@ }; /* These power domains are grouped by VD_GPU */ - pd_gpu@RK3399_PD_GPU { + power-domain@RK3399_PD_GPU { reg = <RK3399_PD_GPU>; clocks = <&cru ACLK_GPU>; pm_qos = <&qos_gpu>; }; /* These power domains are grouped by VD_LOGIC */ - pd_edp@RK3399_PD_EDP { + power-domain@RK3399_PD_EDP { reg = <RK3399_PD_EDP>; clocks = <&cru PCLK_EDP_CTRL>; }; - pd_emmc@RK3399_PD_EMMC { + power-domain@RK3399_PD_EMMC { reg = <RK3399_PD_EMMC>; clocks = <&cru ACLK_EMMC>; pm_qos = <&qos_emmc>; }; - pd_gmac@RK3399_PD_GMAC { + power-domain@RK3399_PD_GMAC { reg = <RK3399_PD_GMAC>; clocks = <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; pm_qos = <&qos_gmac>; }; - pd_sd@RK3399_PD_SD { + power-domain@RK3399_PD_SD { reg = <RK3399_PD_SD>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; pm_qos = <&qos_sd>; }; - pd_sdioaudio@RK3399_PD_SDIOAUDIO { + power-domain@RK3399_PD_SDIOAUDIO { reg = <RK3399_PD_SDIOAUDIO>; clocks = <&cru HCLK_SDIO>; pm_qos = <&qos_sdioaudio>; }; - pd_tcpc0@RK3399_PD_TCPD0 { + power-domain@RK3399_PD_TCPD0 { reg = <RK3399_PD_TCPD0>; clocks = <&cru SCLK_UPHY0_TCPDCORE>, <&cru SCLK_UPHY0_TCPDPHY_REF>; }; - pd_tcpc1@RK3399_PD_TCPD1 { + power-domain@RK3399_PD_TCPD1 { reg = <RK3399_PD_TCPD1>; clocks = <&cru SCLK_UPHY1_TCPDCORE>, <&cru SCLK_UPHY1_TCPDPHY_REF>; }; - pd_usb3@RK3399_PD_USB3 { + power-domain@RK3399_PD_USB3 { reg = <RK3399_PD_USB3>; clocks = <&cru ACLK_USB3>; pm_qos = <&qos_usb_otg0>, <&qos_usb_otg1>; }; - pd_vio@RK3399_PD_VIO { + power-domain@RK3399_PD_VIO { reg = <RK3399_PD_VIO>; #address-cells = <1>; #size-cells = <0>; - pd_hdcp@RK3399_PD_HDCP { + power-domain@RK3399_PD_HDCP { reg = <RK3399_PD_HDCP>; clocks = <&cru ACLK_HDCP>, <&cru HCLK_HDCP>, <&cru PCLK_HDCP>; pm_qos = <&qos_hdcp>; }; - pd_isp0@RK3399_PD_ISP0 { + power-domain@RK3399_PD_ISP0 { reg = <RK3399_PD_ISP0>; clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>; pm_qos = <&qos_isp0_m0>, <&qos_isp0_m1>; }; - pd_isp1@RK3399_PD_ISP1 { + power-domain@RK3399_PD_ISP1 { reg = <RK3399_PD_ISP1>; clocks = <&cru ACLK_ISP1>, <&cru HCLK_ISP1>; pm_qos = <&qos_isp1_m0>, <&qos_isp1_m1>; }; - pd_vo@RK3399_PD_VO { + power-domain@RK3399_PD_VO { reg = <RK3399_PD_VO>; #address-cells = <1>; #size-cells = <0>; - pd_vopb@RK3399_PD_VOPB { + power-domain@RK3399_PD_VOPB { reg = <RK3399_PD_VOPB>; clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; pm_qos = <&qos_vop_big_r>, <&qos_vop_big_w>; }; - pd_vopl@RK3399_PD_VOPL { + power-domain@RK3399_PD_VOPL { reg = <RK3399_PD_VOPL>; clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 75+ messages in thread
* Re: [PATCH v5 06/11] arm64: dts: rockchip: Fix power-controller node names for rk3399 2021-03-26 9:17 ` Elaine Zhang (?) @ 2021-03-26 9:42 ` Enric Balletbo Serra -1 siblings, 0 replies; 75+ messages in thread From: Enric Balletbo Serra @ 2021-03-26 9:42 UTC (permalink / raw) To: Elaine Zhang Cc: Rob Herring, Heiko Stübner, devicetree@vger.kernel.org, Linux ARM, open list:ARM/Rockchip SoC..., linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao Missatge de Elaine Zhang <zhangqing@rock-chips.com> del dia dv., 26 de març 2021 a les 10:18: > > Use more generic names (as recommended in the device tree specification > or the binding documentation) > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > --- > arch/arm64/boot/dts/rockchip/rk3399.dtsi | 40 ++++++++++++------------ > 1 file changed, 20 insertions(+), 20 deletions(-) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi > index edbbf35fe19e..142f5593d48b 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi > @@ -971,26 +971,26 @@ > #size-cells = <0>; > > /* These power domains are grouped by VD_CENTER */ > - pd_iep@RK3399_PD_IEP { > + power-domain@RK3399_PD_IEP { > reg = <RK3399_PD_IEP>; > clocks = <&cru ACLK_IEP>, > <&cru HCLK_IEP>; > pm_qos = <&qos_iep>; > }; > - pd_rga@RK3399_PD_RGA { > + power-domain@RK3399_PD_RGA { > reg = <RK3399_PD_RGA>; > clocks = <&cru ACLK_RGA>, > <&cru HCLK_RGA>; > pm_qos = <&qos_rga_r>, > <&qos_rga_w>; > }; > - pd_vcodec@RK3399_PD_VCODEC { > + power-domain@RK3399_PD_VCODEC { > reg = <RK3399_PD_VCODEC>; > clocks = <&cru ACLK_VCODEC>, > <&cru HCLK_VCODEC>; > pm_qos = <&qos_video_m0>; > }; > - pd_vdu@RK3399_PD_VDU { > + power-domain@RK3399_PD_VDU { > reg = <RK3399_PD_VDU>; > clocks = <&cru ACLK_VDU>, > <&cru HCLK_VDU>; > @@ -999,94 +999,94 @@ > }; > > /* These power domains are grouped by VD_GPU */ > - pd_gpu@RK3399_PD_GPU { > + power-domain@RK3399_PD_GPU { > reg = <RK3399_PD_GPU>; > clocks = <&cru ACLK_GPU>; > pm_qos = <&qos_gpu>; > }; > > /* These power domains are grouped by VD_LOGIC */ > - pd_edp@RK3399_PD_EDP { > + power-domain@RK3399_PD_EDP { > reg = <RK3399_PD_EDP>; > clocks = <&cru PCLK_EDP_CTRL>; > }; > - pd_emmc@RK3399_PD_EMMC { > + power-domain@RK3399_PD_EMMC { > reg = <RK3399_PD_EMMC>; > clocks = <&cru ACLK_EMMC>; > pm_qos = <&qos_emmc>; > }; > - pd_gmac@RK3399_PD_GMAC { > + power-domain@RK3399_PD_GMAC { > reg = <RK3399_PD_GMAC>; > clocks = <&cru ACLK_GMAC>, > <&cru PCLK_GMAC>; > pm_qos = <&qos_gmac>; > }; > - pd_sd@RK3399_PD_SD { > + power-domain@RK3399_PD_SD { > reg = <RK3399_PD_SD>; > clocks = <&cru HCLK_SDMMC>, > <&cru SCLK_SDMMC>; > pm_qos = <&qos_sd>; > }; > - pd_sdioaudio@RK3399_PD_SDIOAUDIO { > + power-domain@RK3399_PD_SDIOAUDIO { > reg = <RK3399_PD_SDIOAUDIO>; > clocks = <&cru HCLK_SDIO>; > pm_qos = <&qos_sdioaudio>; > }; > - pd_tcpc0@RK3399_PD_TCPD0 { > + power-domain@RK3399_PD_TCPD0 { > reg = <RK3399_PD_TCPD0>; > clocks = <&cru SCLK_UPHY0_TCPDCORE>, > <&cru SCLK_UPHY0_TCPDPHY_REF>; > }; > - pd_tcpc1@RK3399_PD_TCPD1 { > + power-domain@RK3399_PD_TCPD1 { > reg = <RK3399_PD_TCPD1>; > clocks = <&cru SCLK_UPHY1_TCPDCORE>, > <&cru SCLK_UPHY1_TCPDPHY_REF>; > }; > - pd_usb3@RK3399_PD_USB3 { > + power-domain@RK3399_PD_USB3 { > reg = <RK3399_PD_USB3>; > clocks = <&cru ACLK_USB3>; > pm_qos = <&qos_usb_otg0>, > <&qos_usb_otg1>; > }; > - pd_vio@RK3399_PD_VIO { > + power-domain@RK3399_PD_VIO { > reg = <RK3399_PD_VIO>; > #address-cells = <1>; > #size-cells = <0>; > > - pd_hdcp@RK3399_PD_HDCP { > + power-domain@RK3399_PD_HDCP { > reg = <RK3399_PD_HDCP>; > clocks = <&cru ACLK_HDCP>, > <&cru HCLK_HDCP>, > <&cru PCLK_HDCP>; > pm_qos = <&qos_hdcp>; > }; > - pd_isp0@RK3399_PD_ISP0 { > + power-domain@RK3399_PD_ISP0 { > reg = <RK3399_PD_ISP0>; > clocks = <&cru ACLK_ISP0>, > <&cru HCLK_ISP0>; > pm_qos = <&qos_isp0_m0>, > <&qos_isp0_m1>; > }; > - pd_isp1@RK3399_PD_ISP1 { > + power-domain@RK3399_PD_ISP1 { > reg = <RK3399_PD_ISP1>; > clocks = <&cru ACLK_ISP1>, > <&cru HCLK_ISP1>; > pm_qos = <&qos_isp1_m0>, > <&qos_isp1_m1>; > }; > - pd_vo@RK3399_PD_VO { > + power-domain@RK3399_PD_VO { > reg = <RK3399_PD_VO>; > #address-cells = <1>; > #size-cells = <0>; > > - pd_vopb@RK3399_PD_VOPB { > + power-domain@RK3399_PD_VOPB { > reg = <RK3399_PD_VOPB>; > clocks = <&cru ACLK_VOP0>, > <&cru HCLK_VOP0>; > pm_qos = <&qos_vop_big_r>, > <&qos_vop_big_w>; > }; > - pd_vopl@RK3399_PD_VOPL { > + power-domain@RK3399_PD_VOPL { > reg = <RK3399_PD_VOPL>; > clocks = <&cru ACLK_VOP1>, > <&cru HCLK_VOP1>; > -- > 2.17.1 > > > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v5 06/11] arm64: dts: rockchip: Fix power-controller node names for rk3399 @ 2021-03-26 9:42 ` Enric Balletbo Serra 0 siblings, 0 replies; 75+ messages in thread From: Enric Balletbo Serra @ 2021-03-26 9:42 UTC (permalink / raw) To: Elaine Zhang Cc: Rob Herring, Heiko Stübner, devicetree@vger.kernel.org, Linux ARM, open list:ARM/Rockchip SoC..., linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao Missatge de Elaine Zhang <zhangqing@rock-chips.com> del dia dv., 26 de març 2021 a les 10:18: > > Use more generic names (as recommended in the device tree specification > or the binding documentation) > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > --- > arch/arm64/boot/dts/rockchip/rk3399.dtsi | 40 ++++++++++++------------ > 1 file changed, 20 insertions(+), 20 deletions(-) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi > index edbbf35fe19e..142f5593d48b 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi > @@ -971,26 +971,26 @@ > #size-cells = <0>; > > /* These power domains are grouped by VD_CENTER */ > - pd_iep@RK3399_PD_IEP { > + power-domain@RK3399_PD_IEP { > reg = <RK3399_PD_IEP>; > clocks = <&cru ACLK_IEP>, > <&cru HCLK_IEP>; > pm_qos = <&qos_iep>; > }; > - pd_rga@RK3399_PD_RGA { > + power-domain@RK3399_PD_RGA { > reg = <RK3399_PD_RGA>; > clocks = <&cru ACLK_RGA>, > <&cru HCLK_RGA>; > pm_qos = <&qos_rga_r>, > <&qos_rga_w>; > }; > - pd_vcodec@RK3399_PD_VCODEC { > + power-domain@RK3399_PD_VCODEC { > reg = <RK3399_PD_VCODEC>; > clocks = <&cru ACLK_VCODEC>, > <&cru HCLK_VCODEC>; > pm_qos = <&qos_video_m0>; > }; > - pd_vdu@RK3399_PD_VDU { > + power-domain@RK3399_PD_VDU { > reg = <RK3399_PD_VDU>; > clocks = <&cru ACLK_VDU>, > <&cru HCLK_VDU>; > @@ -999,94 +999,94 @@ > }; > > /* These power domains are grouped by VD_GPU */ > - pd_gpu@RK3399_PD_GPU { > + power-domain@RK3399_PD_GPU { > reg = <RK3399_PD_GPU>; > clocks = <&cru ACLK_GPU>; > pm_qos = <&qos_gpu>; > }; > > /* These power domains are grouped by VD_LOGIC */ > - pd_edp@RK3399_PD_EDP { > + power-domain@RK3399_PD_EDP { > reg = <RK3399_PD_EDP>; > clocks = <&cru PCLK_EDP_CTRL>; > }; > - pd_emmc@RK3399_PD_EMMC { > + power-domain@RK3399_PD_EMMC { > reg = <RK3399_PD_EMMC>; > clocks = <&cru ACLK_EMMC>; > pm_qos = <&qos_emmc>; > }; > - pd_gmac@RK3399_PD_GMAC { > + power-domain@RK3399_PD_GMAC { > reg = <RK3399_PD_GMAC>; > clocks = <&cru ACLK_GMAC>, > <&cru PCLK_GMAC>; > pm_qos = <&qos_gmac>; > }; > - pd_sd@RK3399_PD_SD { > + power-domain@RK3399_PD_SD { > reg = <RK3399_PD_SD>; > clocks = <&cru HCLK_SDMMC>, > <&cru SCLK_SDMMC>; > pm_qos = <&qos_sd>; > }; > - pd_sdioaudio@RK3399_PD_SDIOAUDIO { > + power-domain@RK3399_PD_SDIOAUDIO { > reg = <RK3399_PD_SDIOAUDIO>; > clocks = <&cru HCLK_SDIO>; > pm_qos = <&qos_sdioaudio>; > }; > - pd_tcpc0@RK3399_PD_TCPD0 { > + power-domain@RK3399_PD_TCPD0 { > reg = <RK3399_PD_TCPD0>; > clocks = <&cru SCLK_UPHY0_TCPDCORE>, > <&cru SCLK_UPHY0_TCPDPHY_REF>; > }; > - pd_tcpc1@RK3399_PD_TCPD1 { > + power-domain@RK3399_PD_TCPD1 { > reg = <RK3399_PD_TCPD1>; > clocks = <&cru SCLK_UPHY1_TCPDCORE>, > <&cru SCLK_UPHY1_TCPDPHY_REF>; > }; > - pd_usb3@RK3399_PD_USB3 { > + power-domain@RK3399_PD_USB3 { > reg = <RK3399_PD_USB3>; > clocks = <&cru ACLK_USB3>; > pm_qos = <&qos_usb_otg0>, > <&qos_usb_otg1>; > }; > - pd_vio@RK3399_PD_VIO { > + power-domain@RK3399_PD_VIO { > reg = <RK3399_PD_VIO>; > #address-cells = <1>; > #size-cells = <0>; > > - pd_hdcp@RK3399_PD_HDCP { > + power-domain@RK3399_PD_HDCP { > reg = <RK3399_PD_HDCP>; > clocks = <&cru ACLK_HDCP>, > <&cru HCLK_HDCP>, > <&cru PCLK_HDCP>; > pm_qos = <&qos_hdcp>; > }; > - pd_isp0@RK3399_PD_ISP0 { > + power-domain@RK3399_PD_ISP0 { > reg = <RK3399_PD_ISP0>; > clocks = <&cru ACLK_ISP0>, > <&cru HCLK_ISP0>; > pm_qos = <&qos_isp0_m0>, > <&qos_isp0_m1>; > }; > - pd_isp1@RK3399_PD_ISP1 { > + power-domain@RK3399_PD_ISP1 { > reg = <RK3399_PD_ISP1>; > clocks = <&cru ACLK_ISP1>, > <&cru HCLK_ISP1>; > pm_qos = <&qos_isp1_m0>, > <&qos_isp1_m1>; > }; > - pd_vo@RK3399_PD_VO { > + power-domain@RK3399_PD_VO { > reg = <RK3399_PD_VO>; > #address-cells = <1>; > #size-cells = <0>; > > - pd_vopb@RK3399_PD_VOPB { > + power-domain@RK3399_PD_VOPB { > reg = <RK3399_PD_VOPB>; > clocks = <&cru ACLK_VOP0>, > <&cru HCLK_VOP0>; > pm_qos = <&qos_vop_big_r>, > <&qos_vop_big_w>; > }; > - pd_vopl@RK3399_PD_VOPL { > + power-domain@RK3399_PD_VOPL { > reg = <RK3399_PD_VOPL>; > clocks = <&cru ACLK_VOP1>, > <&cru HCLK_VOP1>; > -- > 2.17.1 > > > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v5 06/11] arm64: dts: rockchip: Fix power-controller node names for rk3399 @ 2021-03-26 9:42 ` Enric Balletbo Serra 0 siblings, 0 replies; 75+ messages in thread From: Enric Balletbo Serra @ 2021-03-26 9:42 UTC (permalink / raw) To: Elaine Zhang Cc: Rob Herring, Heiko Stübner, devicetree@vger.kernel.org, Linux ARM, open list:ARM/Rockchip SoC..., linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao Missatge de Elaine Zhang <zhangqing@rock-chips.com> del dia dv., 26 de març 2021 a les 10:18: > > Use more generic names (as recommended in the device tree specification > or the binding documentation) > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > --- > arch/arm64/boot/dts/rockchip/rk3399.dtsi | 40 ++++++++++++------------ > 1 file changed, 20 insertions(+), 20 deletions(-) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi > index edbbf35fe19e..142f5593d48b 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi > @@ -971,26 +971,26 @@ > #size-cells = <0>; > > /* These power domains are grouped by VD_CENTER */ > - pd_iep@RK3399_PD_IEP { > + power-domain@RK3399_PD_IEP { > reg = <RK3399_PD_IEP>; > clocks = <&cru ACLK_IEP>, > <&cru HCLK_IEP>; > pm_qos = <&qos_iep>; > }; > - pd_rga@RK3399_PD_RGA { > + power-domain@RK3399_PD_RGA { > reg = <RK3399_PD_RGA>; > clocks = <&cru ACLK_RGA>, > <&cru HCLK_RGA>; > pm_qos = <&qos_rga_r>, > <&qos_rga_w>; > }; > - pd_vcodec@RK3399_PD_VCODEC { > + power-domain@RK3399_PD_VCODEC { > reg = <RK3399_PD_VCODEC>; > clocks = <&cru ACLK_VCODEC>, > <&cru HCLK_VCODEC>; > pm_qos = <&qos_video_m0>; > }; > - pd_vdu@RK3399_PD_VDU { > + power-domain@RK3399_PD_VDU { > reg = <RK3399_PD_VDU>; > clocks = <&cru ACLK_VDU>, > <&cru HCLK_VDU>; > @@ -999,94 +999,94 @@ > }; > > /* These power domains are grouped by VD_GPU */ > - pd_gpu@RK3399_PD_GPU { > + power-domain@RK3399_PD_GPU { > reg = <RK3399_PD_GPU>; > clocks = <&cru ACLK_GPU>; > pm_qos = <&qos_gpu>; > }; > > /* These power domains are grouped by VD_LOGIC */ > - pd_edp@RK3399_PD_EDP { > + power-domain@RK3399_PD_EDP { > reg = <RK3399_PD_EDP>; > clocks = <&cru PCLK_EDP_CTRL>; > }; > - pd_emmc@RK3399_PD_EMMC { > + power-domain@RK3399_PD_EMMC { > reg = <RK3399_PD_EMMC>; > clocks = <&cru ACLK_EMMC>; > pm_qos = <&qos_emmc>; > }; > - pd_gmac@RK3399_PD_GMAC { > + power-domain@RK3399_PD_GMAC { > reg = <RK3399_PD_GMAC>; > clocks = <&cru ACLK_GMAC>, > <&cru PCLK_GMAC>; > pm_qos = <&qos_gmac>; > }; > - pd_sd@RK3399_PD_SD { > + power-domain@RK3399_PD_SD { > reg = <RK3399_PD_SD>; > clocks = <&cru HCLK_SDMMC>, > <&cru SCLK_SDMMC>; > pm_qos = <&qos_sd>; > }; > - pd_sdioaudio@RK3399_PD_SDIOAUDIO { > + power-domain@RK3399_PD_SDIOAUDIO { > reg = <RK3399_PD_SDIOAUDIO>; > clocks = <&cru HCLK_SDIO>; > pm_qos = <&qos_sdioaudio>; > }; > - pd_tcpc0@RK3399_PD_TCPD0 { > + power-domain@RK3399_PD_TCPD0 { > reg = <RK3399_PD_TCPD0>; > clocks = <&cru SCLK_UPHY0_TCPDCORE>, > <&cru SCLK_UPHY0_TCPDPHY_REF>; > }; > - pd_tcpc1@RK3399_PD_TCPD1 { > + power-domain@RK3399_PD_TCPD1 { > reg = <RK3399_PD_TCPD1>; > clocks = <&cru SCLK_UPHY1_TCPDCORE>, > <&cru SCLK_UPHY1_TCPDPHY_REF>; > }; > - pd_usb3@RK3399_PD_USB3 { > + power-domain@RK3399_PD_USB3 { > reg = <RK3399_PD_USB3>; > clocks = <&cru ACLK_USB3>; > pm_qos = <&qos_usb_otg0>, > <&qos_usb_otg1>; > }; > - pd_vio@RK3399_PD_VIO { > + power-domain@RK3399_PD_VIO { > reg = <RK3399_PD_VIO>; > #address-cells = <1>; > #size-cells = <0>; > > - pd_hdcp@RK3399_PD_HDCP { > + power-domain@RK3399_PD_HDCP { > reg = <RK3399_PD_HDCP>; > clocks = <&cru ACLK_HDCP>, > <&cru HCLK_HDCP>, > <&cru PCLK_HDCP>; > pm_qos = <&qos_hdcp>; > }; > - pd_isp0@RK3399_PD_ISP0 { > + power-domain@RK3399_PD_ISP0 { > reg = <RK3399_PD_ISP0>; > clocks = <&cru ACLK_ISP0>, > <&cru HCLK_ISP0>; > pm_qos = <&qos_isp0_m0>, > <&qos_isp0_m1>; > }; > - pd_isp1@RK3399_PD_ISP1 { > + power-domain@RK3399_PD_ISP1 { > reg = <RK3399_PD_ISP1>; > clocks = <&cru ACLK_ISP1>, > <&cru HCLK_ISP1>; > pm_qos = <&qos_isp1_m0>, > <&qos_isp1_m1>; > }; > - pd_vo@RK3399_PD_VO { > + power-domain@RK3399_PD_VO { > reg = <RK3399_PD_VO>; > #address-cells = <1>; > #size-cells = <0>; > > - pd_vopb@RK3399_PD_VOPB { > + power-domain@RK3399_PD_VOPB { > reg = <RK3399_PD_VOPB>; > clocks = <&cru ACLK_VOP0>, > <&cru HCLK_VOP0>; > pm_qos = <&qos_vop_big_r>, > <&qos_vop_big_w>; > }; > - pd_vopl@RK3399_PD_VOPL { > + power-domain@RK3399_PD_VOPL { > reg = <RK3399_PD_VOPL>; > clocks = <&cru ACLK_VOP1>, > <&cru HCLK_VOP1>; > -- > 2.17.1 > > > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v5 07/11] soc: rockchip: pm-domains: Add a meaningful power domain name 2021-03-26 9:15 ` Elaine Zhang (?) @ 2021-03-26 9:17 ` Elaine Zhang -1 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:17 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Add the power domains names to the power domain info struct so we have meaningful name for every power domain. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- drivers/soc/rockchip/pm_domains.c | 217 +++++++++++++++--------------- 1 file changed, 112 insertions(+), 105 deletions(-) diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c index 54eb6cfc5d5b..d661d967079f 100644 --- a/drivers/soc/rockchip/pm_domains.c +++ b/drivers/soc/rockchip/pm_domains.c @@ -29,6 +29,7 @@ #include <dt-bindings/power/rk3399-power.h> struct rockchip_domain_info { + const char *name; int pwr_mask; int status_mask; int req_mask; @@ -85,8 +86,9 @@ struct rockchip_pmu { #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd) -#define DOMAIN(pwr, status, req, idle, ack, wakeup) \ +#define DOMAIN(_name, pwr, status, req, idle, ack, wakeup) \ { \ + .name = _name, \ .pwr_mask = (pwr), \ .status_mask = (status), \ .req_mask = (req), \ @@ -95,8 +97,9 @@ struct rockchip_pmu { .active_wakeup = (wakeup), \ } -#define DOMAIN_M(pwr, status, req, idle, ack, wakeup) \ +#define DOMAIN_M(_name, pwr, status, req, idle, ack, wakeup) \ { \ + .name = _name, \ .pwr_w_mask = (pwr) << 16, \ .pwr_mask = (pwr), \ .status_mask = (status), \ @@ -107,8 +110,9 @@ struct rockchip_pmu { .active_wakeup = wakeup, \ } -#define DOMAIN_RK3036(req, ack, idle, wakeup) \ +#define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \ { \ + .name = _name, \ .req_mask = (req), \ .req_w_mask = (req) << 16, \ .ack_mask = (ack), \ @@ -119,17 +123,17 @@ struct rockchip_pmu { #define DOMAIN_PX30(pwr, status, req, wakeup) \ DOMAIN_M(pwr, status, req, (req) << 16, req, wakeup) -#define DOMAIN_RK3288(pwr, status, req, wakeup) \ - DOMAIN(pwr, status, req, req, (req) << 16, wakeup) +#define DOMAIN_RK3288(name, pwr, status, req, wakeup) \ + DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup) -#define DOMAIN_RK3328(pwr, status, req, wakeup) \ - DOMAIN_M(pwr, pwr, req, (req) << 10, req, wakeup) +#define DOMAIN_RK3328(name, pwr, status, req, wakeup) \ + DOMAIN_M(name, pwr, pwr, req, (req) << 10, req, wakeup) -#define DOMAIN_RK3368(pwr, status, req, wakeup) \ - DOMAIN(pwr, status, req, (req) << 16, req, wakeup) +#define DOMAIN_RK3368(name, pwr, status, req, wakeup) \ + DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup) -#define DOMAIN_RK3399(pwr, status, req, wakeup) \ - DOMAIN(pwr, status, req, req, req, wakeup) +#define DOMAIN_RK3399(name, pwr, status, req, wakeup) \ + DOMAIN(name, pwr, status, req, req, req, wakeup) static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd) { @@ -490,7 +494,10 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, goto err_unprepare_clocks; } - pd->genpd.name = node->name; + if (!pd->info->name) + pd->genpd.name = node->name; + else + pd->genpd.name = pd->info->name; pd->genpd.power_off = rockchip_pd_power_off; pd->genpd.power_on = rockchip_pd_power_on; pd->genpd.attach_dev = rockchip_pd_attach_dev; @@ -716,129 +723,129 @@ static int rockchip_pm_domain_probe(struct platform_device *pdev) } static const struct rockchip_domain_info px30_pm_domains[] = { - [PX30_PD_USB] = DOMAIN_PX30(BIT(5), BIT(5), BIT(10), false), - [PX30_PD_SDCARD] = DOMAIN_PX30(BIT(8), BIT(8), BIT(9), false), - [PX30_PD_GMAC] = DOMAIN_PX30(BIT(10), BIT(10), BIT(6), false), - [PX30_PD_MMC_NAND] = DOMAIN_PX30(BIT(11), BIT(11), BIT(5), false), - [PX30_PD_VPU] = DOMAIN_PX30(BIT(12), BIT(12), BIT(14), false), - [PX30_PD_VO] = DOMAIN_PX30(BIT(13), BIT(13), BIT(7), false), - [PX30_PD_VI] = DOMAIN_PX30(BIT(14), BIT(14), BIT(8), false), - [PX30_PD_GPU] = DOMAIN_PX30(BIT(15), BIT(15), BIT(2), false), + [PX30_PD_USB] = DOMAIN_PX30("usb", BIT(5), BIT(5), BIT(10), false), + [PX30_PD_SDCARD] = DOMAIN_PX30("sdcard", BIT(8), BIT(8), BIT(9), false), + [PX30_PD_GMAC] = DOMAIN_PX30("gmac", BIT(10), BIT(10), BIT(6), false), + [PX30_PD_MMC_NAND] = DOMAIN_PX30("mmc_nand", BIT(11), BIT(11), BIT(5), false), + [PX30_PD_VPU] = DOMAIN_PX30("vpu", BIT(12), BIT(12), BIT(14), false), + [PX30_PD_VO] = DOMAIN_PX30("vo", BIT(13), BIT(13), BIT(7), false), + [PX30_PD_VI] = DOMAIN_PX30("vi", BIT(14), BIT(14), BIT(8), false), + [PX30_PD_GPU] = DOMAIN_PX30("gpu", BIT(15), BIT(15), BIT(2), false), }; static const struct rockchip_domain_info rk3036_pm_domains[] = { - [RK3036_PD_MSCH] = DOMAIN_RK3036(BIT(14), BIT(23), BIT(30), true), - [RK3036_PD_CORE] = DOMAIN_RK3036(BIT(13), BIT(17), BIT(24), false), - [RK3036_PD_PERI] = DOMAIN_RK3036(BIT(12), BIT(18), BIT(25), false), - [RK3036_PD_VIO] = DOMAIN_RK3036(BIT(11), BIT(19), BIT(26), false), - [RK3036_PD_VPU] = DOMAIN_RK3036(BIT(10), BIT(20), BIT(27), false), - [RK3036_PD_GPU] = DOMAIN_RK3036(BIT(9), BIT(21), BIT(28), false), - [RK3036_PD_SYS] = DOMAIN_RK3036(BIT(8), BIT(22), BIT(29), false), + [RK3036_PD_MSCH] = DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true), + [RK3036_PD_CORE] = DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false), + [RK3036_PD_PERI] = DOMAIN_RK3036("peri", BIT(12), BIT(18), BIT(25), false), + [RK3036_PD_VIO] = DOMAIN_RK3036("vio", BIT(11), BIT(19), BIT(26), false), + [RK3036_PD_VPU] = DOMAIN_RK3036("vpu", BIT(10), BIT(20), BIT(27), false), + [RK3036_PD_GPU] = DOMAIN_RK3036("gpu", BIT(9), BIT(21), BIT(28), false), + [RK3036_PD_SYS] = DOMAIN_RK3036("sys", BIT(8), BIT(22), BIT(29), false), }; static const struct rockchip_domain_info rk3066_pm_domains[] = { - [RK3066_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), - [RK3066_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), - [RK3066_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), - [RK3066_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), - [RK3066_PD_CPU] = DOMAIN(0, BIT(5), BIT(1), BIT(26), BIT(31), false), + [RK3066_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), + [RK3066_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), + [RK3066_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), + [RK3066_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), + [RK3066_PD_CPU] = DOMAIN("cpu", 0, BIT(5), BIT(1), BIT(26), BIT(31), false), }; static const struct rockchip_domain_info rk3128_pm_domains[] = { - [RK3128_PD_CORE] = DOMAIN_RK3288(BIT(0), BIT(0), BIT(4), false), - [RK3128_PD_MSCH] = DOMAIN_RK3288(0, 0, BIT(6), true), - [RK3128_PD_VIO] = DOMAIN_RK3288(BIT(3), BIT(3), BIT(2), false), - [RK3128_PD_VIDEO] = DOMAIN_RK3288(BIT(2), BIT(2), BIT(1), false), - [RK3128_PD_GPU] = DOMAIN_RK3288(BIT(1), BIT(1), BIT(3), false), + [RK3128_PD_CORE] = DOMAIN_RK3288("core", BIT(0), BIT(0), BIT(4), false), + [RK3128_PD_MSCH] = DOMAIN_RK3288("msch", 0, 0, BIT(6), true), + [RK3128_PD_VIO] = DOMAIN_RK3288("vio", BIT(3), BIT(3), BIT(2), false), + [RK3128_PD_VIDEO] = DOMAIN_RK3288("video", BIT(2), BIT(2), BIT(1), false), + [RK3128_PD_GPU] = DOMAIN_RK3288("gpu", BIT(1), BIT(1), BIT(3), false), }; static const struct rockchip_domain_info rk3188_pm_domains[] = { - [RK3188_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), - [RK3188_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), - [RK3188_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), - [RK3188_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), - [RK3188_PD_CPU] = DOMAIN(BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false), + [RK3188_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), + [RK3188_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), + [RK3188_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), + [RK3188_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), + [RK3188_PD_CPU] = DOMAIN("cpu", BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false), }; static const struct rockchip_domain_info rk3228_pm_domains[] = { - [RK3228_PD_CORE] = DOMAIN_RK3036(BIT(0), BIT(0), BIT(16), true), - [RK3228_PD_MSCH] = DOMAIN_RK3036(BIT(1), BIT(1), BIT(17), true), - [RK3228_PD_BUS] = DOMAIN_RK3036(BIT(2), BIT(2), BIT(18), true), - [RK3228_PD_SYS] = DOMAIN_RK3036(BIT(3), BIT(3), BIT(19), true), - [RK3228_PD_VIO] = DOMAIN_RK3036(BIT(4), BIT(4), BIT(20), false), - [RK3228_PD_VOP] = DOMAIN_RK3036(BIT(5), BIT(5), BIT(21), false), - [RK3228_PD_VPU] = DOMAIN_RK3036(BIT(6), BIT(6), BIT(22), false), - [RK3228_PD_RKVDEC] = DOMAIN_RK3036(BIT(7), BIT(7), BIT(23), false), - [RK3228_PD_GPU] = DOMAIN_RK3036(BIT(8), BIT(8), BIT(24), false), - [RK3228_PD_PERI] = DOMAIN_RK3036(BIT(9), BIT(9), BIT(25), true), - [RK3228_PD_GMAC] = DOMAIN_RK3036(BIT(10), BIT(10), BIT(26), false), + [RK3228_PD_CORE] = DOMAIN_RK3036("core", BIT(0), BIT(0), BIT(16), true), + [RK3228_PD_MSCH] = DOMAIN_RK3036("msch", BIT(1), BIT(1), BIT(17), true), + [RK3228_PD_BUS] = DOMAIN_RK3036("bus", BIT(2), BIT(2), BIT(18), true), + [RK3228_PD_SYS] = DOMAIN_RK3036("sys", BIT(3), BIT(3), BIT(19), true), + [RK3228_PD_VIO] = DOMAIN_RK3036("vio", BIT(4), BIT(4), BIT(20), false), + [RK3228_PD_VOP] = DOMAIN_RK3036("vop", BIT(5), BIT(5), BIT(21), false), + [RK3228_PD_VPU] = DOMAIN_RK3036("vpu", BIT(6), BIT(6), BIT(22), false), + [RK3228_PD_RKVDEC] = DOMAIN_RK3036("vdec", BIT(7), BIT(7), BIT(23), false), + [RK3228_PD_GPU] = DOMAIN_RK3036("gpu", BIT(8), BIT(8), BIT(24), false), + [RK3228_PD_PERI] = DOMAIN_RK3036("peri", BIT(9), BIT(9), BIT(25), true), + [RK3228_PD_GMAC] = DOMAIN_RK3036("gmac", BIT(10), BIT(10), BIT(26), false), }; static const struct rockchip_domain_info rk3288_pm_domains[] = { - [RK3288_PD_VIO] = DOMAIN_RK3288(BIT(7), BIT(7), BIT(4), false), - [RK3288_PD_HEVC] = DOMAIN_RK3288(BIT(14), BIT(10), BIT(9), false), - [RK3288_PD_VIDEO] = DOMAIN_RK3288(BIT(8), BIT(8), BIT(3), false), - [RK3288_PD_GPU] = DOMAIN_RK3288(BIT(9), BIT(9), BIT(2), false), + [RK3288_PD_VIO] = DOMAIN_RK3288("vio", BIT(7), BIT(7), BIT(4), false), + [RK3288_PD_HEVC] = DOMAIN_RK3288("hevc", BIT(14), BIT(10), BIT(9), false), + [RK3288_PD_VIDEO] = DOMAIN_RK3288("video", BIT(8), BIT(8), BIT(3), false), + [RK3288_PD_GPU] = DOMAIN_RK3288("gpu", BIT(9), BIT(9), BIT(2), false), }; static const struct rockchip_domain_info rk3328_pm_domains[] = { - [RK3328_PD_CORE] = DOMAIN_RK3328(0, BIT(0), BIT(0), false), - [RK3328_PD_GPU] = DOMAIN_RK3328(0, BIT(1), BIT(1), false), - [RK3328_PD_BUS] = DOMAIN_RK3328(0, BIT(2), BIT(2), true), - [RK3328_PD_MSCH] = DOMAIN_RK3328(0, BIT(3), BIT(3), true), - [RK3328_PD_PERI] = DOMAIN_RK3328(0, BIT(4), BIT(4), true), - [RK3328_PD_VIDEO] = DOMAIN_RK3328(0, BIT(5), BIT(5), false), - [RK3328_PD_HEVC] = DOMAIN_RK3328(0, BIT(6), BIT(6), false), - [RK3328_PD_VIO] = DOMAIN_RK3328(0, BIT(8), BIT(8), false), - [RK3328_PD_VPU] = DOMAIN_RK3328(0, BIT(9), BIT(9), false), + [RK3328_PD_CORE] = DOMAIN_RK3328("core", 0, BIT(0), BIT(0), false), + [RK3328_PD_GPU] = DOMAIN_RK3328("gpu", 0, BIT(1), BIT(1), false), + [RK3328_PD_BUS] = DOMAIN_RK3328("bus", 0, BIT(2), BIT(2), true), + [RK3328_PD_MSCH] = DOMAIN_RK3328("msch", 0, BIT(3), BIT(3), true), + [RK3328_PD_PERI] = DOMAIN_RK3328("peri", 0, BIT(4), BIT(4), true), + [RK3328_PD_VIDEO] = DOMAIN_RK3328("video", 0, BIT(5), BIT(5), false), + [RK3328_PD_HEVC] = DOMAIN_RK3328("hevc", 0, BIT(6), BIT(6), false), + [RK3328_PD_VIO] = DOMAIN_RK3328("vio", 0, BIT(8), BIT(8), false), + [RK3328_PD_VPU] = DOMAIN_RK3328("vpu", 0, BIT(9), BIT(9), false), }; static const struct rockchip_domain_info rk3366_pm_domains[] = { - [RK3366_PD_PERI] = DOMAIN_RK3368(BIT(10), BIT(10), BIT(6), true), - [RK3366_PD_VIO] = DOMAIN_RK3368(BIT(14), BIT(14), BIT(8), false), - [RK3366_PD_VIDEO] = DOMAIN_RK3368(BIT(13), BIT(13), BIT(7), false), - [RK3366_PD_RKVDEC] = DOMAIN_RK3368(BIT(11), BIT(11), BIT(7), false), - [RK3366_PD_WIFIBT] = DOMAIN_RK3368(BIT(8), BIT(8), BIT(9), false), - [RK3366_PD_VPU] = DOMAIN_RK3368(BIT(12), BIT(12), BIT(7), false), - [RK3366_PD_GPU] = DOMAIN_RK3368(BIT(15), BIT(15), BIT(2), false), + [RK3366_PD_PERI] = DOMAIN_RK3368("peri", BIT(10), BIT(10), BIT(6), true), + [RK3366_PD_VIO] = DOMAIN_RK3368("vio", BIT(14), BIT(14), BIT(8), false), + [RK3366_PD_VIDEO] = DOMAIN_RK3368("video", BIT(13), BIT(13), BIT(7), false), + [RK3366_PD_RKVDEC] = DOMAIN_RK3368("vdec", BIT(11), BIT(11), BIT(7), false), + [RK3366_PD_WIFIBT] = DOMAIN_RK3368("wifibt", BIT(8), BIT(8), BIT(9), false), + [RK3366_PD_VPU] = DOMAIN_RK3368("vpu", BIT(12), BIT(12), BIT(7), false), + [RK3366_PD_GPU] = DOMAIN_RK3368("gpu", BIT(15), BIT(15), BIT(2), false), }; static const struct rockchip_domain_info rk3368_pm_domains[] = { - [RK3368_PD_PERI] = DOMAIN_RK3368(BIT(13), BIT(12), BIT(6), true), - [RK3368_PD_VIO] = DOMAIN_RK3368(BIT(15), BIT(14), BIT(8), false), - [RK3368_PD_VIDEO] = DOMAIN_RK3368(BIT(14), BIT(13), BIT(7), false), - [RK3368_PD_GPU_0] = DOMAIN_RK3368(BIT(16), BIT(15), BIT(2), false), - [RK3368_PD_GPU_1] = DOMAIN_RK3368(BIT(17), BIT(16), BIT(2), false), + [RK3368_PD_PERI] = DOMAIN_RK3368("peri", BIT(13), BIT(12), BIT(6), true), + [RK3368_PD_VIO] = DOMAIN_RK3368("vio", BIT(15), BIT(14), BIT(8), false), + [RK3368_PD_VIDEO] = DOMAIN_RK3368("video", BIT(14), BIT(13), BIT(7), false), + [RK3368_PD_GPU_0] = DOMAIN_RK3368("gpu_0", BIT(16), BIT(15), BIT(2), false), + [RK3368_PD_GPU_1] = DOMAIN_RK3368("gpu_1", BIT(17), BIT(16), BIT(2), false), }; static const struct rockchip_domain_info rk3399_pm_domains[] = { - [RK3399_PD_TCPD0] = DOMAIN_RK3399(BIT(8), BIT(8), 0, false), - [RK3399_PD_TCPD1] = DOMAIN_RK3399(BIT(9), BIT(9), 0, false), - [RK3399_PD_CCI] = DOMAIN_RK3399(BIT(10), BIT(10), 0, true), - [RK3399_PD_CCI0] = DOMAIN_RK3399(0, 0, BIT(15), true), - [RK3399_PD_CCI1] = DOMAIN_RK3399(0, 0, BIT(16), true), - [RK3399_PD_PERILP] = DOMAIN_RK3399(BIT(11), BIT(11), BIT(1), true), - [RK3399_PD_PERIHP] = DOMAIN_RK3399(BIT(12), BIT(12), BIT(2), true), - [RK3399_PD_CENTER] = DOMAIN_RK3399(BIT(13), BIT(13), BIT(14), true), - [RK3399_PD_VIO] = DOMAIN_RK3399(BIT(14), BIT(14), BIT(17), false), - [RK3399_PD_GPU] = DOMAIN_RK3399(BIT(15), BIT(15), BIT(0), false), - [RK3399_PD_VCODEC] = DOMAIN_RK3399(BIT(16), BIT(16), BIT(3), false), - [RK3399_PD_VDU] = DOMAIN_RK3399(BIT(17), BIT(17), BIT(4), false), - [RK3399_PD_RGA] = DOMAIN_RK3399(BIT(18), BIT(18), BIT(5), false), - [RK3399_PD_IEP] = DOMAIN_RK3399(BIT(19), BIT(19), BIT(6), false), - [RK3399_PD_VO] = DOMAIN_RK3399(BIT(20), BIT(20), 0, false), - [RK3399_PD_VOPB] = DOMAIN_RK3399(0, 0, BIT(7), false), - [RK3399_PD_VOPL] = DOMAIN_RK3399(0, 0, BIT(8), false), - [RK3399_PD_ISP0] = DOMAIN_RK3399(BIT(22), BIT(22), BIT(9), false), - [RK3399_PD_ISP1] = DOMAIN_RK3399(BIT(23), BIT(23), BIT(10), false), - [RK3399_PD_HDCP] = DOMAIN_RK3399(BIT(24), BIT(24), BIT(11), false), - [RK3399_PD_GMAC] = DOMAIN_RK3399(BIT(25), BIT(25), BIT(23), true), - [RK3399_PD_EMMC] = DOMAIN_RK3399(BIT(26), BIT(26), BIT(24), true), - [RK3399_PD_USB3] = DOMAIN_RK3399(BIT(27), BIT(27), BIT(12), true), - [RK3399_PD_EDP] = DOMAIN_RK3399(BIT(28), BIT(28), BIT(22), false), - [RK3399_PD_GIC] = DOMAIN_RK3399(BIT(29), BIT(29), BIT(27), true), - [RK3399_PD_SD] = DOMAIN_RK3399(BIT(30), BIT(30), BIT(28), true), - [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399(BIT(31), BIT(31), BIT(29), true), + [RK3399_PD_TCPD0] = DOMAIN_RK3399("tcpd0", BIT(8), BIT(8), 0, false), + [RK3399_PD_TCPD1] = DOMAIN_RK3399("tcpd1", BIT(9), BIT(9), 0, false), + [RK3399_PD_CCI] = DOMAIN_RK3399("cci", BIT(10), BIT(10), 0, true), + [RK3399_PD_CCI0] = DOMAIN_RK3399("cci0", 0, 0, BIT(15), true), + [RK3399_PD_CCI1] = DOMAIN_RK3399("cci1", 0, 0, BIT(16), true), + [RK3399_PD_PERILP] = DOMAIN_RK3399("perilp", BIT(11), BIT(11), BIT(1), true), + [RK3399_PD_PERIHP] = DOMAIN_RK3399("perihp", BIT(12), BIT(12), BIT(2), true), + [RK3399_PD_CENTER] = DOMAIN_RK3399("center", BIT(13), BIT(13), BIT(14), true), + [RK3399_PD_VIO] = DOMAIN_RK3399("vio", BIT(14), BIT(14), BIT(17), false), + [RK3399_PD_GPU] = DOMAIN_RK3399("gpu", BIT(15), BIT(15), BIT(0), false), + [RK3399_PD_VCODEC] = DOMAIN_RK3399("vcodec", BIT(16), BIT(16), BIT(3), false), + [RK3399_PD_VDU] = DOMAIN_RK3399("vdu", BIT(17), BIT(17), BIT(4), false), + [RK3399_PD_RGA] = DOMAIN_RK3399("rga", BIT(18), BIT(18), BIT(5), false), + [RK3399_PD_IEP] = DOMAIN_RK3399("iep", BIT(19), BIT(19), BIT(6), false), + [RK3399_PD_VO] = DOMAIN_RK3399("vo", BIT(20), BIT(20), 0, false), + [RK3399_PD_VOPB] = DOMAIN_RK3399("vopb", 0, 0, BIT(7), false), + [RK3399_PD_VOPL] = DOMAIN_RK3399("vopl", 0, 0, BIT(8), false), + [RK3399_PD_ISP0] = DOMAIN_RK3399("isp0", BIT(22), BIT(22), BIT(9), false), + [RK3399_PD_ISP1] = DOMAIN_RK3399("isp1", BIT(23), BIT(23), BIT(10), false), + [RK3399_PD_HDCP] = DOMAIN_RK3399("hdcp", BIT(24), BIT(24), BIT(11), false), + [RK3399_PD_GMAC] = DOMAIN_RK3399("gmac", BIT(25), BIT(25), BIT(23), true), + [RK3399_PD_EMMC] = DOMAIN_RK3399("emmc", BIT(26), BIT(26), BIT(24), true), + [RK3399_PD_USB3] = DOMAIN_RK3399("usb3", BIT(27), BIT(27), BIT(12), true), + [RK3399_PD_EDP] = DOMAIN_RK3399("edp", BIT(28), BIT(28), BIT(22), false), + [RK3399_PD_GIC] = DOMAIN_RK3399("gic", BIT(29), BIT(29), BIT(27), true), + [RK3399_PD_SD] = DOMAIN_RK3399("sd", BIT(30), BIT(30), BIT(28), true), + [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true), }; static const struct rockchip_pmu_info px30_pmu = { -- 2.17.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v5 07/11] soc: rockchip: pm-domains: Add a meaningful power domain name @ 2021-03-26 9:17 ` Elaine Zhang 0 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:17 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Add the power domains names to the power domain info struct so we have meaningful name for every power domain. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- drivers/soc/rockchip/pm_domains.c | 217 +++++++++++++++--------------- 1 file changed, 112 insertions(+), 105 deletions(-) diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c index 54eb6cfc5d5b..d661d967079f 100644 --- a/drivers/soc/rockchip/pm_domains.c +++ b/drivers/soc/rockchip/pm_domains.c @@ -29,6 +29,7 @@ #include <dt-bindings/power/rk3399-power.h> struct rockchip_domain_info { + const char *name; int pwr_mask; int status_mask; int req_mask; @@ -85,8 +86,9 @@ struct rockchip_pmu { #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd) -#define DOMAIN(pwr, status, req, idle, ack, wakeup) \ +#define DOMAIN(_name, pwr, status, req, idle, ack, wakeup) \ { \ + .name = _name, \ .pwr_mask = (pwr), \ .status_mask = (status), \ .req_mask = (req), \ @@ -95,8 +97,9 @@ struct rockchip_pmu { .active_wakeup = (wakeup), \ } -#define DOMAIN_M(pwr, status, req, idle, ack, wakeup) \ +#define DOMAIN_M(_name, pwr, status, req, idle, ack, wakeup) \ { \ + .name = _name, \ .pwr_w_mask = (pwr) << 16, \ .pwr_mask = (pwr), \ .status_mask = (status), \ @@ -107,8 +110,9 @@ struct rockchip_pmu { .active_wakeup = wakeup, \ } -#define DOMAIN_RK3036(req, ack, idle, wakeup) \ +#define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \ { \ + .name = _name, \ .req_mask = (req), \ .req_w_mask = (req) << 16, \ .ack_mask = (ack), \ @@ -119,17 +123,17 @@ struct rockchip_pmu { #define DOMAIN_PX30(pwr, status, req, wakeup) \ DOMAIN_M(pwr, status, req, (req) << 16, req, wakeup) -#define DOMAIN_RK3288(pwr, status, req, wakeup) \ - DOMAIN(pwr, status, req, req, (req) << 16, wakeup) +#define DOMAIN_RK3288(name, pwr, status, req, wakeup) \ + DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup) -#define DOMAIN_RK3328(pwr, status, req, wakeup) \ - DOMAIN_M(pwr, pwr, req, (req) << 10, req, wakeup) +#define DOMAIN_RK3328(name, pwr, status, req, wakeup) \ + DOMAIN_M(name, pwr, pwr, req, (req) << 10, req, wakeup) -#define DOMAIN_RK3368(pwr, status, req, wakeup) \ - DOMAIN(pwr, status, req, (req) << 16, req, wakeup) +#define DOMAIN_RK3368(name, pwr, status, req, wakeup) \ + DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup) -#define DOMAIN_RK3399(pwr, status, req, wakeup) \ - DOMAIN(pwr, status, req, req, req, wakeup) +#define DOMAIN_RK3399(name, pwr, status, req, wakeup) \ + DOMAIN(name, pwr, status, req, req, req, wakeup) static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd) { @@ -490,7 +494,10 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, goto err_unprepare_clocks; } - pd->genpd.name = node->name; + if (!pd->info->name) + pd->genpd.name = node->name; + else + pd->genpd.name = pd->info->name; pd->genpd.power_off = rockchip_pd_power_off; pd->genpd.power_on = rockchip_pd_power_on; pd->genpd.attach_dev = rockchip_pd_attach_dev; @@ -716,129 +723,129 @@ static int rockchip_pm_domain_probe(struct platform_device *pdev) } static const struct rockchip_domain_info px30_pm_domains[] = { - [PX30_PD_USB] = DOMAIN_PX30(BIT(5), BIT(5), BIT(10), false), - [PX30_PD_SDCARD] = DOMAIN_PX30(BIT(8), BIT(8), BIT(9), false), - [PX30_PD_GMAC] = DOMAIN_PX30(BIT(10), BIT(10), BIT(6), false), - [PX30_PD_MMC_NAND] = DOMAIN_PX30(BIT(11), BIT(11), BIT(5), false), - [PX30_PD_VPU] = DOMAIN_PX30(BIT(12), BIT(12), BIT(14), false), - [PX30_PD_VO] = DOMAIN_PX30(BIT(13), BIT(13), BIT(7), false), - [PX30_PD_VI] = DOMAIN_PX30(BIT(14), BIT(14), BIT(8), false), - [PX30_PD_GPU] = DOMAIN_PX30(BIT(15), BIT(15), BIT(2), false), + [PX30_PD_USB] = DOMAIN_PX30("usb", BIT(5), BIT(5), BIT(10), false), + [PX30_PD_SDCARD] = DOMAIN_PX30("sdcard", BIT(8), BIT(8), BIT(9), false), + [PX30_PD_GMAC] = DOMAIN_PX30("gmac", BIT(10), BIT(10), BIT(6), false), + [PX30_PD_MMC_NAND] = DOMAIN_PX30("mmc_nand", BIT(11), BIT(11), BIT(5), false), + [PX30_PD_VPU] = DOMAIN_PX30("vpu", BIT(12), BIT(12), BIT(14), false), + [PX30_PD_VO] = DOMAIN_PX30("vo", BIT(13), BIT(13), BIT(7), false), + [PX30_PD_VI] = DOMAIN_PX30("vi", BIT(14), BIT(14), BIT(8), false), + [PX30_PD_GPU] = DOMAIN_PX30("gpu", BIT(15), BIT(15), BIT(2), false), }; static const struct rockchip_domain_info rk3036_pm_domains[] = { - [RK3036_PD_MSCH] = DOMAIN_RK3036(BIT(14), BIT(23), BIT(30), true), - [RK3036_PD_CORE] = DOMAIN_RK3036(BIT(13), BIT(17), BIT(24), false), - [RK3036_PD_PERI] = DOMAIN_RK3036(BIT(12), BIT(18), BIT(25), false), - [RK3036_PD_VIO] = DOMAIN_RK3036(BIT(11), BIT(19), BIT(26), false), - [RK3036_PD_VPU] = DOMAIN_RK3036(BIT(10), BIT(20), BIT(27), false), - [RK3036_PD_GPU] = DOMAIN_RK3036(BIT(9), BIT(21), BIT(28), false), - [RK3036_PD_SYS] = DOMAIN_RK3036(BIT(8), BIT(22), BIT(29), false), + [RK3036_PD_MSCH] = DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true), + [RK3036_PD_CORE] = DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false), + [RK3036_PD_PERI] = DOMAIN_RK3036("peri", BIT(12), BIT(18), BIT(25), false), + [RK3036_PD_VIO] = DOMAIN_RK3036("vio", BIT(11), BIT(19), BIT(26), false), + [RK3036_PD_VPU] = DOMAIN_RK3036("vpu", BIT(10), BIT(20), BIT(27), false), + [RK3036_PD_GPU] = DOMAIN_RK3036("gpu", BIT(9), BIT(21), BIT(28), false), + [RK3036_PD_SYS] = DOMAIN_RK3036("sys", BIT(8), BIT(22), BIT(29), false), }; static const struct rockchip_domain_info rk3066_pm_domains[] = { - [RK3066_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), - [RK3066_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), - [RK3066_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), - [RK3066_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), - [RK3066_PD_CPU] = DOMAIN(0, BIT(5), BIT(1), BIT(26), BIT(31), false), + [RK3066_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), + [RK3066_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), + [RK3066_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), + [RK3066_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), + [RK3066_PD_CPU] = DOMAIN("cpu", 0, BIT(5), BIT(1), BIT(26), BIT(31), false), }; static const struct rockchip_domain_info rk3128_pm_domains[] = { - [RK3128_PD_CORE] = DOMAIN_RK3288(BIT(0), BIT(0), BIT(4), false), - [RK3128_PD_MSCH] = DOMAIN_RK3288(0, 0, BIT(6), true), - [RK3128_PD_VIO] = DOMAIN_RK3288(BIT(3), BIT(3), BIT(2), false), - [RK3128_PD_VIDEO] = DOMAIN_RK3288(BIT(2), BIT(2), BIT(1), false), - [RK3128_PD_GPU] = DOMAIN_RK3288(BIT(1), BIT(1), BIT(3), false), + [RK3128_PD_CORE] = DOMAIN_RK3288("core", BIT(0), BIT(0), BIT(4), false), + [RK3128_PD_MSCH] = DOMAIN_RK3288("msch", 0, 0, BIT(6), true), + [RK3128_PD_VIO] = DOMAIN_RK3288("vio", BIT(3), BIT(3), BIT(2), false), + [RK3128_PD_VIDEO] = DOMAIN_RK3288("video", BIT(2), BIT(2), BIT(1), false), + [RK3128_PD_GPU] = DOMAIN_RK3288("gpu", BIT(1), BIT(1), BIT(3), false), }; static const struct rockchip_domain_info rk3188_pm_domains[] = { - [RK3188_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), - [RK3188_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), - [RK3188_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), - [RK3188_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), - [RK3188_PD_CPU] = DOMAIN(BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false), + [RK3188_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), + [RK3188_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), + [RK3188_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), + [RK3188_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), + [RK3188_PD_CPU] = DOMAIN("cpu", BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false), }; static const struct rockchip_domain_info rk3228_pm_domains[] = { - [RK3228_PD_CORE] = DOMAIN_RK3036(BIT(0), BIT(0), BIT(16), true), - [RK3228_PD_MSCH] = DOMAIN_RK3036(BIT(1), BIT(1), BIT(17), true), - [RK3228_PD_BUS] = DOMAIN_RK3036(BIT(2), BIT(2), BIT(18), true), - [RK3228_PD_SYS] = DOMAIN_RK3036(BIT(3), BIT(3), BIT(19), true), - [RK3228_PD_VIO] = DOMAIN_RK3036(BIT(4), BIT(4), BIT(20), false), - [RK3228_PD_VOP] = DOMAIN_RK3036(BIT(5), BIT(5), BIT(21), false), - [RK3228_PD_VPU] = DOMAIN_RK3036(BIT(6), BIT(6), BIT(22), false), - [RK3228_PD_RKVDEC] = DOMAIN_RK3036(BIT(7), BIT(7), BIT(23), false), - [RK3228_PD_GPU] = DOMAIN_RK3036(BIT(8), BIT(8), BIT(24), false), - [RK3228_PD_PERI] = DOMAIN_RK3036(BIT(9), BIT(9), BIT(25), true), - [RK3228_PD_GMAC] = DOMAIN_RK3036(BIT(10), BIT(10), BIT(26), false), + [RK3228_PD_CORE] = DOMAIN_RK3036("core", BIT(0), BIT(0), BIT(16), true), + [RK3228_PD_MSCH] = DOMAIN_RK3036("msch", BIT(1), BIT(1), BIT(17), true), + [RK3228_PD_BUS] = DOMAIN_RK3036("bus", BIT(2), BIT(2), BIT(18), true), + [RK3228_PD_SYS] = DOMAIN_RK3036("sys", BIT(3), BIT(3), BIT(19), true), + [RK3228_PD_VIO] = DOMAIN_RK3036("vio", BIT(4), BIT(4), BIT(20), false), + [RK3228_PD_VOP] = DOMAIN_RK3036("vop", BIT(5), BIT(5), BIT(21), false), + [RK3228_PD_VPU] = DOMAIN_RK3036("vpu", BIT(6), BIT(6), BIT(22), false), + [RK3228_PD_RKVDEC] = DOMAIN_RK3036("vdec", BIT(7), BIT(7), BIT(23), false), + [RK3228_PD_GPU] = DOMAIN_RK3036("gpu", BIT(8), BIT(8), BIT(24), false), + [RK3228_PD_PERI] = DOMAIN_RK3036("peri", BIT(9), BIT(9), BIT(25), true), + [RK3228_PD_GMAC] = DOMAIN_RK3036("gmac", BIT(10), BIT(10), BIT(26), false), }; static const struct rockchip_domain_info rk3288_pm_domains[] = { - [RK3288_PD_VIO] = DOMAIN_RK3288(BIT(7), BIT(7), BIT(4), false), - [RK3288_PD_HEVC] = DOMAIN_RK3288(BIT(14), BIT(10), BIT(9), false), - [RK3288_PD_VIDEO] = DOMAIN_RK3288(BIT(8), BIT(8), BIT(3), false), - [RK3288_PD_GPU] = DOMAIN_RK3288(BIT(9), BIT(9), BIT(2), false), + [RK3288_PD_VIO] = DOMAIN_RK3288("vio", BIT(7), BIT(7), BIT(4), false), + [RK3288_PD_HEVC] = DOMAIN_RK3288("hevc", BIT(14), BIT(10), BIT(9), false), + [RK3288_PD_VIDEO] = DOMAIN_RK3288("video", BIT(8), BIT(8), BIT(3), false), + [RK3288_PD_GPU] = DOMAIN_RK3288("gpu", BIT(9), BIT(9), BIT(2), false), }; static const struct rockchip_domain_info rk3328_pm_domains[] = { - [RK3328_PD_CORE] = DOMAIN_RK3328(0, BIT(0), BIT(0), false), - [RK3328_PD_GPU] = DOMAIN_RK3328(0, BIT(1), BIT(1), false), - [RK3328_PD_BUS] = DOMAIN_RK3328(0, BIT(2), BIT(2), true), - [RK3328_PD_MSCH] = DOMAIN_RK3328(0, BIT(3), BIT(3), true), - [RK3328_PD_PERI] = DOMAIN_RK3328(0, BIT(4), BIT(4), true), - [RK3328_PD_VIDEO] = DOMAIN_RK3328(0, BIT(5), BIT(5), false), - [RK3328_PD_HEVC] = DOMAIN_RK3328(0, BIT(6), BIT(6), false), - [RK3328_PD_VIO] = DOMAIN_RK3328(0, BIT(8), BIT(8), false), - [RK3328_PD_VPU] = DOMAIN_RK3328(0, BIT(9), BIT(9), false), + [RK3328_PD_CORE] = DOMAIN_RK3328("core", 0, BIT(0), BIT(0), false), + [RK3328_PD_GPU] = DOMAIN_RK3328("gpu", 0, BIT(1), BIT(1), false), + [RK3328_PD_BUS] = DOMAIN_RK3328("bus", 0, BIT(2), BIT(2), true), + [RK3328_PD_MSCH] = DOMAIN_RK3328("msch", 0, BIT(3), BIT(3), true), + [RK3328_PD_PERI] = DOMAIN_RK3328("peri", 0, BIT(4), BIT(4), true), + [RK3328_PD_VIDEO] = DOMAIN_RK3328("video", 0, BIT(5), BIT(5), false), + [RK3328_PD_HEVC] = DOMAIN_RK3328("hevc", 0, BIT(6), BIT(6), false), + [RK3328_PD_VIO] = DOMAIN_RK3328("vio", 0, BIT(8), BIT(8), false), + [RK3328_PD_VPU] = DOMAIN_RK3328("vpu", 0, BIT(9), BIT(9), false), }; static const struct rockchip_domain_info rk3366_pm_domains[] = { - [RK3366_PD_PERI] = DOMAIN_RK3368(BIT(10), BIT(10), BIT(6), true), - [RK3366_PD_VIO] = DOMAIN_RK3368(BIT(14), BIT(14), BIT(8), false), - [RK3366_PD_VIDEO] = DOMAIN_RK3368(BIT(13), BIT(13), BIT(7), false), - [RK3366_PD_RKVDEC] = DOMAIN_RK3368(BIT(11), BIT(11), BIT(7), false), - [RK3366_PD_WIFIBT] = DOMAIN_RK3368(BIT(8), BIT(8), BIT(9), false), - [RK3366_PD_VPU] = DOMAIN_RK3368(BIT(12), BIT(12), BIT(7), false), - [RK3366_PD_GPU] = DOMAIN_RK3368(BIT(15), BIT(15), BIT(2), false), + [RK3366_PD_PERI] = DOMAIN_RK3368("peri", BIT(10), BIT(10), BIT(6), true), + [RK3366_PD_VIO] = DOMAIN_RK3368("vio", BIT(14), BIT(14), BIT(8), false), + [RK3366_PD_VIDEO] = DOMAIN_RK3368("video", BIT(13), BIT(13), BIT(7), false), + [RK3366_PD_RKVDEC] = DOMAIN_RK3368("vdec", BIT(11), BIT(11), BIT(7), false), + [RK3366_PD_WIFIBT] = DOMAIN_RK3368("wifibt", BIT(8), BIT(8), BIT(9), false), + [RK3366_PD_VPU] = DOMAIN_RK3368("vpu", BIT(12), BIT(12), BIT(7), false), + [RK3366_PD_GPU] = DOMAIN_RK3368("gpu", BIT(15), BIT(15), BIT(2), false), }; static const struct rockchip_domain_info rk3368_pm_domains[] = { - [RK3368_PD_PERI] = DOMAIN_RK3368(BIT(13), BIT(12), BIT(6), true), - [RK3368_PD_VIO] = DOMAIN_RK3368(BIT(15), BIT(14), BIT(8), false), - [RK3368_PD_VIDEO] = DOMAIN_RK3368(BIT(14), BIT(13), BIT(7), false), - [RK3368_PD_GPU_0] = DOMAIN_RK3368(BIT(16), BIT(15), BIT(2), false), - [RK3368_PD_GPU_1] = DOMAIN_RK3368(BIT(17), BIT(16), BIT(2), false), + [RK3368_PD_PERI] = DOMAIN_RK3368("peri", BIT(13), BIT(12), BIT(6), true), + [RK3368_PD_VIO] = DOMAIN_RK3368("vio", BIT(15), BIT(14), BIT(8), false), + [RK3368_PD_VIDEO] = DOMAIN_RK3368("video", BIT(14), BIT(13), BIT(7), false), + [RK3368_PD_GPU_0] = DOMAIN_RK3368("gpu_0", BIT(16), BIT(15), BIT(2), false), + [RK3368_PD_GPU_1] = DOMAIN_RK3368("gpu_1", BIT(17), BIT(16), BIT(2), false), }; static const struct rockchip_domain_info rk3399_pm_domains[] = { - [RK3399_PD_TCPD0] = DOMAIN_RK3399(BIT(8), BIT(8), 0, false), - [RK3399_PD_TCPD1] = DOMAIN_RK3399(BIT(9), BIT(9), 0, false), - [RK3399_PD_CCI] = DOMAIN_RK3399(BIT(10), BIT(10), 0, true), - [RK3399_PD_CCI0] = DOMAIN_RK3399(0, 0, BIT(15), true), - [RK3399_PD_CCI1] = DOMAIN_RK3399(0, 0, BIT(16), true), - [RK3399_PD_PERILP] = DOMAIN_RK3399(BIT(11), BIT(11), BIT(1), true), - [RK3399_PD_PERIHP] = DOMAIN_RK3399(BIT(12), BIT(12), BIT(2), true), - [RK3399_PD_CENTER] = DOMAIN_RK3399(BIT(13), BIT(13), BIT(14), true), - [RK3399_PD_VIO] = DOMAIN_RK3399(BIT(14), BIT(14), BIT(17), false), - [RK3399_PD_GPU] = DOMAIN_RK3399(BIT(15), BIT(15), BIT(0), false), - [RK3399_PD_VCODEC] = DOMAIN_RK3399(BIT(16), BIT(16), BIT(3), false), - [RK3399_PD_VDU] = DOMAIN_RK3399(BIT(17), BIT(17), BIT(4), false), - [RK3399_PD_RGA] = DOMAIN_RK3399(BIT(18), BIT(18), BIT(5), false), - [RK3399_PD_IEP] = DOMAIN_RK3399(BIT(19), BIT(19), BIT(6), false), - [RK3399_PD_VO] = DOMAIN_RK3399(BIT(20), BIT(20), 0, false), - [RK3399_PD_VOPB] = DOMAIN_RK3399(0, 0, BIT(7), false), - [RK3399_PD_VOPL] = DOMAIN_RK3399(0, 0, BIT(8), false), - [RK3399_PD_ISP0] = DOMAIN_RK3399(BIT(22), BIT(22), BIT(9), false), - [RK3399_PD_ISP1] = DOMAIN_RK3399(BIT(23), BIT(23), BIT(10), false), - [RK3399_PD_HDCP] = DOMAIN_RK3399(BIT(24), BIT(24), BIT(11), false), - [RK3399_PD_GMAC] = DOMAIN_RK3399(BIT(25), BIT(25), BIT(23), true), - [RK3399_PD_EMMC] = DOMAIN_RK3399(BIT(26), BIT(26), BIT(24), true), - [RK3399_PD_USB3] = DOMAIN_RK3399(BIT(27), BIT(27), BIT(12), true), - [RK3399_PD_EDP] = DOMAIN_RK3399(BIT(28), BIT(28), BIT(22), false), - [RK3399_PD_GIC] = DOMAIN_RK3399(BIT(29), BIT(29), BIT(27), true), - [RK3399_PD_SD] = DOMAIN_RK3399(BIT(30), BIT(30), BIT(28), true), - [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399(BIT(31), BIT(31), BIT(29), true), + [RK3399_PD_TCPD0] = DOMAIN_RK3399("tcpd0", BIT(8), BIT(8), 0, false), + [RK3399_PD_TCPD1] = DOMAIN_RK3399("tcpd1", BIT(9), BIT(9), 0, false), + [RK3399_PD_CCI] = DOMAIN_RK3399("cci", BIT(10), BIT(10), 0, true), + [RK3399_PD_CCI0] = DOMAIN_RK3399("cci0", 0, 0, BIT(15), true), + [RK3399_PD_CCI1] = DOMAIN_RK3399("cci1", 0, 0, BIT(16), true), + [RK3399_PD_PERILP] = DOMAIN_RK3399("perilp", BIT(11), BIT(11), BIT(1), true), + [RK3399_PD_PERIHP] = DOMAIN_RK3399("perihp", BIT(12), BIT(12), BIT(2), true), + [RK3399_PD_CENTER] = DOMAIN_RK3399("center", BIT(13), BIT(13), BIT(14), true), + [RK3399_PD_VIO] = DOMAIN_RK3399("vio", BIT(14), BIT(14), BIT(17), false), + [RK3399_PD_GPU] = DOMAIN_RK3399("gpu", BIT(15), BIT(15), BIT(0), false), + [RK3399_PD_VCODEC] = DOMAIN_RK3399("vcodec", BIT(16), BIT(16), BIT(3), false), + [RK3399_PD_VDU] = DOMAIN_RK3399("vdu", BIT(17), BIT(17), BIT(4), false), + [RK3399_PD_RGA] = DOMAIN_RK3399("rga", BIT(18), BIT(18), BIT(5), false), + [RK3399_PD_IEP] = DOMAIN_RK3399("iep", BIT(19), BIT(19), BIT(6), false), + [RK3399_PD_VO] = DOMAIN_RK3399("vo", BIT(20), BIT(20), 0, false), + [RK3399_PD_VOPB] = DOMAIN_RK3399("vopb", 0, 0, BIT(7), false), + [RK3399_PD_VOPL] = DOMAIN_RK3399("vopl", 0, 0, BIT(8), false), + [RK3399_PD_ISP0] = DOMAIN_RK3399("isp0", BIT(22), BIT(22), BIT(9), false), + [RK3399_PD_ISP1] = DOMAIN_RK3399("isp1", BIT(23), BIT(23), BIT(10), false), + [RK3399_PD_HDCP] = DOMAIN_RK3399("hdcp", BIT(24), BIT(24), BIT(11), false), + [RK3399_PD_GMAC] = DOMAIN_RK3399("gmac", BIT(25), BIT(25), BIT(23), true), + [RK3399_PD_EMMC] = DOMAIN_RK3399("emmc", BIT(26), BIT(26), BIT(24), true), + [RK3399_PD_USB3] = DOMAIN_RK3399("usb3", BIT(27), BIT(27), BIT(12), true), + [RK3399_PD_EDP] = DOMAIN_RK3399("edp", BIT(28), BIT(28), BIT(22), false), + [RK3399_PD_GIC] = DOMAIN_RK3399("gic", BIT(29), BIT(29), BIT(27), true), + [RK3399_PD_SD] = DOMAIN_RK3399("sd", BIT(30), BIT(30), BIT(28), true), + [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true), }; static const struct rockchip_pmu_info px30_pmu = { -- 2.17.1 ^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v5 07/11] soc: rockchip: pm-domains: Add a meaningful power domain name @ 2021-03-26 9:17 ` Elaine Zhang 0 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:17 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Add the power domains names to the power domain info struct so we have meaningful name for every power domain. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- drivers/soc/rockchip/pm_domains.c | 217 +++++++++++++++--------------- 1 file changed, 112 insertions(+), 105 deletions(-) diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c index 54eb6cfc5d5b..d661d967079f 100644 --- a/drivers/soc/rockchip/pm_domains.c +++ b/drivers/soc/rockchip/pm_domains.c @@ -29,6 +29,7 @@ #include <dt-bindings/power/rk3399-power.h> struct rockchip_domain_info { + const char *name; int pwr_mask; int status_mask; int req_mask; @@ -85,8 +86,9 @@ struct rockchip_pmu { #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd) -#define DOMAIN(pwr, status, req, idle, ack, wakeup) \ +#define DOMAIN(_name, pwr, status, req, idle, ack, wakeup) \ { \ + .name = _name, \ .pwr_mask = (pwr), \ .status_mask = (status), \ .req_mask = (req), \ @@ -95,8 +97,9 @@ struct rockchip_pmu { .active_wakeup = (wakeup), \ } -#define DOMAIN_M(pwr, status, req, idle, ack, wakeup) \ +#define DOMAIN_M(_name, pwr, status, req, idle, ack, wakeup) \ { \ + .name = _name, \ .pwr_w_mask = (pwr) << 16, \ .pwr_mask = (pwr), \ .status_mask = (status), \ @@ -107,8 +110,9 @@ struct rockchip_pmu { .active_wakeup = wakeup, \ } -#define DOMAIN_RK3036(req, ack, idle, wakeup) \ +#define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \ { \ + .name = _name, \ .req_mask = (req), \ .req_w_mask = (req) << 16, \ .ack_mask = (ack), \ @@ -119,17 +123,17 @@ struct rockchip_pmu { #define DOMAIN_PX30(pwr, status, req, wakeup) \ DOMAIN_M(pwr, status, req, (req) << 16, req, wakeup) -#define DOMAIN_RK3288(pwr, status, req, wakeup) \ - DOMAIN(pwr, status, req, req, (req) << 16, wakeup) +#define DOMAIN_RK3288(name, pwr, status, req, wakeup) \ + DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup) -#define DOMAIN_RK3328(pwr, status, req, wakeup) \ - DOMAIN_M(pwr, pwr, req, (req) << 10, req, wakeup) +#define DOMAIN_RK3328(name, pwr, status, req, wakeup) \ + DOMAIN_M(name, pwr, pwr, req, (req) << 10, req, wakeup) -#define DOMAIN_RK3368(pwr, status, req, wakeup) \ - DOMAIN(pwr, status, req, (req) << 16, req, wakeup) +#define DOMAIN_RK3368(name, pwr, status, req, wakeup) \ + DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup) -#define DOMAIN_RK3399(pwr, status, req, wakeup) \ - DOMAIN(pwr, status, req, req, req, wakeup) +#define DOMAIN_RK3399(name, pwr, status, req, wakeup) \ + DOMAIN(name, pwr, status, req, req, req, wakeup) static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd) { @@ -490,7 +494,10 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, goto err_unprepare_clocks; } - pd->genpd.name = node->name; + if (!pd->info->name) + pd->genpd.name = node->name; + else + pd->genpd.name = pd->info->name; pd->genpd.power_off = rockchip_pd_power_off; pd->genpd.power_on = rockchip_pd_power_on; pd->genpd.attach_dev = rockchip_pd_attach_dev; @@ -716,129 +723,129 @@ static int rockchip_pm_domain_probe(struct platform_device *pdev) } static const struct rockchip_domain_info px30_pm_domains[] = { - [PX30_PD_USB] = DOMAIN_PX30(BIT(5), BIT(5), BIT(10), false), - [PX30_PD_SDCARD] = DOMAIN_PX30(BIT(8), BIT(8), BIT(9), false), - [PX30_PD_GMAC] = DOMAIN_PX30(BIT(10), BIT(10), BIT(6), false), - [PX30_PD_MMC_NAND] = DOMAIN_PX30(BIT(11), BIT(11), BIT(5), false), - [PX30_PD_VPU] = DOMAIN_PX30(BIT(12), BIT(12), BIT(14), false), - [PX30_PD_VO] = DOMAIN_PX30(BIT(13), BIT(13), BIT(7), false), - [PX30_PD_VI] = DOMAIN_PX30(BIT(14), BIT(14), BIT(8), false), - [PX30_PD_GPU] = DOMAIN_PX30(BIT(15), BIT(15), BIT(2), false), + [PX30_PD_USB] = DOMAIN_PX30("usb", BIT(5), BIT(5), BIT(10), false), + [PX30_PD_SDCARD] = DOMAIN_PX30("sdcard", BIT(8), BIT(8), BIT(9), false), + [PX30_PD_GMAC] = DOMAIN_PX30("gmac", BIT(10), BIT(10), BIT(6), false), + [PX30_PD_MMC_NAND] = DOMAIN_PX30("mmc_nand", BIT(11), BIT(11), BIT(5), false), + [PX30_PD_VPU] = DOMAIN_PX30("vpu", BIT(12), BIT(12), BIT(14), false), + [PX30_PD_VO] = DOMAIN_PX30("vo", BIT(13), BIT(13), BIT(7), false), + [PX30_PD_VI] = DOMAIN_PX30("vi", BIT(14), BIT(14), BIT(8), false), + [PX30_PD_GPU] = DOMAIN_PX30("gpu", BIT(15), BIT(15), BIT(2), false), }; static const struct rockchip_domain_info rk3036_pm_domains[] = { - [RK3036_PD_MSCH] = DOMAIN_RK3036(BIT(14), BIT(23), BIT(30), true), - [RK3036_PD_CORE] = DOMAIN_RK3036(BIT(13), BIT(17), BIT(24), false), - [RK3036_PD_PERI] = DOMAIN_RK3036(BIT(12), BIT(18), BIT(25), false), - [RK3036_PD_VIO] = DOMAIN_RK3036(BIT(11), BIT(19), BIT(26), false), - [RK3036_PD_VPU] = DOMAIN_RK3036(BIT(10), BIT(20), BIT(27), false), - [RK3036_PD_GPU] = DOMAIN_RK3036(BIT(9), BIT(21), BIT(28), false), - [RK3036_PD_SYS] = DOMAIN_RK3036(BIT(8), BIT(22), BIT(29), false), + [RK3036_PD_MSCH] = DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true), + [RK3036_PD_CORE] = DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false), + [RK3036_PD_PERI] = DOMAIN_RK3036("peri", BIT(12), BIT(18), BIT(25), false), + [RK3036_PD_VIO] = DOMAIN_RK3036("vio", BIT(11), BIT(19), BIT(26), false), + [RK3036_PD_VPU] = DOMAIN_RK3036("vpu", BIT(10), BIT(20), BIT(27), false), + [RK3036_PD_GPU] = DOMAIN_RK3036("gpu", BIT(9), BIT(21), BIT(28), false), + [RK3036_PD_SYS] = DOMAIN_RK3036("sys", BIT(8), BIT(22), BIT(29), false), }; static const struct rockchip_domain_info rk3066_pm_domains[] = { - [RK3066_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), - [RK3066_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), - [RK3066_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), - [RK3066_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), - [RK3066_PD_CPU] = DOMAIN(0, BIT(5), BIT(1), BIT(26), BIT(31), false), + [RK3066_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), + [RK3066_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), + [RK3066_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), + [RK3066_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), + [RK3066_PD_CPU] = DOMAIN("cpu", 0, BIT(5), BIT(1), BIT(26), BIT(31), false), }; static const struct rockchip_domain_info rk3128_pm_domains[] = { - [RK3128_PD_CORE] = DOMAIN_RK3288(BIT(0), BIT(0), BIT(4), false), - [RK3128_PD_MSCH] = DOMAIN_RK3288(0, 0, BIT(6), true), - [RK3128_PD_VIO] = DOMAIN_RK3288(BIT(3), BIT(3), BIT(2), false), - [RK3128_PD_VIDEO] = DOMAIN_RK3288(BIT(2), BIT(2), BIT(1), false), - [RK3128_PD_GPU] = DOMAIN_RK3288(BIT(1), BIT(1), BIT(3), false), + [RK3128_PD_CORE] = DOMAIN_RK3288("core", BIT(0), BIT(0), BIT(4), false), + [RK3128_PD_MSCH] = DOMAIN_RK3288("msch", 0, 0, BIT(6), true), + [RK3128_PD_VIO] = DOMAIN_RK3288("vio", BIT(3), BIT(3), BIT(2), false), + [RK3128_PD_VIDEO] = DOMAIN_RK3288("video", BIT(2), BIT(2), BIT(1), false), + [RK3128_PD_GPU] = DOMAIN_RK3288("gpu", BIT(1), BIT(1), BIT(3), false), }; static const struct rockchip_domain_info rk3188_pm_domains[] = { - [RK3188_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), - [RK3188_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), - [RK3188_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), - [RK3188_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), - [RK3188_PD_CPU] = DOMAIN(BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false), + [RK3188_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), + [RK3188_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), + [RK3188_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), + [RK3188_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), + [RK3188_PD_CPU] = DOMAIN("cpu", BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false), }; static const struct rockchip_domain_info rk3228_pm_domains[] = { - [RK3228_PD_CORE] = DOMAIN_RK3036(BIT(0), BIT(0), BIT(16), true), - [RK3228_PD_MSCH] = DOMAIN_RK3036(BIT(1), BIT(1), BIT(17), true), - [RK3228_PD_BUS] = DOMAIN_RK3036(BIT(2), BIT(2), BIT(18), true), - [RK3228_PD_SYS] = DOMAIN_RK3036(BIT(3), BIT(3), BIT(19), true), - [RK3228_PD_VIO] = DOMAIN_RK3036(BIT(4), BIT(4), BIT(20), false), - [RK3228_PD_VOP] = DOMAIN_RK3036(BIT(5), BIT(5), BIT(21), false), - [RK3228_PD_VPU] = DOMAIN_RK3036(BIT(6), BIT(6), BIT(22), false), - [RK3228_PD_RKVDEC] = DOMAIN_RK3036(BIT(7), BIT(7), BIT(23), false), - [RK3228_PD_GPU] = DOMAIN_RK3036(BIT(8), BIT(8), BIT(24), false), - [RK3228_PD_PERI] = DOMAIN_RK3036(BIT(9), BIT(9), BIT(25), true), - [RK3228_PD_GMAC] = DOMAIN_RK3036(BIT(10), BIT(10), BIT(26), false), + [RK3228_PD_CORE] = DOMAIN_RK3036("core", BIT(0), BIT(0), BIT(16), true), + [RK3228_PD_MSCH] = DOMAIN_RK3036("msch", BIT(1), BIT(1), BIT(17), true), + [RK3228_PD_BUS] = DOMAIN_RK3036("bus", BIT(2), BIT(2), BIT(18), true), + [RK3228_PD_SYS] = DOMAIN_RK3036("sys", BIT(3), BIT(3), BIT(19), true), + [RK3228_PD_VIO] = DOMAIN_RK3036("vio", BIT(4), BIT(4), BIT(20), false), + [RK3228_PD_VOP] = DOMAIN_RK3036("vop", BIT(5), BIT(5), BIT(21), false), + [RK3228_PD_VPU] = DOMAIN_RK3036("vpu", BIT(6), BIT(6), BIT(22), false), + [RK3228_PD_RKVDEC] = DOMAIN_RK3036("vdec", BIT(7), BIT(7), BIT(23), false), + [RK3228_PD_GPU] = DOMAIN_RK3036("gpu", BIT(8), BIT(8), BIT(24), false), + [RK3228_PD_PERI] = DOMAIN_RK3036("peri", BIT(9), BIT(9), BIT(25), true), + [RK3228_PD_GMAC] = DOMAIN_RK3036("gmac", BIT(10), BIT(10), BIT(26), false), }; static const struct rockchip_domain_info rk3288_pm_domains[] = { - [RK3288_PD_VIO] = DOMAIN_RK3288(BIT(7), BIT(7), BIT(4), false), - [RK3288_PD_HEVC] = DOMAIN_RK3288(BIT(14), BIT(10), BIT(9), false), - [RK3288_PD_VIDEO] = DOMAIN_RK3288(BIT(8), BIT(8), BIT(3), false), - [RK3288_PD_GPU] = DOMAIN_RK3288(BIT(9), BIT(9), BIT(2), false), + [RK3288_PD_VIO] = DOMAIN_RK3288("vio", BIT(7), BIT(7), BIT(4), false), + [RK3288_PD_HEVC] = DOMAIN_RK3288("hevc", BIT(14), BIT(10), BIT(9), false), + [RK3288_PD_VIDEO] = DOMAIN_RK3288("video", BIT(8), BIT(8), BIT(3), false), + [RK3288_PD_GPU] = DOMAIN_RK3288("gpu", BIT(9), BIT(9), BIT(2), false), }; static const struct rockchip_domain_info rk3328_pm_domains[] = { - [RK3328_PD_CORE] = DOMAIN_RK3328(0, BIT(0), BIT(0), false), - [RK3328_PD_GPU] = DOMAIN_RK3328(0, BIT(1), BIT(1), false), - [RK3328_PD_BUS] = DOMAIN_RK3328(0, BIT(2), BIT(2), true), - [RK3328_PD_MSCH] = DOMAIN_RK3328(0, BIT(3), BIT(3), true), - [RK3328_PD_PERI] = DOMAIN_RK3328(0, BIT(4), BIT(4), true), - [RK3328_PD_VIDEO] = DOMAIN_RK3328(0, BIT(5), BIT(5), false), - [RK3328_PD_HEVC] = DOMAIN_RK3328(0, BIT(6), BIT(6), false), - [RK3328_PD_VIO] = DOMAIN_RK3328(0, BIT(8), BIT(8), false), - [RK3328_PD_VPU] = DOMAIN_RK3328(0, BIT(9), BIT(9), false), + [RK3328_PD_CORE] = DOMAIN_RK3328("core", 0, BIT(0), BIT(0), false), + [RK3328_PD_GPU] = DOMAIN_RK3328("gpu", 0, BIT(1), BIT(1), false), + [RK3328_PD_BUS] = DOMAIN_RK3328("bus", 0, BIT(2), BIT(2), true), + [RK3328_PD_MSCH] = DOMAIN_RK3328("msch", 0, BIT(3), BIT(3), true), + [RK3328_PD_PERI] = DOMAIN_RK3328("peri", 0, BIT(4), BIT(4), true), + [RK3328_PD_VIDEO] = DOMAIN_RK3328("video", 0, BIT(5), BIT(5), false), + [RK3328_PD_HEVC] = DOMAIN_RK3328("hevc", 0, BIT(6), BIT(6), false), + [RK3328_PD_VIO] = DOMAIN_RK3328("vio", 0, BIT(8), BIT(8), false), + [RK3328_PD_VPU] = DOMAIN_RK3328("vpu", 0, BIT(9), BIT(9), false), }; static const struct rockchip_domain_info rk3366_pm_domains[] = { - [RK3366_PD_PERI] = DOMAIN_RK3368(BIT(10), BIT(10), BIT(6), true), - [RK3366_PD_VIO] = DOMAIN_RK3368(BIT(14), BIT(14), BIT(8), false), - [RK3366_PD_VIDEO] = DOMAIN_RK3368(BIT(13), BIT(13), BIT(7), false), - [RK3366_PD_RKVDEC] = DOMAIN_RK3368(BIT(11), BIT(11), BIT(7), false), - [RK3366_PD_WIFIBT] = DOMAIN_RK3368(BIT(8), BIT(8), BIT(9), false), - [RK3366_PD_VPU] = DOMAIN_RK3368(BIT(12), BIT(12), BIT(7), false), - [RK3366_PD_GPU] = DOMAIN_RK3368(BIT(15), BIT(15), BIT(2), false), + [RK3366_PD_PERI] = DOMAIN_RK3368("peri", BIT(10), BIT(10), BIT(6), true), + [RK3366_PD_VIO] = DOMAIN_RK3368("vio", BIT(14), BIT(14), BIT(8), false), + [RK3366_PD_VIDEO] = DOMAIN_RK3368("video", BIT(13), BIT(13), BIT(7), false), + [RK3366_PD_RKVDEC] = DOMAIN_RK3368("vdec", BIT(11), BIT(11), BIT(7), false), + [RK3366_PD_WIFIBT] = DOMAIN_RK3368("wifibt", BIT(8), BIT(8), BIT(9), false), + [RK3366_PD_VPU] = DOMAIN_RK3368("vpu", BIT(12), BIT(12), BIT(7), false), + [RK3366_PD_GPU] = DOMAIN_RK3368("gpu", BIT(15), BIT(15), BIT(2), false), }; static const struct rockchip_domain_info rk3368_pm_domains[] = { - [RK3368_PD_PERI] = DOMAIN_RK3368(BIT(13), BIT(12), BIT(6), true), - [RK3368_PD_VIO] = DOMAIN_RK3368(BIT(15), BIT(14), BIT(8), false), - [RK3368_PD_VIDEO] = DOMAIN_RK3368(BIT(14), BIT(13), BIT(7), false), - [RK3368_PD_GPU_0] = DOMAIN_RK3368(BIT(16), BIT(15), BIT(2), false), - [RK3368_PD_GPU_1] = DOMAIN_RK3368(BIT(17), BIT(16), BIT(2), false), + [RK3368_PD_PERI] = DOMAIN_RK3368("peri", BIT(13), BIT(12), BIT(6), true), + [RK3368_PD_VIO] = DOMAIN_RK3368("vio", BIT(15), BIT(14), BIT(8), false), + [RK3368_PD_VIDEO] = DOMAIN_RK3368("video", BIT(14), BIT(13), BIT(7), false), + [RK3368_PD_GPU_0] = DOMAIN_RK3368("gpu_0", BIT(16), BIT(15), BIT(2), false), + [RK3368_PD_GPU_1] = DOMAIN_RK3368("gpu_1", BIT(17), BIT(16), BIT(2), false), }; static const struct rockchip_domain_info rk3399_pm_domains[] = { - [RK3399_PD_TCPD0] = DOMAIN_RK3399(BIT(8), BIT(8), 0, false), - [RK3399_PD_TCPD1] = DOMAIN_RK3399(BIT(9), BIT(9), 0, false), - [RK3399_PD_CCI] = DOMAIN_RK3399(BIT(10), BIT(10), 0, true), - [RK3399_PD_CCI0] = DOMAIN_RK3399(0, 0, BIT(15), true), - [RK3399_PD_CCI1] = DOMAIN_RK3399(0, 0, BIT(16), true), - [RK3399_PD_PERILP] = DOMAIN_RK3399(BIT(11), BIT(11), BIT(1), true), - [RK3399_PD_PERIHP] = DOMAIN_RK3399(BIT(12), BIT(12), BIT(2), true), - [RK3399_PD_CENTER] = DOMAIN_RK3399(BIT(13), BIT(13), BIT(14), true), - [RK3399_PD_VIO] = DOMAIN_RK3399(BIT(14), BIT(14), BIT(17), false), - [RK3399_PD_GPU] = DOMAIN_RK3399(BIT(15), BIT(15), BIT(0), false), - [RK3399_PD_VCODEC] = DOMAIN_RK3399(BIT(16), BIT(16), BIT(3), false), - [RK3399_PD_VDU] = DOMAIN_RK3399(BIT(17), BIT(17), BIT(4), false), - [RK3399_PD_RGA] = DOMAIN_RK3399(BIT(18), BIT(18), BIT(5), false), - [RK3399_PD_IEP] = DOMAIN_RK3399(BIT(19), BIT(19), BIT(6), false), - [RK3399_PD_VO] = DOMAIN_RK3399(BIT(20), BIT(20), 0, false), - [RK3399_PD_VOPB] = DOMAIN_RK3399(0, 0, BIT(7), false), - [RK3399_PD_VOPL] = DOMAIN_RK3399(0, 0, BIT(8), false), - [RK3399_PD_ISP0] = DOMAIN_RK3399(BIT(22), BIT(22), BIT(9), false), - [RK3399_PD_ISP1] = DOMAIN_RK3399(BIT(23), BIT(23), BIT(10), false), - [RK3399_PD_HDCP] = DOMAIN_RK3399(BIT(24), BIT(24), BIT(11), false), - [RK3399_PD_GMAC] = DOMAIN_RK3399(BIT(25), BIT(25), BIT(23), true), - [RK3399_PD_EMMC] = DOMAIN_RK3399(BIT(26), BIT(26), BIT(24), true), - [RK3399_PD_USB3] = DOMAIN_RK3399(BIT(27), BIT(27), BIT(12), true), - [RK3399_PD_EDP] = DOMAIN_RK3399(BIT(28), BIT(28), BIT(22), false), - [RK3399_PD_GIC] = DOMAIN_RK3399(BIT(29), BIT(29), BIT(27), true), - [RK3399_PD_SD] = DOMAIN_RK3399(BIT(30), BIT(30), BIT(28), true), - [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399(BIT(31), BIT(31), BIT(29), true), + [RK3399_PD_TCPD0] = DOMAIN_RK3399("tcpd0", BIT(8), BIT(8), 0, false), + [RK3399_PD_TCPD1] = DOMAIN_RK3399("tcpd1", BIT(9), BIT(9), 0, false), + [RK3399_PD_CCI] = DOMAIN_RK3399("cci", BIT(10), BIT(10), 0, true), + [RK3399_PD_CCI0] = DOMAIN_RK3399("cci0", 0, 0, BIT(15), true), + [RK3399_PD_CCI1] = DOMAIN_RK3399("cci1", 0, 0, BIT(16), true), + [RK3399_PD_PERILP] = DOMAIN_RK3399("perilp", BIT(11), BIT(11), BIT(1), true), + [RK3399_PD_PERIHP] = DOMAIN_RK3399("perihp", BIT(12), BIT(12), BIT(2), true), + [RK3399_PD_CENTER] = DOMAIN_RK3399("center", BIT(13), BIT(13), BIT(14), true), + [RK3399_PD_VIO] = DOMAIN_RK3399("vio", BIT(14), BIT(14), BIT(17), false), + [RK3399_PD_GPU] = DOMAIN_RK3399("gpu", BIT(15), BIT(15), BIT(0), false), + [RK3399_PD_VCODEC] = DOMAIN_RK3399("vcodec", BIT(16), BIT(16), BIT(3), false), + [RK3399_PD_VDU] = DOMAIN_RK3399("vdu", BIT(17), BIT(17), BIT(4), false), + [RK3399_PD_RGA] = DOMAIN_RK3399("rga", BIT(18), BIT(18), BIT(5), false), + [RK3399_PD_IEP] = DOMAIN_RK3399("iep", BIT(19), BIT(19), BIT(6), false), + [RK3399_PD_VO] = DOMAIN_RK3399("vo", BIT(20), BIT(20), 0, false), + [RK3399_PD_VOPB] = DOMAIN_RK3399("vopb", 0, 0, BIT(7), false), + [RK3399_PD_VOPL] = DOMAIN_RK3399("vopl", 0, 0, BIT(8), false), + [RK3399_PD_ISP0] = DOMAIN_RK3399("isp0", BIT(22), BIT(22), BIT(9), false), + [RK3399_PD_ISP1] = DOMAIN_RK3399("isp1", BIT(23), BIT(23), BIT(10), false), + [RK3399_PD_HDCP] = DOMAIN_RK3399("hdcp", BIT(24), BIT(24), BIT(11), false), + [RK3399_PD_GMAC] = DOMAIN_RK3399("gmac", BIT(25), BIT(25), BIT(23), true), + [RK3399_PD_EMMC] = DOMAIN_RK3399("emmc", BIT(26), BIT(26), BIT(24), true), + [RK3399_PD_USB3] = DOMAIN_RK3399("usb3", BIT(27), BIT(27), BIT(12), true), + [RK3399_PD_EDP] = DOMAIN_RK3399("edp", BIT(28), BIT(28), BIT(22), false), + [RK3399_PD_GIC] = DOMAIN_RK3399("gic", BIT(29), BIT(29), BIT(27), true), + [RK3399_PD_SD] = DOMAIN_RK3399("sd", BIT(30), BIT(30), BIT(28), true), + [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true), }; static const struct rockchip_pmu_info px30_pmu = { -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 75+ messages in thread
* Re: [PATCH v5 07/11] soc: rockchip: pm-domains: Add a meaningful power domain name 2021-03-26 9:17 ` Elaine Zhang (?) @ 2021-03-26 9:49 ` Heiko Stübner -1 siblings, 0 replies; 75+ messages in thread From: Heiko Stübner @ 2021-03-26 9:49 UTC (permalink / raw) To: robh+dt, Elaine Zhang Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Hi Elaine, Am Freitag, 26. März 2021, 10:17:39 CET schrieb Elaine Zhang: > Add the power domains names to the power domain info struct so we > have meaningful name for every power domain. > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> I like that approach very much, there is one tiny comment below. > --- > drivers/soc/rockchip/pm_domains.c | 217 +++++++++++++++--------------- > 1 file changed, 112 insertions(+), 105 deletions(-) > > diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c > index 54eb6cfc5d5b..d661d967079f 100644 > --- a/drivers/soc/rockchip/pm_domains.c > +++ b/drivers/soc/rockchip/pm_domains.c > @@ -29,6 +29,7 @@ > #include <dt-bindings/power/rk3399-power.h> > > struct rockchip_domain_info { > + const char *name; > int pwr_mask; > int status_mask; > int req_mask; > @@ -85,8 +86,9 @@ struct rockchip_pmu { > > #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd) > > -#define DOMAIN(pwr, status, req, idle, ack, wakeup) \ > +#define DOMAIN(_name, pwr, status, req, idle, ack, wakeup) \ > { \ > + .name = _name, \ > .pwr_mask = (pwr), \ > .status_mask = (status), \ > .req_mask = (req), \ > @@ -95,8 +97,9 @@ struct rockchip_pmu { > .active_wakeup = (wakeup), \ > } > > -#define DOMAIN_M(pwr, status, req, idle, ack, wakeup) \ > +#define DOMAIN_M(_name, pwr, status, req, idle, ack, wakeup) \ > { \ > + .name = _name, \ > .pwr_w_mask = (pwr) << 16, \ > .pwr_mask = (pwr), \ > .status_mask = (status), \ > @@ -107,8 +110,9 @@ struct rockchip_pmu { > .active_wakeup = wakeup, \ > } > > -#define DOMAIN_RK3036(req, ack, idle, wakeup) \ > +#define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \ > { \ > + .name = _name, \ > .req_mask = (req), \ > .req_w_mask = (req) << 16, \ > .ack_mask = (ack), \ > @@ -119,17 +123,17 @@ struct rockchip_pmu { > #define DOMAIN_PX30(pwr, status, req, wakeup) \ > DOMAIN_M(pwr, status, req, (req) << 16, req, wakeup) > > -#define DOMAIN_RK3288(pwr, status, req, wakeup) \ > - DOMAIN(pwr, status, req, req, (req) << 16, wakeup) > +#define DOMAIN_RK3288(name, pwr, status, req, wakeup) \ > + DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup) > > -#define DOMAIN_RK3328(pwr, status, req, wakeup) \ > - DOMAIN_M(pwr, pwr, req, (req) << 10, req, wakeup) > +#define DOMAIN_RK3328(name, pwr, status, req, wakeup) \ > + DOMAIN_M(name, pwr, pwr, req, (req) << 10, req, wakeup) > > -#define DOMAIN_RK3368(pwr, status, req, wakeup) \ > - DOMAIN(pwr, status, req, (req) << 16, req, wakeup) > +#define DOMAIN_RK3368(name, pwr, status, req, wakeup) \ > + DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup) > > -#define DOMAIN_RK3399(pwr, status, req, wakeup) \ > - DOMAIN(pwr, status, req, req, req, wakeup) > +#define DOMAIN_RK3399(name, pwr, status, req, wakeup) \ > + DOMAIN(name, pwr, status, req, req, req, wakeup) > > static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd) > { > @@ -490,7 +494,10 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, > goto err_unprepare_clocks; > } > > - pd->genpd.name = node->name; > + if (!pd->info->name) > + pd->genpd.name = node->name; I guess we should make that "node->full_name" perhaps? And I guess it might be nicer to swap the cases if (pd->info->name) pd->genpd.name = pd->info->name else pd->genpd.name = node->full_name; for easier readability Heiko > + else > + pd->genpd.name = pd->info->name; > pd->genpd.power_off = rockchip_pd_power_off; > pd->genpd.power_on = rockchip_pd_power_on; > pd->genpd.attach_dev = rockchip_pd_attach_dev; > @@ -716,129 +723,129 @@ static int rockchip_pm_domain_probe(struct platform_device *pdev) > } > > static const struct rockchip_domain_info px30_pm_domains[] = { > - [PX30_PD_USB] = DOMAIN_PX30(BIT(5), BIT(5), BIT(10), false), > - [PX30_PD_SDCARD] = DOMAIN_PX30(BIT(8), BIT(8), BIT(9), false), > - [PX30_PD_GMAC] = DOMAIN_PX30(BIT(10), BIT(10), BIT(6), false), > - [PX30_PD_MMC_NAND] = DOMAIN_PX30(BIT(11), BIT(11), BIT(5), false), > - [PX30_PD_VPU] = DOMAIN_PX30(BIT(12), BIT(12), BIT(14), false), > - [PX30_PD_VO] = DOMAIN_PX30(BIT(13), BIT(13), BIT(7), false), > - [PX30_PD_VI] = DOMAIN_PX30(BIT(14), BIT(14), BIT(8), false), > - [PX30_PD_GPU] = DOMAIN_PX30(BIT(15), BIT(15), BIT(2), false), > + [PX30_PD_USB] = DOMAIN_PX30("usb", BIT(5), BIT(5), BIT(10), false), > + [PX30_PD_SDCARD] = DOMAIN_PX30("sdcard", BIT(8), BIT(8), BIT(9), false), > + [PX30_PD_GMAC] = DOMAIN_PX30("gmac", BIT(10), BIT(10), BIT(6), false), > + [PX30_PD_MMC_NAND] = DOMAIN_PX30("mmc_nand", BIT(11), BIT(11), BIT(5), false), > + [PX30_PD_VPU] = DOMAIN_PX30("vpu", BIT(12), BIT(12), BIT(14), false), > + [PX30_PD_VO] = DOMAIN_PX30("vo", BIT(13), BIT(13), BIT(7), false), > + [PX30_PD_VI] = DOMAIN_PX30("vi", BIT(14), BIT(14), BIT(8), false), > + [PX30_PD_GPU] = DOMAIN_PX30("gpu", BIT(15), BIT(15), BIT(2), false), > }; > > static const struct rockchip_domain_info rk3036_pm_domains[] = { > - [RK3036_PD_MSCH] = DOMAIN_RK3036(BIT(14), BIT(23), BIT(30), true), > - [RK3036_PD_CORE] = DOMAIN_RK3036(BIT(13), BIT(17), BIT(24), false), > - [RK3036_PD_PERI] = DOMAIN_RK3036(BIT(12), BIT(18), BIT(25), false), > - [RK3036_PD_VIO] = DOMAIN_RK3036(BIT(11), BIT(19), BIT(26), false), > - [RK3036_PD_VPU] = DOMAIN_RK3036(BIT(10), BIT(20), BIT(27), false), > - [RK3036_PD_GPU] = DOMAIN_RK3036(BIT(9), BIT(21), BIT(28), false), > - [RK3036_PD_SYS] = DOMAIN_RK3036(BIT(8), BIT(22), BIT(29), false), > + [RK3036_PD_MSCH] = DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true), > + [RK3036_PD_CORE] = DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false), > + [RK3036_PD_PERI] = DOMAIN_RK3036("peri", BIT(12), BIT(18), BIT(25), false), > + [RK3036_PD_VIO] = DOMAIN_RK3036("vio", BIT(11), BIT(19), BIT(26), false), > + [RK3036_PD_VPU] = DOMAIN_RK3036("vpu", BIT(10), BIT(20), BIT(27), false), > + [RK3036_PD_GPU] = DOMAIN_RK3036("gpu", BIT(9), BIT(21), BIT(28), false), > + [RK3036_PD_SYS] = DOMAIN_RK3036("sys", BIT(8), BIT(22), BIT(29), false), > }; > > static const struct rockchip_domain_info rk3066_pm_domains[] = { > - [RK3066_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > - [RK3066_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > - [RK3066_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > - [RK3066_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > - [RK3066_PD_CPU] = DOMAIN(0, BIT(5), BIT(1), BIT(26), BIT(31), false), > + [RK3066_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > + [RK3066_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > + [RK3066_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > + [RK3066_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > + [RK3066_PD_CPU] = DOMAIN("cpu", 0, BIT(5), BIT(1), BIT(26), BIT(31), false), > }; > > static const struct rockchip_domain_info rk3128_pm_domains[] = { > - [RK3128_PD_CORE] = DOMAIN_RK3288(BIT(0), BIT(0), BIT(4), false), > - [RK3128_PD_MSCH] = DOMAIN_RK3288(0, 0, BIT(6), true), > - [RK3128_PD_VIO] = DOMAIN_RK3288(BIT(3), BIT(3), BIT(2), false), > - [RK3128_PD_VIDEO] = DOMAIN_RK3288(BIT(2), BIT(2), BIT(1), false), > - [RK3128_PD_GPU] = DOMAIN_RK3288(BIT(1), BIT(1), BIT(3), false), > + [RK3128_PD_CORE] = DOMAIN_RK3288("core", BIT(0), BIT(0), BIT(4), false), > + [RK3128_PD_MSCH] = DOMAIN_RK3288("msch", 0, 0, BIT(6), true), > + [RK3128_PD_VIO] = DOMAIN_RK3288("vio", BIT(3), BIT(3), BIT(2), false), > + [RK3128_PD_VIDEO] = DOMAIN_RK3288("video", BIT(2), BIT(2), BIT(1), false), > + [RK3128_PD_GPU] = DOMAIN_RK3288("gpu", BIT(1), BIT(1), BIT(3), false), > }; > > static const struct rockchip_domain_info rk3188_pm_domains[] = { > - [RK3188_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > - [RK3188_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > - [RK3188_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > - [RK3188_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > - [RK3188_PD_CPU] = DOMAIN(BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false), > + [RK3188_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > + [RK3188_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > + [RK3188_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > + [RK3188_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > + [RK3188_PD_CPU] = DOMAIN("cpu", BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false), > }; > > static const struct rockchip_domain_info rk3228_pm_domains[] = { > - [RK3228_PD_CORE] = DOMAIN_RK3036(BIT(0), BIT(0), BIT(16), true), > - [RK3228_PD_MSCH] = DOMAIN_RK3036(BIT(1), BIT(1), BIT(17), true), > - [RK3228_PD_BUS] = DOMAIN_RK3036(BIT(2), BIT(2), BIT(18), true), > - [RK3228_PD_SYS] = DOMAIN_RK3036(BIT(3), BIT(3), BIT(19), true), > - [RK3228_PD_VIO] = DOMAIN_RK3036(BIT(4), BIT(4), BIT(20), false), > - [RK3228_PD_VOP] = DOMAIN_RK3036(BIT(5), BIT(5), BIT(21), false), > - [RK3228_PD_VPU] = DOMAIN_RK3036(BIT(6), BIT(6), BIT(22), false), > - [RK3228_PD_RKVDEC] = DOMAIN_RK3036(BIT(7), BIT(7), BIT(23), false), > - [RK3228_PD_GPU] = DOMAIN_RK3036(BIT(8), BIT(8), BIT(24), false), > - [RK3228_PD_PERI] = DOMAIN_RK3036(BIT(9), BIT(9), BIT(25), true), > - [RK3228_PD_GMAC] = DOMAIN_RK3036(BIT(10), BIT(10), BIT(26), false), > + [RK3228_PD_CORE] = DOMAIN_RK3036("core", BIT(0), BIT(0), BIT(16), true), > + [RK3228_PD_MSCH] = DOMAIN_RK3036("msch", BIT(1), BIT(1), BIT(17), true), > + [RK3228_PD_BUS] = DOMAIN_RK3036("bus", BIT(2), BIT(2), BIT(18), true), > + [RK3228_PD_SYS] = DOMAIN_RK3036("sys", BIT(3), BIT(3), BIT(19), true), > + [RK3228_PD_VIO] = DOMAIN_RK3036("vio", BIT(4), BIT(4), BIT(20), false), > + [RK3228_PD_VOP] = DOMAIN_RK3036("vop", BIT(5), BIT(5), BIT(21), false), > + [RK3228_PD_VPU] = DOMAIN_RK3036("vpu", BIT(6), BIT(6), BIT(22), false), > + [RK3228_PD_RKVDEC] = DOMAIN_RK3036("vdec", BIT(7), BIT(7), BIT(23), false), > + [RK3228_PD_GPU] = DOMAIN_RK3036("gpu", BIT(8), BIT(8), BIT(24), false), > + [RK3228_PD_PERI] = DOMAIN_RK3036("peri", BIT(9), BIT(9), BIT(25), true), > + [RK3228_PD_GMAC] = DOMAIN_RK3036("gmac", BIT(10), BIT(10), BIT(26), false), > }; > > static const struct rockchip_domain_info rk3288_pm_domains[] = { > - [RK3288_PD_VIO] = DOMAIN_RK3288(BIT(7), BIT(7), BIT(4), false), > - [RK3288_PD_HEVC] = DOMAIN_RK3288(BIT(14), BIT(10), BIT(9), false), > - [RK3288_PD_VIDEO] = DOMAIN_RK3288(BIT(8), BIT(8), BIT(3), false), > - [RK3288_PD_GPU] = DOMAIN_RK3288(BIT(9), BIT(9), BIT(2), false), > + [RK3288_PD_VIO] = DOMAIN_RK3288("vio", BIT(7), BIT(7), BIT(4), false), > + [RK3288_PD_HEVC] = DOMAIN_RK3288("hevc", BIT(14), BIT(10), BIT(9), false), > + [RK3288_PD_VIDEO] = DOMAIN_RK3288("video", BIT(8), BIT(8), BIT(3), false), > + [RK3288_PD_GPU] = DOMAIN_RK3288("gpu", BIT(9), BIT(9), BIT(2), false), > }; > > static const struct rockchip_domain_info rk3328_pm_domains[] = { > - [RK3328_PD_CORE] = DOMAIN_RK3328(0, BIT(0), BIT(0), false), > - [RK3328_PD_GPU] = DOMAIN_RK3328(0, BIT(1), BIT(1), false), > - [RK3328_PD_BUS] = DOMAIN_RK3328(0, BIT(2), BIT(2), true), > - [RK3328_PD_MSCH] = DOMAIN_RK3328(0, BIT(3), BIT(3), true), > - [RK3328_PD_PERI] = DOMAIN_RK3328(0, BIT(4), BIT(4), true), > - [RK3328_PD_VIDEO] = DOMAIN_RK3328(0, BIT(5), BIT(5), false), > - [RK3328_PD_HEVC] = DOMAIN_RK3328(0, BIT(6), BIT(6), false), > - [RK3328_PD_VIO] = DOMAIN_RK3328(0, BIT(8), BIT(8), false), > - [RK3328_PD_VPU] = DOMAIN_RK3328(0, BIT(9), BIT(9), false), > + [RK3328_PD_CORE] = DOMAIN_RK3328("core", 0, BIT(0), BIT(0), false), > + [RK3328_PD_GPU] = DOMAIN_RK3328("gpu", 0, BIT(1), BIT(1), false), > + [RK3328_PD_BUS] = DOMAIN_RK3328("bus", 0, BIT(2), BIT(2), true), > + [RK3328_PD_MSCH] = DOMAIN_RK3328("msch", 0, BIT(3), BIT(3), true), > + [RK3328_PD_PERI] = DOMAIN_RK3328("peri", 0, BIT(4), BIT(4), true), > + [RK3328_PD_VIDEO] = DOMAIN_RK3328("video", 0, BIT(5), BIT(5), false), > + [RK3328_PD_HEVC] = DOMAIN_RK3328("hevc", 0, BIT(6), BIT(6), false), > + [RK3328_PD_VIO] = DOMAIN_RK3328("vio", 0, BIT(8), BIT(8), false), > + [RK3328_PD_VPU] = DOMAIN_RK3328("vpu", 0, BIT(9), BIT(9), false), > }; > > static const struct rockchip_domain_info rk3366_pm_domains[] = { > - [RK3366_PD_PERI] = DOMAIN_RK3368(BIT(10), BIT(10), BIT(6), true), > - [RK3366_PD_VIO] = DOMAIN_RK3368(BIT(14), BIT(14), BIT(8), false), > - [RK3366_PD_VIDEO] = DOMAIN_RK3368(BIT(13), BIT(13), BIT(7), false), > - [RK3366_PD_RKVDEC] = DOMAIN_RK3368(BIT(11), BIT(11), BIT(7), false), > - [RK3366_PD_WIFIBT] = DOMAIN_RK3368(BIT(8), BIT(8), BIT(9), false), > - [RK3366_PD_VPU] = DOMAIN_RK3368(BIT(12), BIT(12), BIT(7), false), > - [RK3366_PD_GPU] = DOMAIN_RK3368(BIT(15), BIT(15), BIT(2), false), > + [RK3366_PD_PERI] = DOMAIN_RK3368("peri", BIT(10), BIT(10), BIT(6), true), > + [RK3366_PD_VIO] = DOMAIN_RK3368("vio", BIT(14), BIT(14), BIT(8), false), > + [RK3366_PD_VIDEO] = DOMAIN_RK3368("video", BIT(13), BIT(13), BIT(7), false), > + [RK3366_PD_RKVDEC] = DOMAIN_RK3368("vdec", BIT(11), BIT(11), BIT(7), false), > + [RK3366_PD_WIFIBT] = DOMAIN_RK3368("wifibt", BIT(8), BIT(8), BIT(9), false), > + [RK3366_PD_VPU] = DOMAIN_RK3368("vpu", BIT(12), BIT(12), BIT(7), false), > + [RK3366_PD_GPU] = DOMAIN_RK3368("gpu", BIT(15), BIT(15), BIT(2), false), > }; > > static const struct rockchip_domain_info rk3368_pm_domains[] = { > - [RK3368_PD_PERI] = DOMAIN_RK3368(BIT(13), BIT(12), BIT(6), true), > - [RK3368_PD_VIO] = DOMAIN_RK3368(BIT(15), BIT(14), BIT(8), false), > - [RK3368_PD_VIDEO] = DOMAIN_RK3368(BIT(14), BIT(13), BIT(7), false), > - [RK3368_PD_GPU_0] = DOMAIN_RK3368(BIT(16), BIT(15), BIT(2), false), > - [RK3368_PD_GPU_1] = DOMAIN_RK3368(BIT(17), BIT(16), BIT(2), false), > + [RK3368_PD_PERI] = DOMAIN_RK3368("peri", BIT(13), BIT(12), BIT(6), true), > + [RK3368_PD_VIO] = DOMAIN_RK3368("vio", BIT(15), BIT(14), BIT(8), false), > + [RK3368_PD_VIDEO] = DOMAIN_RK3368("video", BIT(14), BIT(13), BIT(7), false), > + [RK3368_PD_GPU_0] = DOMAIN_RK3368("gpu_0", BIT(16), BIT(15), BIT(2), false), > + [RK3368_PD_GPU_1] = DOMAIN_RK3368("gpu_1", BIT(17), BIT(16), BIT(2), false), > }; > > static const struct rockchip_domain_info rk3399_pm_domains[] = { > - [RK3399_PD_TCPD0] = DOMAIN_RK3399(BIT(8), BIT(8), 0, false), > - [RK3399_PD_TCPD1] = DOMAIN_RK3399(BIT(9), BIT(9), 0, false), > - [RK3399_PD_CCI] = DOMAIN_RK3399(BIT(10), BIT(10), 0, true), > - [RK3399_PD_CCI0] = DOMAIN_RK3399(0, 0, BIT(15), true), > - [RK3399_PD_CCI1] = DOMAIN_RK3399(0, 0, BIT(16), true), > - [RK3399_PD_PERILP] = DOMAIN_RK3399(BIT(11), BIT(11), BIT(1), true), > - [RK3399_PD_PERIHP] = DOMAIN_RK3399(BIT(12), BIT(12), BIT(2), true), > - [RK3399_PD_CENTER] = DOMAIN_RK3399(BIT(13), BIT(13), BIT(14), true), > - [RK3399_PD_VIO] = DOMAIN_RK3399(BIT(14), BIT(14), BIT(17), false), > - [RK3399_PD_GPU] = DOMAIN_RK3399(BIT(15), BIT(15), BIT(0), false), > - [RK3399_PD_VCODEC] = DOMAIN_RK3399(BIT(16), BIT(16), BIT(3), false), > - [RK3399_PD_VDU] = DOMAIN_RK3399(BIT(17), BIT(17), BIT(4), false), > - [RK3399_PD_RGA] = DOMAIN_RK3399(BIT(18), BIT(18), BIT(5), false), > - [RK3399_PD_IEP] = DOMAIN_RK3399(BIT(19), BIT(19), BIT(6), false), > - [RK3399_PD_VO] = DOMAIN_RK3399(BIT(20), BIT(20), 0, false), > - [RK3399_PD_VOPB] = DOMAIN_RK3399(0, 0, BIT(7), false), > - [RK3399_PD_VOPL] = DOMAIN_RK3399(0, 0, BIT(8), false), > - [RK3399_PD_ISP0] = DOMAIN_RK3399(BIT(22), BIT(22), BIT(9), false), > - [RK3399_PD_ISP1] = DOMAIN_RK3399(BIT(23), BIT(23), BIT(10), false), > - [RK3399_PD_HDCP] = DOMAIN_RK3399(BIT(24), BIT(24), BIT(11), false), > - [RK3399_PD_GMAC] = DOMAIN_RK3399(BIT(25), BIT(25), BIT(23), true), > - [RK3399_PD_EMMC] = DOMAIN_RK3399(BIT(26), BIT(26), BIT(24), true), > - [RK3399_PD_USB3] = DOMAIN_RK3399(BIT(27), BIT(27), BIT(12), true), > - [RK3399_PD_EDP] = DOMAIN_RK3399(BIT(28), BIT(28), BIT(22), false), > - [RK3399_PD_GIC] = DOMAIN_RK3399(BIT(29), BIT(29), BIT(27), true), > - [RK3399_PD_SD] = DOMAIN_RK3399(BIT(30), BIT(30), BIT(28), true), > - [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399(BIT(31), BIT(31), BIT(29), true), > + [RK3399_PD_TCPD0] = DOMAIN_RK3399("tcpd0", BIT(8), BIT(8), 0, false), > + [RK3399_PD_TCPD1] = DOMAIN_RK3399("tcpd1", BIT(9), BIT(9), 0, false), > + [RK3399_PD_CCI] = DOMAIN_RK3399("cci", BIT(10), BIT(10), 0, true), > + [RK3399_PD_CCI0] = DOMAIN_RK3399("cci0", 0, 0, BIT(15), true), > + [RK3399_PD_CCI1] = DOMAIN_RK3399("cci1", 0, 0, BIT(16), true), > + [RK3399_PD_PERILP] = DOMAIN_RK3399("perilp", BIT(11), BIT(11), BIT(1), true), > + [RK3399_PD_PERIHP] = DOMAIN_RK3399("perihp", BIT(12), BIT(12), BIT(2), true), > + [RK3399_PD_CENTER] = DOMAIN_RK3399("center", BIT(13), BIT(13), BIT(14), true), > + [RK3399_PD_VIO] = DOMAIN_RK3399("vio", BIT(14), BIT(14), BIT(17), false), > + [RK3399_PD_GPU] = DOMAIN_RK3399("gpu", BIT(15), BIT(15), BIT(0), false), > + [RK3399_PD_VCODEC] = DOMAIN_RK3399("vcodec", BIT(16), BIT(16), BIT(3), false), > + [RK3399_PD_VDU] = DOMAIN_RK3399("vdu", BIT(17), BIT(17), BIT(4), false), > + [RK3399_PD_RGA] = DOMAIN_RK3399("rga", BIT(18), BIT(18), BIT(5), false), > + [RK3399_PD_IEP] = DOMAIN_RK3399("iep", BIT(19), BIT(19), BIT(6), false), > + [RK3399_PD_VO] = DOMAIN_RK3399("vo", BIT(20), BIT(20), 0, false), > + [RK3399_PD_VOPB] = DOMAIN_RK3399("vopb", 0, 0, BIT(7), false), > + [RK3399_PD_VOPL] = DOMAIN_RK3399("vopl", 0, 0, BIT(8), false), > + [RK3399_PD_ISP0] = DOMAIN_RK3399("isp0", BIT(22), BIT(22), BIT(9), false), > + [RK3399_PD_ISP1] = DOMAIN_RK3399("isp1", BIT(23), BIT(23), BIT(10), false), > + [RK3399_PD_HDCP] = DOMAIN_RK3399("hdcp", BIT(24), BIT(24), BIT(11), false), > + [RK3399_PD_GMAC] = DOMAIN_RK3399("gmac", BIT(25), BIT(25), BIT(23), true), > + [RK3399_PD_EMMC] = DOMAIN_RK3399("emmc", BIT(26), BIT(26), BIT(24), true), > + [RK3399_PD_USB3] = DOMAIN_RK3399("usb3", BIT(27), BIT(27), BIT(12), true), > + [RK3399_PD_EDP] = DOMAIN_RK3399("edp", BIT(28), BIT(28), BIT(22), false), > + [RK3399_PD_GIC] = DOMAIN_RK3399("gic", BIT(29), BIT(29), BIT(27), true), > + [RK3399_PD_SD] = DOMAIN_RK3399("sd", BIT(30), BIT(30), BIT(28), true), > + [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true), > }; > > static const struct rockchip_pmu_info px30_pmu = { > _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v5 07/11] soc: rockchip: pm-domains: Add a meaningful power domain name @ 2021-03-26 9:49 ` Heiko Stübner 0 siblings, 0 replies; 75+ messages in thread From: Heiko Stübner @ 2021-03-26 9:49 UTC (permalink / raw) To: robh+dt, Elaine Zhang Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Hi Elaine, Am Freitag, 26. März 2021, 10:17:39 CET schrieb Elaine Zhang: > Add the power domains names to the power domain info struct so we > have meaningful name for every power domain. > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> I like that approach very much, there is one tiny comment below. > --- > drivers/soc/rockchip/pm_domains.c | 217 +++++++++++++++--------------- > 1 file changed, 112 insertions(+), 105 deletions(-) > > diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c > index 54eb6cfc5d5b..d661d967079f 100644 > --- a/drivers/soc/rockchip/pm_domains.c > +++ b/drivers/soc/rockchip/pm_domains.c > @@ -29,6 +29,7 @@ > #include <dt-bindings/power/rk3399-power.h> > > struct rockchip_domain_info { > + const char *name; > int pwr_mask; > int status_mask; > int req_mask; > @@ -85,8 +86,9 @@ struct rockchip_pmu { > > #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd) > > -#define DOMAIN(pwr, status, req, idle, ack, wakeup) \ > +#define DOMAIN(_name, pwr, status, req, idle, ack, wakeup) \ > { \ > + .name = _name, \ > .pwr_mask = (pwr), \ > .status_mask = (status), \ > .req_mask = (req), \ > @@ -95,8 +97,9 @@ struct rockchip_pmu { > .active_wakeup = (wakeup), \ > } > > -#define DOMAIN_M(pwr, status, req, idle, ack, wakeup) \ > +#define DOMAIN_M(_name, pwr, status, req, idle, ack, wakeup) \ > { \ > + .name = _name, \ > .pwr_w_mask = (pwr) << 16, \ > .pwr_mask = (pwr), \ > .status_mask = (status), \ > @@ -107,8 +110,9 @@ struct rockchip_pmu { > .active_wakeup = wakeup, \ > } > > -#define DOMAIN_RK3036(req, ack, idle, wakeup) \ > +#define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \ > { \ > + .name = _name, \ > .req_mask = (req), \ > .req_w_mask = (req) << 16, \ > .ack_mask = (ack), \ > @@ -119,17 +123,17 @@ struct rockchip_pmu { > #define DOMAIN_PX30(pwr, status, req, wakeup) \ > DOMAIN_M(pwr, status, req, (req) << 16, req, wakeup) > > -#define DOMAIN_RK3288(pwr, status, req, wakeup) \ > - DOMAIN(pwr, status, req, req, (req) << 16, wakeup) > +#define DOMAIN_RK3288(name, pwr, status, req, wakeup) \ > + DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup) > > -#define DOMAIN_RK3328(pwr, status, req, wakeup) \ > - DOMAIN_M(pwr, pwr, req, (req) << 10, req, wakeup) > +#define DOMAIN_RK3328(name, pwr, status, req, wakeup) \ > + DOMAIN_M(name, pwr, pwr, req, (req) << 10, req, wakeup) > > -#define DOMAIN_RK3368(pwr, status, req, wakeup) \ > - DOMAIN(pwr, status, req, (req) << 16, req, wakeup) > +#define DOMAIN_RK3368(name, pwr, status, req, wakeup) \ > + DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup) > > -#define DOMAIN_RK3399(pwr, status, req, wakeup) \ > - DOMAIN(pwr, status, req, req, req, wakeup) > +#define DOMAIN_RK3399(name, pwr, status, req, wakeup) \ > + DOMAIN(name, pwr, status, req, req, req, wakeup) > > static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd) > { > @@ -490,7 +494,10 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, > goto err_unprepare_clocks; > } > > - pd->genpd.name = node->name; > + if (!pd->info->name) > + pd->genpd.name = node->name; I guess we should make that "node->full_name" perhaps? And I guess it might be nicer to swap the cases if (pd->info->name) pd->genpd.name = pd->info->name else pd->genpd.name = node->full_name; for easier readability Heiko > + else > + pd->genpd.name = pd->info->name; > pd->genpd.power_off = rockchip_pd_power_off; > pd->genpd.power_on = rockchip_pd_power_on; > pd->genpd.attach_dev = rockchip_pd_attach_dev; > @@ -716,129 +723,129 @@ static int rockchip_pm_domain_probe(struct platform_device *pdev) > } > > static const struct rockchip_domain_info px30_pm_domains[] = { > - [PX30_PD_USB] = DOMAIN_PX30(BIT(5), BIT(5), BIT(10), false), > - [PX30_PD_SDCARD] = DOMAIN_PX30(BIT(8), BIT(8), BIT(9), false), > - [PX30_PD_GMAC] = DOMAIN_PX30(BIT(10), BIT(10), BIT(6), false), > - [PX30_PD_MMC_NAND] = DOMAIN_PX30(BIT(11), BIT(11), BIT(5), false), > - [PX30_PD_VPU] = DOMAIN_PX30(BIT(12), BIT(12), BIT(14), false), > - [PX30_PD_VO] = DOMAIN_PX30(BIT(13), BIT(13), BIT(7), false), > - [PX30_PD_VI] = DOMAIN_PX30(BIT(14), BIT(14), BIT(8), false), > - [PX30_PD_GPU] = DOMAIN_PX30(BIT(15), BIT(15), BIT(2), false), > + [PX30_PD_USB] = DOMAIN_PX30("usb", BIT(5), BIT(5), BIT(10), false), > + [PX30_PD_SDCARD] = DOMAIN_PX30("sdcard", BIT(8), BIT(8), BIT(9), false), > + [PX30_PD_GMAC] = DOMAIN_PX30("gmac", BIT(10), BIT(10), BIT(6), false), > + [PX30_PD_MMC_NAND] = DOMAIN_PX30("mmc_nand", BIT(11), BIT(11), BIT(5), false), > + [PX30_PD_VPU] = DOMAIN_PX30("vpu", BIT(12), BIT(12), BIT(14), false), > + [PX30_PD_VO] = DOMAIN_PX30("vo", BIT(13), BIT(13), BIT(7), false), > + [PX30_PD_VI] = DOMAIN_PX30("vi", BIT(14), BIT(14), BIT(8), false), > + [PX30_PD_GPU] = DOMAIN_PX30("gpu", BIT(15), BIT(15), BIT(2), false), > }; > > static const struct rockchip_domain_info rk3036_pm_domains[] = { > - [RK3036_PD_MSCH] = DOMAIN_RK3036(BIT(14), BIT(23), BIT(30), true), > - [RK3036_PD_CORE] = DOMAIN_RK3036(BIT(13), BIT(17), BIT(24), false), > - [RK3036_PD_PERI] = DOMAIN_RK3036(BIT(12), BIT(18), BIT(25), false), > - [RK3036_PD_VIO] = DOMAIN_RK3036(BIT(11), BIT(19), BIT(26), false), > - [RK3036_PD_VPU] = DOMAIN_RK3036(BIT(10), BIT(20), BIT(27), false), > - [RK3036_PD_GPU] = DOMAIN_RK3036(BIT(9), BIT(21), BIT(28), false), > - [RK3036_PD_SYS] = DOMAIN_RK3036(BIT(8), BIT(22), BIT(29), false), > + [RK3036_PD_MSCH] = DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true), > + [RK3036_PD_CORE] = DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false), > + [RK3036_PD_PERI] = DOMAIN_RK3036("peri", BIT(12), BIT(18), BIT(25), false), > + [RK3036_PD_VIO] = DOMAIN_RK3036("vio", BIT(11), BIT(19), BIT(26), false), > + [RK3036_PD_VPU] = DOMAIN_RK3036("vpu", BIT(10), BIT(20), BIT(27), false), > + [RK3036_PD_GPU] = DOMAIN_RK3036("gpu", BIT(9), BIT(21), BIT(28), false), > + [RK3036_PD_SYS] = DOMAIN_RK3036("sys", BIT(8), BIT(22), BIT(29), false), > }; > > static const struct rockchip_domain_info rk3066_pm_domains[] = { > - [RK3066_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > - [RK3066_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > - [RK3066_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > - [RK3066_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > - [RK3066_PD_CPU] = DOMAIN(0, BIT(5), BIT(1), BIT(26), BIT(31), false), > + [RK3066_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > + [RK3066_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > + [RK3066_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > + [RK3066_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > + [RK3066_PD_CPU] = DOMAIN("cpu", 0, BIT(5), BIT(1), BIT(26), BIT(31), false), > }; > > static const struct rockchip_domain_info rk3128_pm_domains[] = { > - [RK3128_PD_CORE] = DOMAIN_RK3288(BIT(0), BIT(0), BIT(4), false), > - [RK3128_PD_MSCH] = DOMAIN_RK3288(0, 0, BIT(6), true), > - [RK3128_PD_VIO] = DOMAIN_RK3288(BIT(3), BIT(3), BIT(2), false), > - [RK3128_PD_VIDEO] = DOMAIN_RK3288(BIT(2), BIT(2), BIT(1), false), > - [RK3128_PD_GPU] = DOMAIN_RK3288(BIT(1), BIT(1), BIT(3), false), > + [RK3128_PD_CORE] = DOMAIN_RK3288("core", BIT(0), BIT(0), BIT(4), false), > + [RK3128_PD_MSCH] = DOMAIN_RK3288("msch", 0, 0, BIT(6), true), > + [RK3128_PD_VIO] = DOMAIN_RK3288("vio", BIT(3), BIT(3), BIT(2), false), > + [RK3128_PD_VIDEO] = DOMAIN_RK3288("video", BIT(2), BIT(2), BIT(1), false), > + [RK3128_PD_GPU] = DOMAIN_RK3288("gpu", BIT(1), BIT(1), BIT(3), false), > }; > > static const struct rockchip_domain_info rk3188_pm_domains[] = { > - [RK3188_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > - [RK3188_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > - [RK3188_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > - [RK3188_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > - [RK3188_PD_CPU] = DOMAIN(BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false), > + [RK3188_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > + [RK3188_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > + [RK3188_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > + [RK3188_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > + [RK3188_PD_CPU] = DOMAIN("cpu", BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false), > }; > > static const struct rockchip_domain_info rk3228_pm_domains[] = { > - [RK3228_PD_CORE] = DOMAIN_RK3036(BIT(0), BIT(0), BIT(16), true), > - [RK3228_PD_MSCH] = DOMAIN_RK3036(BIT(1), BIT(1), BIT(17), true), > - [RK3228_PD_BUS] = DOMAIN_RK3036(BIT(2), BIT(2), BIT(18), true), > - [RK3228_PD_SYS] = DOMAIN_RK3036(BIT(3), BIT(3), BIT(19), true), > - [RK3228_PD_VIO] = DOMAIN_RK3036(BIT(4), BIT(4), BIT(20), false), > - [RK3228_PD_VOP] = DOMAIN_RK3036(BIT(5), BIT(5), BIT(21), false), > - [RK3228_PD_VPU] = DOMAIN_RK3036(BIT(6), BIT(6), BIT(22), false), > - [RK3228_PD_RKVDEC] = DOMAIN_RK3036(BIT(7), BIT(7), BIT(23), false), > - [RK3228_PD_GPU] = DOMAIN_RK3036(BIT(8), BIT(8), BIT(24), false), > - [RK3228_PD_PERI] = DOMAIN_RK3036(BIT(9), BIT(9), BIT(25), true), > - [RK3228_PD_GMAC] = DOMAIN_RK3036(BIT(10), BIT(10), BIT(26), false), > + [RK3228_PD_CORE] = DOMAIN_RK3036("core", BIT(0), BIT(0), BIT(16), true), > + [RK3228_PD_MSCH] = DOMAIN_RK3036("msch", BIT(1), BIT(1), BIT(17), true), > + [RK3228_PD_BUS] = DOMAIN_RK3036("bus", BIT(2), BIT(2), BIT(18), true), > + [RK3228_PD_SYS] = DOMAIN_RK3036("sys", BIT(3), BIT(3), BIT(19), true), > + [RK3228_PD_VIO] = DOMAIN_RK3036("vio", BIT(4), BIT(4), BIT(20), false), > + [RK3228_PD_VOP] = DOMAIN_RK3036("vop", BIT(5), BIT(5), BIT(21), false), > + [RK3228_PD_VPU] = DOMAIN_RK3036("vpu", BIT(6), BIT(6), BIT(22), false), > + [RK3228_PD_RKVDEC] = DOMAIN_RK3036("vdec", BIT(7), BIT(7), BIT(23), false), > + [RK3228_PD_GPU] = DOMAIN_RK3036("gpu", BIT(8), BIT(8), BIT(24), false), > + [RK3228_PD_PERI] = DOMAIN_RK3036("peri", BIT(9), BIT(9), BIT(25), true), > + [RK3228_PD_GMAC] = DOMAIN_RK3036("gmac", BIT(10), BIT(10), BIT(26), false), > }; > > static const struct rockchip_domain_info rk3288_pm_domains[] = { > - [RK3288_PD_VIO] = DOMAIN_RK3288(BIT(7), BIT(7), BIT(4), false), > - [RK3288_PD_HEVC] = DOMAIN_RK3288(BIT(14), BIT(10), BIT(9), false), > - [RK3288_PD_VIDEO] = DOMAIN_RK3288(BIT(8), BIT(8), BIT(3), false), > - [RK3288_PD_GPU] = DOMAIN_RK3288(BIT(9), BIT(9), BIT(2), false), > + [RK3288_PD_VIO] = DOMAIN_RK3288("vio", BIT(7), BIT(7), BIT(4), false), > + [RK3288_PD_HEVC] = DOMAIN_RK3288("hevc", BIT(14), BIT(10), BIT(9), false), > + [RK3288_PD_VIDEO] = DOMAIN_RK3288("video", BIT(8), BIT(8), BIT(3), false), > + [RK3288_PD_GPU] = DOMAIN_RK3288("gpu", BIT(9), BIT(9), BIT(2), false), > }; > > static const struct rockchip_domain_info rk3328_pm_domains[] = { > - [RK3328_PD_CORE] = DOMAIN_RK3328(0, BIT(0), BIT(0), false), > - [RK3328_PD_GPU] = DOMAIN_RK3328(0, BIT(1), BIT(1), false), > - [RK3328_PD_BUS] = DOMAIN_RK3328(0, BIT(2), BIT(2), true), > - [RK3328_PD_MSCH] = DOMAIN_RK3328(0, BIT(3), BIT(3), true), > - [RK3328_PD_PERI] = DOMAIN_RK3328(0, BIT(4), BIT(4), true), > - [RK3328_PD_VIDEO] = DOMAIN_RK3328(0, BIT(5), BIT(5), false), > - [RK3328_PD_HEVC] = DOMAIN_RK3328(0, BIT(6), BIT(6), false), > - [RK3328_PD_VIO] = DOMAIN_RK3328(0, BIT(8), BIT(8), false), > - [RK3328_PD_VPU] = DOMAIN_RK3328(0, BIT(9), BIT(9), false), > + [RK3328_PD_CORE] = DOMAIN_RK3328("core", 0, BIT(0), BIT(0), false), > + [RK3328_PD_GPU] = DOMAIN_RK3328("gpu", 0, BIT(1), BIT(1), false), > + [RK3328_PD_BUS] = DOMAIN_RK3328("bus", 0, BIT(2), BIT(2), true), > + [RK3328_PD_MSCH] = DOMAIN_RK3328("msch", 0, BIT(3), BIT(3), true), > + [RK3328_PD_PERI] = DOMAIN_RK3328("peri", 0, BIT(4), BIT(4), true), > + [RK3328_PD_VIDEO] = DOMAIN_RK3328("video", 0, BIT(5), BIT(5), false), > + [RK3328_PD_HEVC] = DOMAIN_RK3328("hevc", 0, BIT(6), BIT(6), false), > + [RK3328_PD_VIO] = DOMAIN_RK3328("vio", 0, BIT(8), BIT(8), false), > + [RK3328_PD_VPU] = DOMAIN_RK3328("vpu", 0, BIT(9), BIT(9), false), > }; > > static const struct rockchip_domain_info rk3366_pm_domains[] = { > - [RK3366_PD_PERI] = DOMAIN_RK3368(BIT(10), BIT(10), BIT(6), true), > - [RK3366_PD_VIO] = DOMAIN_RK3368(BIT(14), BIT(14), BIT(8), false), > - [RK3366_PD_VIDEO] = DOMAIN_RK3368(BIT(13), BIT(13), BIT(7), false), > - [RK3366_PD_RKVDEC] = DOMAIN_RK3368(BIT(11), BIT(11), BIT(7), false), > - [RK3366_PD_WIFIBT] = DOMAIN_RK3368(BIT(8), BIT(8), BIT(9), false), > - [RK3366_PD_VPU] = DOMAIN_RK3368(BIT(12), BIT(12), BIT(7), false), > - [RK3366_PD_GPU] = DOMAIN_RK3368(BIT(15), BIT(15), BIT(2), false), > + [RK3366_PD_PERI] = DOMAIN_RK3368("peri", BIT(10), BIT(10), BIT(6), true), > + [RK3366_PD_VIO] = DOMAIN_RK3368("vio", BIT(14), BIT(14), BIT(8), false), > + [RK3366_PD_VIDEO] = DOMAIN_RK3368("video", BIT(13), BIT(13), BIT(7), false), > + [RK3366_PD_RKVDEC] = DOMAIN_RK3368("vdec", BIT(11), BIT(11), BIT(7), false), > + [RK3366_PD_WIFIBT] = DOMAIN_RK3368("wifibt", BIT(8), BIT(8), BIT(9), false), > + [RK3366_PD_VPU] = DOMAIN_RK3368("vpu", BIT(12), BIT(12), BIT(7), false), > + [RK3366_PD_GPU] = DOMAIN_RK3368("gpu", BIT(15), BIT(15), BIT(2), false), > }; > > static const struct rockchip_domain_info rk3368_pm_domains[] = { > - [RK3368_PD_PERI] = DOMAIN_RK3368(BIT(13), BIT(12), BIT(6), true), > - [RK3368_PD_VIO] = DOMAIN_RK3368(BIT(15), BIT(14), BIT(8), false), > - [RK3368_PD_VIDEO] = DOMAIN_RK3368(BIT(14), BIT(13), BIT(7), false), > - [RK3368_PD_GPU_0] = DOMAIN_RK3368(BIT(16), BIT(15), BIT(2), false), > - [RK3368_PD_GPU_1] = DOMAIN_RK3368(BIT(17), BIT(16), BIT(2), false), > + [RK3368_PD_PERI] = DOMAIN_RK3368("peri", BIT(13), BIT(12), BIT(6), true), > + [RK3368_PD_VIO] = DOMAIN_RK3368("vio", BIT(15), BIT(14), BIT(8), false), > + [RK3368_PD_VIDEO] = DOMAIN_RK3368("video", BIT(14), BIT(13), BIT(7), false), > + [RK3368_PD_GPU_0] = DOMAIN_RK3368("gpu_0", BIT(16), BIT(15), BIT(2), false), > + [RK3368_PD_GPU_1] = DOMAIN_RK3368("gpu_1", BIT(17), BIT(16), BIT(2), false), > }; > > static const struct rockchip_domain_info rk3399_pm_domains[] = { > - [RK3399_PD_TCPD0] = DOMAIN_RK3399(BIT(8), BIT(8), 0, false), > - [RK3399_PD_TCPD1] = DOMAIN_RK3399(BIT(9), BIT(9), 0, false), > - [RK3399_PD_CCI] = DOMAIN_RK3399(BIT(10), BIT(10), 0, true), > - [RK3399_PD_CCI0] = DOMAIN_RK3399(0, 0, BIT(15), true), > - [RK3399_PD_CCI1] = DOMAIN_RK3399(0, 0, BIT(16), true), > - [RK3399_PD_PERILP] = DOMAIN_RK3399(BIT(11), BIT(11), BIT(1), true), > - [RK3399_PD_PERIHP] = DOMAIN_RK3399(BIT(12), BIT(12), BIT(2), true), > - [RK3399_PD_CENTER] = DOMAIN_RK3399(BIT(13), BIT(13), BIT(14), true), > - [RK3399_PD_VIO] = DOMAIN_RK3399(BIT(14), BIT(14), BIT(17), false), > - [RK3399_PD_GPU] = DOMAIN_RK3399(BIT(15), BIT(15), BIT(0), false), > - [RK3399_PD_VCODEC] = DOMAIN_RK3399(BIT(16), BIT(16), BIT(3), false), > - [RK3399_PD_VDU] = DOMAIN_RK3399(BIT(17), BIT(17), BIT(4), false), > - [RK3399_PD_RGA] = DOMAIN_RK3399(BIT(18), BIT(18), BIT(5), false), > - [RK3399_PD_IEP] = DOMAIN_RK3399(BIT(19), BIT(19), BIT(6), false), > - [RK3399_PD_VO] = DOMAIN_RK3399(BIT(20), BIT(20), 0, false), > - [RK3399_PD_VOPB] = DOMAIN_RK3399(0, 0, BIT(7), false), > - [RK3399_PD_VOPL] = DOMAIN_RK3399(0, 0, BIT(8), false), > - [RK3399_PD_ISP0] = DOMAIN_RK3399(BIT(22), BIT(22), BIT(9), false), > - [RK3399_PD_ISP1] = DOMAIN_RK3399(BIT(23), BIT(23), BIT(10), false), > - [RK3399_PD_HDCP] = DOMAIN_RK3399(BIT(24), BIT(24), BIT(11), false), > - [RK3399_PD_GMAC] = DOMAIN_RK3399(BIT(25), BIT(25), BIT(23), true), > - [RK3399_PD_EMMC] = DOMAIN_RK3399(BIT(26), BIT(26), BIT(24), true), > - [RK3399_PD_USB3] = DOMAIN_RK3399(BIT(27), BIT(27), BIT(12), true), > - [RK3399_PD_EDP] = DOMAIN_RK3399(BIT(28), BIT(28), BIT(22), false), > - [RK3399_PD_GIC] = DOMAIN_RK3399(BIT(29), BIT(29), BIT(27), true), > - [RK3399_PD_SD] = DOMAIN_RK3399(BIT(30), BIT(30), BIT(28), true), > - [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399(BIT(31), BIT(31), BIT(29), true), > + [RK3399_PD_TCPD0] = DOMAIN_RK3399("tcpd0", BIT(8), BIT(8), 0, false), > + [RK3399_PD_TCPD1] = DOMAIN_RK3399("tcpd1", BIT(9), BIT(9), 0, false), > + [RK3399_PD_CCI] = DOMAIN_RK3399("cci", BIT(10), BIT(10), 0, true), > + [RK3399_PD_CCI0] = DOMAIN_RK3399("cci0", 0, 0, BIT(15), true), > + [RK3399_PD_CCI1] = DOMAIN_RK3399("cci1", 0, 0, BIT(16), true), > + [RK3399_PD_PERILP] = DOMAIN_RK3399("perilp", BIT(11), BIT(11), BIT(1), true), > + [RK3399_PD_PERIHP] = DOMAIN_RK3399("perihp", BIT(12), BIT(12), BIT(2), true), > + [RK3399_PD_CENTER] = DOMAIN_RK3399("center", BIT(13), BIT(13), BIT(14), true), > + [RK3399_PD_VIO] = DOMAIN_RK3399("vio", BIT(14), BIT(14), BIT(17), false), > + [RK3399_PD_GPU] = DOMAIN_RK3399("gpu", BIT(15), BIT(15), BIT(0), false), > + [RK3399_PD_VCODEC] = DOMAIN_RK3399("vcodec", BIT(16), BIT(16), BIT(3), false), > + [RK3399_PD_VDU] = DOMAIN_RK3399("vdu", BIT(17), BIT(17), BIT(4), false), > + [RK3399_PD_RGA] = DOMAIN_RK3399("rga", BIT(18), BIT(18), BIT(5), false), > + [RK3399_PD_IEP] = DOMAIN_RK3399("iep", BIT(19), BIT(19), BIT(6), false), > + [RK3399_PD_VO] = DOMAIN_RK3399("vo", BIT(20), BIT(20), 0, false), > + [RK3399_PD_VOPB] = DOMAIN_RK3399("vopb", 0, 0, BIT(7), false), > + [RK3399_PD_VOPL] = DOMAIN_RK3399("vopl", 0, 0, BIT(8), false), > + [RK3399_PD_ISP0] = DOMAIN_RK3399("isp0", BIT(22), BIT(22), BIT(9), false), > + [RK3399_PD_ISP1] = DOMAIN_RK3399("isp1", BIT(23), BIT(23), BIT(10), false), > + [RK3399_PD_HDCP] = DOMAIN_RK3399("hdcp", BIT(24), BIT(24), BIT(11), false), > + [RK3399_PD_GMAC] = DOMAIN_RK3399("gmac", BIT(25), BIT(25), BIT(23), true), > + [RK3399_PD_EMMC] = DOMAIN_RK3399("emmc", BIT(26), BIT(26), BIT(24), true), > + [RK3399_PD_USB3] = DOMAIN_RK3399("usb3", BIT(27), BIT(27), BIT(12), true), > + [RK3399_PD_EDP] = DOMAIN_RK3399("edp", BIT(28), BIT(28), BIT(22), false), > + [RK3399_PD_GIC] = DOMAIN_RK3399("gic", BIT(29), BIT(29), BIT(27), true), > + [RK3399_PD_SD] = DOMAIN_RK3399("sd", BIT(30), BIT(30), BIT(28), true), > + [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true), > }; > > static const struct rockchip_pmu_info px30_pmu = { > ^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v5 07/11] soc: rockchip: pm-domains: Add a meaningful power domain name @ 2021-03-26 9:49 ` Heiko Stübner 0 siblings, 0 replies; 75+ messages in thread From: Heiko Stübner @ 2021-03-26 9:49 UTC (permalink / raw) To: robh+dt, Elaine Zhang Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Hi Elaine, Am Freitag, 26. März 2021, 10:17:39 CET schrieb Elaine Zhang: > Add the power domains names to the power domain info struct so we > have meaningful name for every power domain. > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> I like that approach very much, there is one tiny comment below. > --- > drivers/soc/rockchip/pm_domains.c | 217 +++++++++++++++--------------- > 1 file changed, 112 insertions(+), 105 deletions(-) > > diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c > index 54eb6cfc5d5b..d661d967079f 100644 > --- a/drivers/soc/rockchip/pm_domains.c > +++ b/drivers/soc/rockchip/pm_domains.c > @@ -29,6 +29,7 @@ > #include <dt-bindings/power/rk3399-power.h> > > struct rockchip_domain_info { > + const char *name; > int pwr_mask; > int status_mask; > int req_mask; > @@ -85,8 +86,9 @@ struct rockchip_pmu { > > #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd) > > -#define DOMAIN(pwr, status, req, idle, ack, wakeup) \ > +#define DOMAIN(_name, pwr, status, req, idle, ack, wakeup) \ > { \ > + .name = _name, \ > .pwr_mask = (pwr), \ > .status_mask = (status), \ > .req_mask = (req), \ > @@ -95,8 +97,9 @@ struct rockchip_pmu { > .active_wakeup = (wakeup), \ > } > > -#define DOMAIN_M(pwr, status, req, idle, ack, wakeup) \ > +#define DOMAIN_M(_name, pwr, status, req, idle, ack, wakeup) \ > { \ > + .name = _name, \ > .pwr_w_mask = (pwr) << 16, \ > .pwr_mask = (pwr), \ > .status_mask = (status), \ > @@ -107,8 +110,9 @@ struct rockchip_pmu { > .active_wakeup = wakeup, \ > } > > -#define DOMAIN_RK3036(req, ack, idle, wakeup) \ > +#define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \ > { \ > + .name = _name, \ > .req_mask = (req), \ > .req_w_mask = (req) << 16, \ > .ack_mask = (ack), \ > @@ -119,17 +123,17 @@ struct rockchip_pmu { > #define DOMAIN_PX30(pwr, status, req, wakeup) \ > DOMAIN_M(pwr, status, req, (req) << 16, req, wakeup) > > -#define DOMAIN_RK3288(pwr, status, req, wakeup) \ > - DOMAIN(pwr, status, req, req, (req) << 16, wakeup) > +#define DOMAIN_RK3288(name, pwr, status, req, wakeup) \ > + DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup) > > -#define DOMAIN_RK3328(pwr, status, req, wakeup) \ > - DOMAIN_M(pwr, pwr, req, (req) << 10, req, wakeup) > +#define DOMAIN_RK3328(name, pwr, status, req, wakeup) \ > + DOMAIN_M(name, pwr, pwr, req, (req) << 10, req, wakeup) > > -#define DOMAIN_RK3368(pwr, status, req, wakeup) \ > - DOMAIN(pwr, status, req, (req) << 16, req, wakeup) > +#define DOMAIN_RK3368(name, pwr, status, req, wakeup) \ > + DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup) > > -#define DOMAIN_RK3399(pwr, status, req, wakeup) \ > - DOMAIN(pwr, status, req, req, req, wakeup) > +#define DOMAIN_RK3399(name, pwr, status, req, wakeup) \ > + DOMAIN(name, pwr, status, req, req, req, wakeup) > > static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd) > { > @@ -490,7 +494,10 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, > goto err_unprepare_clocks; > } > > - pd->genpd.name = node->name; > + if (!pd->info->name) > + pd->genpd.name = node->name; I guess we should make that "node->full_name" perhaps? And I guess it might be nicer to swap the cases if (pd->info->name) pd->genpd.name = pd->info->name else pd->genpd.name = node->full_name; for easier readability Heiko > + else > + pd->genpd.name = pd->info->name; > pd->genpd.power_off = rockchip_pd_power_off; > pd->genpd.power_on = rockchip_pd_power_on; > pd->genpd.attach_dev = rockchip_pd_attach_dev; > @@ -716,129 +723,129 @@ static int rockchip_pm_domain_probe(struct platform_device *pdev) > } > > static const struct rockchip_domain_info px30_pm_domains[] = { > - [PX30_PD_USB] = DOMAIN_PX30(BIT(5), BIT(5), BIT(10), false), > - [PX30_PD_SDCARD] = DOMAIN_PX30(BIT(8), BIT(8), BIT(9), false), > - [PX30_PD_GMAC] = DOMAIN_PX30(BIT(10), BIT(10), BIT(6), false), > - [PX30_PD_MMC_NAND] = DOMAIN_PX30(BIT(11), BIT(11), BIT(5), false), > - [PX30_PD_VPU] = DOMAIN_PX30(BIT(12), BIT(12), BIT(14), false), > - [PX30_PD_VO] = DOMAIN_PX30(BIT(13), BIT(13), BIT(7), false), > - [PX30_PD_VI] = DOMAIN_PX30(BIT(14), BIT(14), BIT(8), false), > - [PX30_PD_GPU] = DOMAIN_PX30(BIT(15), BIT(15), BIT(2), false), > + [PX30_PD_USB] = DOMAIN_PX30("usb", BIT(5), BIT(5), BIT(10), false), > + [PX30_PD_SDCARD] = DOMAIN_PX30("sdcard", BIT(8), BIT(8), BIT(9), false), > + [PX30_PD_GMAC] = DOMAIN_PX30("gmac", BIT(10), BIT(10), BIT(6), false), > + [PX30_PD_MMC_NAND] = DOMAIN_PX30("mmc_nand", BIT(11), BIT(11), BIT(5), false), > + [PX30_PD_VPU] = DOMAIN_PX30("vpu", BIT(12), BIT(12), BIT(14), false), > + [PX30_PD_VO] = DOMAIN_PX30("vo", BIT(13), BIT(13), BIT(7), false), > + [PX30_PD_VI] = DOMAIN_PX30("vi", BIT(14), BIT(14), BIT(8), false), > + [PX30_PD_GPU] = DOMAIN_PX30("gpu", BIT(15), BIT(15), BIT(2), false), > }; > > static const struct rockchip_domain_info rk3036_pm_domains[] = { > - [RK3036_PD_MSCH] = DOMAIN_RK3036(BIT(14), BIT(23), BIT(30), true), > - [RK3036_PD_CORE] = DOMAIN_RK3036(BIT(13), BIT(17), BIT(24), false), > - [RK3036_PD_PERI] = DOMAIN_RK3036(BIT(12), BIT(18), BIT(25), false), > - [RK3036_PD_VIO] = DOMAIN_RK3036(BIT(11), BIT(19), BIT(26), false), > - [RK3036_PD_VPU] = DOMAIN_RK3036(BIT(10), BIT(20), BIT(27), false), > - [RK3036_PD_GPU] = DOMAIN_RK3036(BIT(9), BIT(21), BIT(28), false), > - [RK3036_PD_SYS] = DOMAIN_RK3036(BIT(8), BIT(22), BIT(29), false), > + [RK3036_PD_MSCH] = DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true), > + [RK3036_PD_CORE] = DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false), > + [RK3036_PD_PERI] = DOMAIN_RK3036("peri", BIT(12), BIT(18), BIT(25), false), > + [RK3036_PD_VIO] = DOMAIN_RK3036("vio", BIT(11), BIT(19), BIT(26), false), > + [RK3036_PD_VPU] = DOMAIN_RK3036("vpu", BIT(10), BIT(20), BIT(27), false), > + [RK3036_PD_GPU] = DOMAIN_RK3036("gpu", BIT(9), BIT(21), BIT(28), false), > + [RK3036_PD_SYS] = DOMAIN_RK3036("sys", BIT(8), BIT(22), BIT(29), false), > }; > > static const struct rockchip_domain_info rk3066_pm_domains[] = { > - [RK3066_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > - [RK3066_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > - [RK3066_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > - [RK3066_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > - [RK3066_PD_CPU] = DOMAIN(0, BIT(5), BIT(1), BIT(26), BIT(31), false), > + [RK3066_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > + [RK3066_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > + [RK3066_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > + [RK3066_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > + [RK3066_PD_CPU] = DOMAIN("cpu", 0, BIT(5), BIT(1), BIT(26), BIT(31), false), > }; > > static const struct rockchip_domain_info rk3128_pm_domains[] = { > - [RK3128_PD_CORE] = DOMAIN_RK3288(BIT(0), BIT(0), BIT(4), false), > - [RK3128_PD_MSCH] = DOMAIN_RK3288(0, 0, BIT(6), true), > - [RK3128_PD_VIO] = DOMAIN_RK3288(BIT(3), BIT(3), BIT(2), false), > - [RK3128_PD_VIDEO] = DOMAIN_RK3288(BIT(2), BIT(2), BIT(1), false), > - [RK3128_PD_GPU] = DOMAIN_RK3288(BIT(1), BIT(1), BIT(3), false), > + [RK3128_PD_CORE] = DOMAIN_RK3288("core", BIT(0), BIT(0), BIT(4), false), > + [RK3128_PD_MSCH] = DOMAIN_RK3288("msch", 0, 0, BIT(6), true), > + [RK3128_PD_VIO] = DOMAIN_RK3288("vio", BIT(3), BIT(3), BIT(2), false), > + [RK3128_PD_VIDEO] = DOMAIN_RK3288("video", BIT(2), BIT(2), BIT(1), false), > + [RK3128_PD_GPU] = DOMAIN_RK3288("gpu", BIT(1), BIT(1), BIT(3), false), > }; > > static const struct rockchip_domain_info rk3188_pm_domains[] = { > - [RK3188_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > - [RK3188_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > - [RK3188_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > - [RK3188_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > - [RK3188_PD_CPU] = DOMAIN(BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false), > + [RK3188_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > + [RK3188_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > + [RK3188_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > + [RK3188_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > + [RK3188_PD_CPU] = DOMAIN("cpu", BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false), > }; > > static const struct rockchip_domain_info rk3228_pm_domains[] = { > - [RK3228_PD_CORE] = DOMAIN_RK3036(BIT(0), BIT(0), BIT(16), true), > - [RK3228_PD_MSCH] = DOMAIN_RK3036(BIT(1), BIT(1), BIT(17), true), > - [RK3228_PD_BUS] = DOMAIN_RK3036(BIT(2), BIT(2), BIT(18), true), > - [RK3228_PD_SYS] = DOMAIN_RK3036(BIT(3), BIT(3), BIT(19), true), > - [RK3228_PD_VIO] = DOMAIN_RK3036(BIT(4), BIT(4), BIT(20), false), > - [RK3228_PD_VOP] = DOMAIN_RK3036(BIT(5), BIT(5), BIT(21), false), > - [RK3228_PD_VPU] = DOMAIN_RK3036(BIT(6), BIT(6), BIT(22), false), > - [RK3228_PD_RKVDEC] = DOMAIN_RK3036(BIT(7), BIT(7), BIT(23), false), > - [RK3228_PD_GPU] = DOMAIN_RK3036(BIT(8), BIT(8), BIT(24), false), > - [RK3228_PD_PERI] = DOMAIN_RK3036(BIT(9), BIT(9), BIT(25), true), > - [RK3228_PD_GMAC] = DOMAIN_RK3036(BIT(10), BIT(10), BIT(26), false), > + [RK3228_PD_CORE] = DOMAIN_RK3036("core", BIT(0), BIT(0), BIT(16), true), > + [RK3228_PD_MSCH] = DOMAIN_RK3036("msch", BIT(1), BIT(1), BIT(17), true), > + [RK3228_PD_BUS] = DOMAIN_RK3036("bus", BIT(2), BIT(2), BIT(18), true), > + [RK3228_PD_SYS] = DOMAIN_RK3036("sys", BIT(3), BIT(3), BIT(19), true), > + [RK3228_PD_VIO] = DOMAIN_RK3036("vio", BIT(4), BIT(4), BIT(20), false), > + [RK3228_PD_VOP] = DOMAIN_RK3036("vop", BIT(5), BIT(5), BIT(21), false), > + [RK3228_PD_VPU] = DOMAIN_RK3036("vpu", BIT(6), BIT(6), BIT(22), false), > + [RK3228_PD_RKVDEC] = DOMAIN_RK3036("vdec", BIT(7), BIT(7), BIT(23), false), > + [RK3228_PD_GPU] = DOMAIN_RK3036("gpu", BIT(8), BIT(8), BIT(24), false), > + [RK3228_PD_PERI] = DOMAIN_RK3036("peri", BIT(9), BIT(9), BIT(25), true), > + [RK3228_PD_GMAC] = DOMAIN_RK3036("gmac", BIT(10), BIT(10), BIT(26), false), > }; > > static const struct rockchip_domain_info rk3288_pm_domains[] = { > - [RK3288_PD_VIO] = DOMAIN_RK3288(BIT(7), BIT(7), BIT(4), false), > - [RK3288_PD_HEVC] = DOMAIN_RK3288(BIT(14), BIT(10), BIT(9), false), > - [RK3288_PD_VIDEO] = DOMAIN_RK3288(BIT(8), BIT(8), BIT(3), false), > - [RK3288_PD_GPU] = DOMAIN_RK3288(BIT(9), BIT(9), BIT(2), false), > + [RK3288_PD_VIO] = DOMAIN_RK3288("vio", BIT(7), BIT(7), BIT(4), false), > + [RK3288_PD_HEVC] = DOMAIN_RK3288("hevc", BIT(14), BIT(10), BIT(9), false), > + [RK3288_PD_VIDEO] = DOMAIN_RK3288("video", BIT(8), BIT(8), BIT(3), false), > + [RK3288_PD_GPU] = DOMAIN_RK3288("gpu", BIT(9), BIT(9), BIT(2), false), > }; > > static const struct rockchip_domain_info rk3328_pm_domains[] = { > - [RK3328_PD_CORE] = DOMAIN_RK3328(0, BIT(0), BIT(0), false), > - [RK3328_PD_GPU] = DOMAIN_RK3328(0, BIT(1), BIT(1), false), > - [RK3328_PD_BUS] = DOMAIN_RK3328(0, BIT(2), BIT(2), true), > - [RK3328_PD_MSCH] = DOMAIN_RK3328(0, BIT(3), BIT(3), true), > - [RK3328_PD_PERI] = DOMAIN_RK3328(0, BIT(4), BIT(4), true), > - [RK3328_PD_VIDEO] = DOMAIN_RK3328(0, BIT(5), BIT(5), false), > - [RK3328_PD_HEVC] = DOMAIN_RK3328(0, BIT(6), BIT(6), false), > - [RK3328_PD_VIO] = DOMAIN_RK3328(0, BIT(8), BIT(8), false), > - [RK3328_PD_VPU] = DOMAIN_RK3328(0, BIT(9), BIT(9), false), > + [RK3328_PD_CORE] = DOMAIN_RK3328("core", 0, BIT(0), BIT(0), false), > + [RK3328_PD_GPU] = DOMAIN_RK3328("gpu", 0, BIT(1), BIT(1), false), > + [RK3328_PD_BUS] = DOMAIN_RK3328("bus", 0, BIT(2), BIT(2), true), > + [RK3328_PD_MSCH] = DOMAIN_RK3328("msch", 0, BIT(3), BIT(3), true), > + [RK3328_PD_PERI] = DOMAIN_RK3328("peri", 0, BIT(4), BIT(4), true), > + [RK3328_PD_VIDEO] = DOMAIN_RK3328("video", 0, BIT(5), BIT(5), false), > + [RK3328_PD_HEVC] = DOMAIN_RK3328("hevc", 0, BIT(6), BIT(6), false), > + [RK3328_PD_VIO] = DOMAIN_RK3328("vio", 0, BIT(8), BIT(8), false), > + [RK3328_PD_VPU] = DOMAIN_RK3328("vpu", 0, BIT(9), BIT(9), false), > }; > > static const struct rockchip_domain_info rk3366_pm_domains[] = { > - [RK3366_PD_PERI] = DOMAIN_RK3368(BIT(10), BIT(10), BIT(6), true), > - [RK3366_PD_VIO] = DOMAIN_RK3368(BIT(14), BIT(14), BIT(8), false), > - [RK3366_PD_VIDEO] = DOMAIN_RK3368(BIT(13), BIT(13), BIT(7), false), > - [RK3366_PD_RKVDEC] = DOMAIN_RK3368(BIT(11), BIT(11), BIT(7), false), > - [RK3366_PD_WIFIBT] = DOMAIN_RK3368(BIT(8), BIT(8), BIT(9), false), > - [RK3366_PD_VPU] = DOMAIN_RK3368(BIT(12), BIT(12), BIT(7), false), > - [RK3366_PD_GPU] = DOMAIN_RK3368(BIT(15), BIT(15), BIT(2), false), > + [RK3366_PD_PERI] = DOMAIN_RK3368("peri", BIT(10), BIT(10), BIT(6), true), > + [RK3366_PD_VIO] = DOMAIN_RK3368("vio", BIT(14), BIT(14), BIT(8), false), > + [RK3366_PD_VIDEO] = DOMAIN_RK3368("video", BIT(13), BIT(13), BIT(7), false), > + [RK3366_PD_RKVDEC] = DOMAIN_RK3368("vdec", BIT(11), BIT(11), BIT(7), false), > + [RK3366_PD_WIFIBT] = DOMAIN_RK3368("wifibt", BIT(8), BIT(8), BIT(9), false), > + [RK3366_PD_VPU] = DOMAIN_RK3368("vpu", BIT(12), BIT(12), BIT(7), false), > + [RK3366_PD_GPU] = DOMAIN_RK3368("gpu", BIT(15), BIT(15), BIT(2), false), > }; > > static const struct rockchip_domain_info rk3368_pm_domains[] = { > - [RK3368_PD_PERI] = DOMAIN_RK3368(BIT(13), BIT(12), BIT(6), true), > - [RK3368_PD_VIO] = DOMAIN_RK3368(BIT(15), BIT(14), BIT(8), false), > - [RK3368_PD_VIDEO] = DOMAIN_RK3368(BIT(14), BIT(13), BIT(7), false), > - [RK3368_PD_GPU_0] = DOMAIN_RK3368(BIT(16), BIT(15), BIT(2), false), > - [RK3368_PD_GPU_1] = DOMAIN_RK3368(BIT(17), BIT(16), BIT(2), false), > + [RK3368_PD_PERI] = DOMAIN_RK3368("peri", BIT(13), BIT(12), BIT(6), true), > + [RK3368_PD_VIO] = DOMAIN_RK3368("vio", BIT(15), BIT(14), BIT(8), false), > + [RK3368_PD_VIDEO] = DOMAIN_RK3368("video", BIT(14), BIT(13), BIT(7), false), > + [RK3368_PD_GPU_0] = DOMAIN_RK3368("gpu_0", BIT(16), BIT(15), BIT(2), false), > + [RK3368_PD_GPU_1] = DOMAIN_RK3368("gpu_1", BIT(17), BIT(16), BIT(2), false), > }; > > static const struct rockchip_domain_info rk3399_pm_domains[] = { > - [RK3399_PD_TCPD0] = DOMAIN_RK3399(BIT(8), BIT(8), 0, false), > - [RK3399_PD_TCPD1] = DOMAIN_RK3399(BIT(9), BIT(9), 0, false), > - [RK3399_PD_CCI] = DOMAIN_RK3399(BIT(10), BIT(10), 0, true), > - [RK3399_PD_CCI0] = DOMAIN_RK3399(0, 0, BIT(15), true), > - [RK3399_PD_CCI1] = DOMAIN_RK3399(0, 0, BIT(16), true), > - [RK3399_PD_PERILP] = DOMAIN_RK3399(BIT(11), BIT(11), BIT(1), true), > - [RK3399_PD_PERIHP] = DOMAIN_RK3399(BIT(12), BIT(12), BIT(2), true), > - [RK3399_PD_CENTER] = DOMAIN_RK3399(BIT(13), BIT(13), BIT(14), true), > - [RK3399_PD_VIO] = DOMAIN_RK3399(BIT(14), BIT(14), BIT(17), false), > - [RK3399_PD_GPU] = DOMAIN_RK3399(BIT(15), BIT(15), BIT(0), false), > - [RK3399_PD_VCODEC] = DOMAIN_RK3399(BIT(16), BIT(16), BIT(3), false), > - [RK3399_PD_VDU] = DOMAIN_RK3399(BIT(17), BIT(17), BIT(4), false), > - [RK3399_PD_RGA] = DOMAIN_RK3399(BIT(18), BIT(18), BIT(5), false), > - [RK3399_PD_IEP] = DOMAIN_RK3399(BIT(19), BIT(19), BIT(6), false), > - [RK3399_PD_VO] = DOMAIN_RK3399(BIT(20), BIT(20), 0, false), > - [RK3399_PD_VOPB] = DOMAIN_RK3399(0, 0, BIT(7), false), > - [RK3399_PD_VOPL] = DOMAIN_RK3399(0, 0, BIT(8), false), > - [RK3399_PD_ISP0] = DOMAIN_RK3399(BIT(22), BIT(22), BIT(9), false), > - [RK3399_PD_ISP1] = DOMAIN_RK3399(BIT(23), BIT(23), BIT(10), false), > - [RK3399_PD_HDCP] = DOMAIN_RK3399(BIT(24), BIT(24), BIT(11), false), > - [RK3399_PD_GMAC] = DOMAIN_RK3399(BIT(25), BIT(25), BIT(23), true), > - [RK3399_PD_EMMC] = DOMAIN_RK3399(BIT(26), BIT(26), BIT(24), true), > - [RK3399_PD_USB3] = DOMAIN_RK3399(BIT(27), BIT(27), BIT(12), true), > - [RK3399_PD_EDP] = DOMAIN_RK3399(BIT(28), BIT(28), BIT(22), false), > - [RK3399_PD_GIC] = DOMAIN_RK3399(BIT(29), BIT(29), BIT(27), true), > - [RK3399_PD_SD] = DOMAIN_RK3399(BIT(30), BIT(30), BIT(28), true), > - [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399(BIT(31), BIT(31), BIT(29), true), > + [RK3399_PD_TCPD0] = DOMAIN_RK3399("tcpd0", BIT(8), BIT(8), 0, false), > + [RK3399_PD_TCPD1] = DOMAIN_RK3399("tcpd1", BIT(9), BIT(9), 0, false), > + [RK3399_PD_CCI] = DOMAIN_RK3399("cci", BIT(10), BIT(10), 0, true), > + [RK3399_PD_CCI0] = DOMAIN_RK3399("cci0", 0, 0, BIT(15), true), > + [RK3399_PD_CCI1] = DOMAIN_RK3399("cci1", 0, 0, BIT(16), true), > + [RK3399_PD_PERILP] = DOMAIN_RK3399("perilp", BIT(11), BIT(11), BIT(1), true), > + [RK3399_PD_PERIHP] = DOMAIN_RK3399("perihp", BIT(12), BIT(12), BIT(2), true), > + [RK3399_PD_CENTER] = DOMAIN_RK3399("center", BIT(13), BIT(13), BIT(14), true), > + [RK3399_PD_VIO] = DOMAIN_RK3399("vio", BIT(14), BIT(14), BIT(17), false), > + [RK3399_PD_GPU] = DOMAIN_RK3399("gpu", BIT(15), BIT(15), BIT(0), false), > + [RK3399_PD_VCODEC] = DOMAIN_RK3399("vcodec", BIT(16), BIT(16), BIT(3), false), > + [RK3399_PD_VDU] = DOMAIN_RK3399("vdu", BIT(17), BIT(17), BIT(4), false), > + [RK3399_PD_RGA] = DOMAIN_RK3399("rga", BIT(18), BIT(18), BIT(5), false), > + [RK3399_PD_IEP] = DOMAIN_RK3399("iep", BIT(19), BIT(19), BIT(6), false), > + [RK3399_PD_VO] = DOMAIN_RK3399("vo", BIT(20), BIT(20), 0, false), > + [RK3399_PD_VOPB] = DOMAIN_RK3399("vopb", 0, 0, BIT(7), false), > + [RK3399_PD_VOPL] = DOMAIN_RK3399("vopl", 0, 0, BIT(8), false), > + [RK3399_PD_ISP0] = DOMAIN_RK3399("isp0", BIT(22), BIT(22), BIT(9), false), > + [RK3399_PD_ISP1] = DOMAIN_RK3399("isp1", BIT(23), BIT(23), BIT(10), false), > + [RK3399_PD_HDCP] = DOMAIN_RK3399("hdcp", BIT(24), BIT(24), BIT(11), false), > + [RK3399_PD_GMAC] = DOMAIN_RK3399("gmac", BIT(25), BIT(25), BIT(23), true), > + [RK3399_PD_EMMC] = DOMAIN_RK3399("emmc", BIT(26), BIT(26), BIT(24), true), > + [RK3399_PD_USB3] = DOMAIN_RK3399("usb3", BIT(27), BIT(27), BIT(12), true), > + [RK3399_PD_EDP] = DOMAIN_RK3399("edp", BIT(28), BIT(28), BIT(22), false), > + [RK3399_PD_GIC] = DOMAIN_RK3399("gic", BIT(29), BIT(29), BIT(27), true), > + [RK3399_PD_SD] = DOMAIN_RK3399("sd", BIT(30), BIT(30), BIT(28), true), > + [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true), > }; > > static const struct rockchip_pmu_info px30_pmu = { > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v5 08/11] dt-bindings: add power-domain header for RK3568 SoCs 2021-03-26 9:15 ` Elaine Zhang (?) @ 2021-03-26 9:17 ` Elaine Zhang -1 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:17 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang According to a description from TRM, add all the power domains Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- include/dt-bindings/power/rk3568-power.h | 32 ++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 include/dt-bindings/power/rk3568-power.h diff --git a/include/dt-bindings/power/rk3568-power.h b/include/dt-bindings/power/rk3568-power.h new file mode 100644 index 000000000000..6cc1af1a9d26 --- /dev/null +++ b/include/dt-bindings/power/rk3568-power.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__ +#define __DT_BINDINGS_POWER_RK3568_POWER_H__ + +/* VD_CORE */ +#define RK3568_PD_CPU_0 0 +#define RK3568_PD_CPU_1 1 +#define RK3568_PD_CPU_2 2 +#define RK3568_PD_CPU_3 3 +#define RK3568_PD_CORE_ALIVE 4 + +/* VD_PMU */ +#define RK3568_PD_PMU 5 + +/* VD_NPU */ +#define RK3568_PD_NPU 6 + +/* VD_GPU */ +#define RK3568_PD_GPU 7 + +/* VD_LOGIC */ +#define RK3568_PD_VI 8 +#define RK3568_PD_VO 9 +#define RK3568_PD_RGA 10 +#define RK3568_PD_VPU 11 +#define RK3568_PD_CENTER 12 +#define RK3568_PD_RKVDEC 13 +#define RK3568_PD_RKVENC 14 +#define RK3568_PD_PIPE 15 +#define RK3568_PD_LOGIC_ALIVE 16 + +#endif -- 2.17.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v5 08/11] dt-bindings: add power-domain header for RK3568 SoCs @ 2021-03-26 9:17 ` Elaine Zhang 0 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:17 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang According to a description from TRM, add all the power domains Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- include/dt-bindings/power/rk3568-power.h | 32 ++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 include/dt-bindings/power/rk3568-power.h diff --git a/include/dt-bindings/power/rk3568-power.h b/include/dt-bindings/power/rk3568-power.h new file mode 100644 index 000000000000..6cc1af1a9d26 --- /dev/null +++ b/include/dt-bindings/power/rk3568-power.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__ +#define __DT_BINDINGS_POWER_RK3568_POWER_H__ + +/* VD_CORE */ +#define RK3568_PD_CPU_0 0 +#define RK3568_PD_CPU_1 1 +#define RK3568_PD_CPU_2 2 +#define RK3568_PD_CPU_3 3 +#define RK3568_PD_CORE_ALIVE 4 + +/* VD_PMU */ +#define RK3568_PD_PMU 5 + +/* VD_NPU */ +#define RK3568_PD_NPU 6 + +/* VD_GPU */ +#define RK3568_PD_GPU 7 + +/* VD_LOGIC */ +#define RK3568_PD_VI 8 +#define RK3568_PD_VO 9 +#define RK3568_PD_RGA 10 +#define RK3568_PD_VPU 11 +#define RK3568_PD_CENTER 12 +#define RK3568_PD_RKVDEC 13 +#define RK3568_PD_RKVENC 14 +#define RK3568_PD_PIPE 15 +#define RK3568_PD_LOGIC_ALIVE 16 + +#endif -- 2.17.1 ^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v5 08/11] dt-bindings: add power-domain header for RK3568 SoCs @ 2021-03-26 9:17 ` Elaine Zhang 0 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:17 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang According to a description from TRM, add all the power domains Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- include/dt-bindings/power/rk3568-power.h | 32 ++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 include/dt-bindings/power/rk3568-power.h diff --git a/include/dt-bindings/power/rk3568-power.h b/include/dt-bindings/power/rk3568-power.h new file mode 100644 index 000000000000..6cc1af1a9d26 --- /dev/null +++ b/include/dt-bindings/power/rk3568-power.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__ +#define __DT_BINDINGS_POWER_RK3568_POWER_H__ + +/* VD_CORE */ +#define RK3568_PD_CPU_0 0 +#define RK3568_PD_CPU_1 1 +#define RK3568_PD_CPU_2 2 +#define RK3568_PD_CPU_3 3 +#define RK3568_PD_CORE_ALIVE 4 + +/* VD_PMU */ +#define RK3568_PD_PMU 5 + +/* VD_NPU */ +#define RK3568_PD_NPU 6 + +/* VD_GPU */ +#define RK3568_PD_GPU 7 + +/* VD_LOGIC */ +#define RK3568_PD_VI 8 +#define RK3568_PD_VO 9 +#define RK3568_PD_RGA 10 +#define RK3568_PD_VPU 11 +#define RK3568_PD_CENTER 12 +#define RK3568_PD_RKVDEC 13 +#define RK3568_PD_RKVENC 14 +#define RK3568_PD_PIPE 15 +#define RK3568_PD_LOGIC_ALIVE 16 + +#endif -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 75+ messages in thread
* Re: [PATCH v5 08/11] dt-bindings: add power-domain header for RK3568 SoCs 2021-03-26 9:17 ` Elaine Zhang (?) @ 2021-03-26 9:52 ` Enric Balletbo Serra -1 siblings, 0 replies; 75+ messages in thread From: Enric Balletbo Serra @ 2021-03-26 9:52 UTC (permalink / raw) To: Elaine Zhang Cc: Rob Herring, Heiko Stübner, devicetree@vger.kernel.org, Linux ARM, open list:ARM/Rockchip SoC..., linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao Missatge de Elaine Zhang <zhangqing@rock-chips.com> del dia dv., 26 de març 2021 a les 10:18: > > According to a description from TRM, add all the power domains > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > --- > include/dt-bindings/power/rk3568-power.h | 32 ++++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > create mode 100644 include/dt-bindings/power/rk3568-power.h > > diff --git a/include/dt-bindings/power/rk3568-power.h b/include/dt-bindings/power/rk3568-power.h > new file mode 100644 > index 000000000000..6cc1af1a9d26 > --- /dev/null > +++ b/include/dt-bindings/power/rk3568-power.h > @@ -0,0 +1,32 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +#ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__ > +#define __DT_BINDINGS_POWER_RK3568_POWER_H__ > + > +/* VD_CORE */ > +#define RK3568_PD_CPU_0 0 > +#define RK3568_PD_CPU_1 1 > +#define RK3568_PD_CPU_2 2 > +#define RK3568_PD_CPU_3 3 > +#define RK3568_PD_CORE_ALIVE 4 > + > +/* VD_PMU */ > +#define RK3568_PD_PMU 5 > + > +/* VD_NPU */ > +#define RK3568_PD_NPU 6 > + > +/* VD_GPU */ > +#define RK3568_PD_GPU 7 > + > +/* VD_LOGIC */ > +#define RK3568_PD_VI 8 > +#define RK3568_PD_VO 9 > +#define RK3568_PD_RGA 10 > +#define RK3568_PD_VPU 11 > +#define RK3568_PD_CENTER 12 > +#define RK3568_PD_RKVDEC 13 > +#define RK3568_PD_RKVENC 14 > +#define RK3568_PD_PIPE 15 > +#define RK3568_PD_LOGIC_ALIVE 16 > + > +#endif > -- > 2.17.1 > > > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v5 08/11] dt-bindings: add power-domain header for RK3568 SoCs @ 2021-03-26 9:52 ` Enric Balletbo Serra 0 siblings, 0 replies; 75+ messages in thread From: Enric Balletbo Serra @ 2021-03-26 9:52 UTC (permalink / raw) To: Elaine Zhang Cc: Rob Herring, Heiko Stübner, devicetree@vger.kernel.org, Linux ARM, open list:ARM/Rockchip SoC..., linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao Missatge de Elaine Zhang <zhangqing@rock-chips.com> del dia dv., 26 de març 2021 a les 10:18: > > According to a description from TRM, add all the power domains > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > --- > include/dt-bindings/power/rk3568-power.h | 32 ++++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > create mode 100644 include/dt-bindings/power/rk3568-power.h > > diff --git a/include/dt-bindings/power/rk3568-power.h b/include/dt-bindings/power/rk3568-power.h > new file mode 100644 > index 000000000000..6cc1af1a9d26 > --- /dev/null > +++ b/include/dt-bindings/power/rk3568-power.h > @@ -0,0 +1,32 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +#ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__ > +#define __DT_BINDINGS_POWER_RK3568_POWER_H__ > + > +/* VD_CORE */ > +#define RK3568_PD_CPU_0 0 > +#define RK3568_PD_CPU_1 1 > +#define RK3568_PD_CPU_2 2 > +#define RK3568_PD_CPU_3 3 > +#define RK3568_PD_CORE_ALIVE 4 > + > +/* VD_PMU */ > +#define RK3568_PD_PMU 5 > + > +/* VD_NPU */ > +#define RK3568_PD_NPU 6 > + > +/* VD_GPU */ > +#define RK3568_PD_GPU 7 > + > +/* VD_LOGIC */ > +#define RK3568_PD_VI 8 > +#define RK3568_PD_VO 9 > +#define RK3568_PD_RGA 10 > +#define RK3568_PD_VPU 11 > +#define RK3568_PD_CENTER 12 > +#define RK3568_PD_RKVDEC 13 > +#define RK3568_PD_RKVENC 14 > +#define RK3568_PD_PIPE 15 > +#define RK3568_PD_LOGIC_ALIVE 16 > + > +#endif > -- > 2.17.1 > > > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v5 08/11] dt-bindings: add power-domain header for RK3568 SoCs @ 2021-03-26 9:52 ` Enric Balletbo Serra 0 siblings, 0 replies; 75+ messages in thread From: Enric Balletbo Serra @ 2021-03-26 9:52 UTC (permalink / raw) To: Elaine Zhang Cc: Rob Herring, Heiko Stübner, devicetree@vger.kernel.org, Linux ARM, open list:ARM/Rockchip SoC..., linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao Missatge de Elaine Zhang <zhangqing@rock-chips.com> del dia dv., 26 de març 2021 a les 10:18: > > According to a description from TRM, add all the power domains > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > --- > include/dt-bindings/power/rk3568-power.h | 32 ++++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > create mode 100644 include/dt-bindings/power/rk3568-power.h > > diff --git a/include/dt-bindings/power/rk3568-power.h b/include/dt-bindings/power/rk3568-power.h > new file mode 100644 > index 000000000000..6cc1af1a9d26 > --- /dev/null > +++ b/include/dt-bindings/power/rk3568-power.h > @@ -0,0 +1,32 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +#ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__ > +#define __DT_BINDINGS_POWER_RK3568_POWER_H__ > + > +/* VD_CORE */ > +#define RK3568_PD_CPU_0 0 > +#define RK3568_PD_CPU_1 1 > +#define RK3568_PD_CPU_2 2 > +#define RK3568_PD_CPU_3 3 > +#define RK3568_PD_CORE_ALIVE 4 > + > +/* VD_PMU */ > +#define RK3568_PD_PMU 5 > + > +/* VD_NPU */ > +#define RK3568_PD_NPU 6 > + > +/* VD_GPU */ > +#define RK3568_PD_GPU 7 > + > +/* VD_LOGIC */ > +#define RK3568_PD_VI 8 > +#define RK3568_PD_VO 9 > +#define RK3568_PD_RGA 10 > +#define RK3568_PD_VPU 11 > +#define RK3568_PD_CENTER 12 > +#define RK3568_PD_RKVDEC 13 > +#define RK3568_PD_RKVENC 14 > +#define RK3568_PD_PIPE 15 > +#define RK3568_PD_LOGIC_ALIVE 16 > + > +#endif > -- > 2.17.1 > > > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v5 09/11] dt-bindings: power: rockchip: Convert to json-schema 2021-03-26 9:15 ` Elaine Zhang (?) @ 2021-03-26 9:18 ` Elaine Zhang -1 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:18 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang, Enric Balletbo i Serra Convert the soc/rockchip/power_domain.txt binding document to json-schema and move to the power bindings directory. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- .../power/rockchip,power-controller.yaml | 291 ++++++++++++++++++ .../bindings/soc/rockchip/power_domain.txt | 136 -------- 2 files changed, 291 insertions(+), 136 deletions(-) create mode 100644 Documentation/devicetree/bindings/power/rockchip,power-controller.yaml delete mode 100644 Documentation/devicetree/bindings/soc/rockchip/power_domain.txt diff --git a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml new file mode 100644 index 000000000000..9fec9e227432 --- /dev/null +++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml @@ -0,0 +1,291 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/rockchip,power-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip Power Domains + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: | + Rockchip processors include support for multiple power domains which can be + powered up/down by software based on different application scenarios to save power. + + Power domains contained within power-controller node are generic power domain + providers documented in Documentation/devicetree/bindings/power/power-domain.yaml. + + IP cores belonging to a power domain should contain a "power-domains" + property that is a phandle for the power domain node representing the domain. + +properties: + $nodename: + const: power-controller + + compatible: + enum: + - rockchip,px30-power-controller + - rockchip,rk3036-power-controller + - rockchip,rk3066-power-controller + - rockchip,rk3128-power-controller + - rockchip,rk3188-power-controller + - rockchip,rk3228-power-controller + - rockchip,rk3288-power-controller + - rockchip,rk3328-power-controller + - rockchip,rk3366-power-controller + - rockchip,rk3368-power-controller + - rockchip,rk3399-power-controller + + "#power-domain-cells": + const: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + clocks: true + + assigned-clocks: + minItems: 1 + + assigned-clock-parents: + minItems: 1 + +patternProperties: + "^power-domain@[0-9a-f]+$": + type: object + description: | + Represents the power domains within the power controller node as documented + in Documentation/devicetree/bindings/power/power-domain.yaml. + + properties: + + "#power-domain-cells": + description: + Must be 0 for nodes representing a single PM domain and 1 for nodes + providing multiple PM domains. + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + reg: + maxItems: 1 + description: | + Power domain index. Valid values are defined in + "include/dt-bindings/power/px30-power.h" + "include/dt-bindings/power/rk3036-power.h" + "include/dt-bindings/power/rk3066-power.h" + "include/dt-bindings/power/rk3128-power.h" + "include/dt-bindings/power/rk3188-power.h" + "include/dt-bindings/power/rk3228-power.h" + "include/dt-bindings/power/rk3288-power.h" + "include/dt-bindings/power/rk3328-power.h" + "include/dt-bindings/power/rk3366-power.h" + "include/dt-bindings/power/rk3368-power.h" + "include/dt-bindings/power/rk3399-power.h" + + clocks: + description: | + A number of phandles to clocks that need to be enabled while power domain + switches state. + + pm_qos: + description: | + A number of phandles to qos blocks which need to be saved and restored + while power domain switches state. + + patternProperties: + "^power-domain@[0-9a-f]+$": + type: object + description: | + Represents a power domain child within a power domain parent node. + + properties: + + "#power-domain-cells": + description: + Must be 0 for nodes representing a single PM domain and 1 for nodes + providing multiple PM domains. + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + reg: + maxItems: 1 + + clocks: + description: | + A number of phandles to clocks that need to be enabled while power domain + switches state. + + pm_qos: + description: | + A number of phandles to qos blocks which need to be saved and restored + while power domain switches state. + + patternProperties: + "^power-domain@[0-9a-f]+$": + type: object + description: | + Represents a power domain child within a power domain parent node. + + properties: + + "#power-domain-cells": + description: + Must be 0 for nodes representing a single PM domain and 1 for nodes + providing multiple PM domains. + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + reg: + maxItems: 1 + + clocks: + description: | + A number of phandles to clocks that need to be enabled while power domain + switches state. + + pm_qos: + description: | + A number of phandles to qos blocks which need to be saved and restored + while power domain switches state. + + required: + - reg + + additionalProperties: false + + required: + - reg + + additionalProperties: false + + required: + - reg + + additionalProperties: false + +required: + - compatible + - "#power-domain-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/rk3399-cru.h> + #include <dt-bindings/power/rk3399-power.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + qos_hdcp: qos@ffa90000 { + compatible = "rockchip,rk3399-qos", "syscon"; + reg = <0x0 0xffa90000 0x0 0x20>; + }; + + qos_iep: qos@ffa98000 { + compatible = "rockchip,rk3399-qos", "syscon"; + reg = <0x0 0xffa98000 0x0 0x20>; + }; + + qos_rga_r: qos@ffab0000 { + compatible = "rockchip,rk3399-qos", "syscon"; + reg = <0x0 0xffab0000 0x0 0x20>; + }; + + qos_rga_w: qos@ffab0080 { + compatible = "rockchip,rk3399-qos", "syscon"; + reg = <0x0 0xffab0080 0x0 0x20>; + }; + + qos_video_m0: qos@ffab8000 { + compatible = "rockchip,rk3399-qos", "syscon"; + reg = <0x0 0xffab8000 0x0 0x20>; + }; + + qos_video_m1_r: qos@ffac0000 { + compatible = "rockchip,rk3399-qos", "syscon"; + reg = <0x0 0xffac0000 0x0 0x20>; + }; + + qos_video_m1_w: qos@ffac0080 { + compatible = "rockchip,rk3399-qos", "syscon"; + reg = <0x0 0xffac0080 0x0 0x20>; + }; + + power-management@ff310000 { + compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; + reg = <0x0 0xff310000 0x0 0x1000>; + + power-controller { + compatible = "rockchip,rk3399-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* These power domains are grouped by VD_CENTER */ + power-domain@RK3399_PD_IEP { + reg = <RK3399_PD_IEP>; + clocks = <&cru ACLK_IEP>, + <&cru HCLK_IEP>; + pm_qos = <&qos_iep>; + #power-domain-cells = <0>; + }; + power-domain@RK3399_PD_RGA { + reg = <RK3399_PD_RGA>; + clocks = <&cru ACLK_RGA>, + <&cru HCLK_RGA>; + pm_qos = <&qos_rga_r>, + <&qos_rga_w>; + #power-domain-cells = <0>; + }; + power-domain@RK3399_PD_VCODEC { + reg = <RK3399_PD_VCODEC>; + clocks = <&cru ACLK_VCODEC>, + <&cru HCLK_VCODEC>; + pm_qos = <&qos_video_m0>; + #power-domain-cells = <0>; + }; + power-domain@RK3399_PD_VDU { + reg = <RK3399_PD_VDU>; + clocks = <&cru ACLK_VDU>, + <&cru HCLK_VDU>; + pm_qos = <&qos_video_m1_r>, + <&qos_video_m1_w>; + #power-domain-cells = <0>; + }; + power-domain@RK3399_PD_VIO { + reg = <RK3399_PD_VIO>; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3399_PD_HDCP { + reg = <RK3399_PD_HDCP>; + clocks = <&cru ACLK_HDCP>, + <&cru HCLK_HDCP>, + <&cru PCLK_HDCP>; + pm_qos = <&qos_hdcp>; + #power-domain-cells = <0>; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt deleted file mode 100644 index 8304eceb62e4..000000000000 --- a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt +++ /dev/null @@ -1,136 +0,0 @@ -* Rockchip Power Domains - -Rockchip processors include support for multiple power domains which can be -powered up/down by software based on different application scenes to save power. - -Required properties for power domain controller: -- compatible: Should be one of the following. - "rockchip,px30-power-controller" - for PX30 SoCs. - "rockchip,rk3036-power-controller" - for RK3036 SoCs. - "rockchip,rk3066-power-controller" - for RK3066 SoCs. - "rockchip,rk3128-power-controller" - for RK3128 SoCs. - "rockchip,rk3188-power-controller" - for RK3188 SoCs. - "rockchip,rk3228-power-controller" - for RK3228 SoCs. - "rockchip,rk3288-power-controller" - for RK3288 SoCs. - "rockchip,rk3328-power-controller" - for RK3328 SoCs. - "rockchip,rk3366-power-controller" - for RK3366 SoCs. - "rockchip,rk3368-power-controller" - for RK3368 SoCs. - "rockchip,rk3399-power-controller" - for RK3399 SoCs. -- #power-domain-cells: Number of cells in a power-domain specifier. - Should be 1 for multiple PM domains. -- #address-cells: Should be 1. -- #size-cells: Should be 0. - -Required properties for power domain sub nodes: -- reg: index of the power domain, should use macros in: - "include/dt-bindings/power/px30-power.h" - for PX30 type power domain. - "include/dt-bindings/power/rk3036-power.h" - for RK3036 type power domain. - "include/dt-bindings/power/rk3066-power.h" - for RK3066 type power domain. - "include/dt-bindings/power/rk3128-power.h" - for RK3128 type power domain. - "include/dt-bindings/power/rk3188-power.h" - for RK3188 type power domain. - "include/dt-bindings/power/rk3228-power.h" - for RK3228 type power domain. - "include/dt-bindings/power/rk3288-power.h" - for RK3288 type power domain. - "include/dt-bindings/power/rk3328-power.h" - for RK3328 type power domain. - "include/dt-bindings/power/rk3366-power.h" - for RK3366 type power domain. - "include/dt-bindings/power/rk3368-power.h" - for RK3368 type power domain. - "include/dt-bindings/power/rk3399-power.h" - for RK3399 type power domain. -- clocks (optional): phandles to clocks which need to be enabled while power domain - switches state. -- pm_qos (optional): phandles to qos blocks which need to be saved and restored - while power domain switches state. - -Qos Example: - - qos_gpu: qos_gpu@ffaf0000 { - compatible ="syscon"; - reg = <0x0 0xffaf0000 0x0 0x20>; - }; - -Example: - - power: power-controller { - compatible = "rockchip,rk3288-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - pd_gpu { - reg = <RK3288_PD_GPU>; - clocks = <&cru ACLK_GPU>; - pm_qos = <&qos_gpu>; - }; - }; - - power: power-controller { - compatible = "rockchip,rk3368-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - pd_gpu_1 { - reg = <RK3368_PD_GPU_1>; - clocks = <&cru ACLK_GPU_CFG>; - }; - }; - -Example 2: - power: power-controller { - compatible = "rockchip,rk3399-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - pd_vio { - #address-cells = <1>; - #size-cells = <0>; - reg = <RK3399_PD_VIO>; - - pd_vo { - #address-cells = <1>; - #size-cells = <0>; - reg = <RK3399_PD_VO>; - - pd_vopb { - reg = <RK3399_PD_VOPB>; - }; - - pd_vopl { - reg = <RK3399_PD_VOPL>; - }; - }; - }; - }; - -Node of a device using power domains must have a power-domains property, -containing a phandle to the power device node and an index specifying which -power domain to use. -The index should use macros in: - "include/dt-bindings/power/px30-power.h" - for px30 type power domain. - "include/dt-bindings/power/rk3036-power.h" - for rk3036 type power domain. - "include/dt-bindings/power/rk3128-power.h" - for rk3128 type power domain. - "include/dt-bindings/power/rk3128-power.h" - for rk3228 type power domain. - "include/dt-bindings/power/rk3288-power.h" - for rk3288 type power domain. - "include/dt-bindings/power/rk3328-power.h" - for rk3328 type power domain. - "include/dt-bindings/power/rk3366-power.h" - for rk3366 type power domain. - "include/dt-bindings/power/rk3368-power.h" - for rk3368 type power domain. - "include/dt-bindings/power/rk3399-power.h" - for rk3399 type power domain. - -Example of the node using power domain: - - node { - /* ... */ - power-domains = <&power RK3288_PD_GPU>; - /* ... */ - }; - - node { - /* ... */ - power-domains = <&power RK3368_PD_GPU_1>; - /* ... */ - }; - - node { - /* ... */ - power-domains = <&power RK3399_PD_VOPB>; - /* ... */ - }; -- 2.17.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v5 09/11] dt-bindings: power: rockchip: Convert to json-schema @ 2021-03-26 9:18 ` Elaine Zhang 0 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:18 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang, Enric Balletbo i Serra Convert the soc/rockchip/power_domain.txt binding document to json-schema and move to the power bindings directory. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- .../power/rockchip,power-controller.yaml | 291 ++++++++++++++++++ .../bindings/soc/rockchip/power_domain.txt | 136 -------- 2 files changed, 291 insertions(+), 136 deletions(-) create mode 100644 Documentation/devicetree/bindings/power/rockchip,power-controller.yaml delete mode 100644 Documentation/devicetree/bindings/soc/rockchip/power_domain.txt diff --git a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml new file mode 100644 index 000000000000..9fec9e227432 --- /dev/null +++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml @@ -0,0 +1,291 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/rockchip,power-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip Power Domains + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: | + Rockchip processors include support for multiple power domains which can be + powered up/down by software based on different application scenarios to save power. + + Power domains contained within power-controller node are generic power domain + providers documented in Documentation/devicetree/bindings/power/power-domain.yaml. + + IP cores belonging to a power domain should contain a "power-domains" + property that is a phandle for the power domain node representing the domain. + +properties: + $nodename: + const: power-controller + + compatible: + enum: + - rockchip,px30-power-controller + - rockchip,rk3036-power-controller + - rockchip,rk3066-power-controller + - rockchip,rk3128-power-controller + - rockchip,rk3188-power-controller + - rockchip,rk3228-power-controller + - rockchip,rk3288-power-controller + - rockchip,rk3328-power-controller + - rockchip,rk3366-power-controller + - rockchip,rk3368-power-controller + - rockchip,rk3399-power-controller + + "#power-domain-cells": + const: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + clocks: true + + assigned-clocks: + minItems: 1 + + assigned-clock-parents: + minItems: 1 + +patternProperties: + "^power-domain@[0-9a-f]+$": + type: object + description: | + Represents the power domains within the power controller node as documented + in Documentation/devicetree/bindings/power/power-domain.yaml. + + properties: + + "#power-domain-cells": + description: + Must be 0 for nodes representing a single PM domain and 1 for nodes + providing multiple PM domains. + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + reg: + maxItems: 1 + description: | + Power domain index. Valid values are defined in + "include/dt-bindings/power/px30-power.h" + "include/dt-bindings/power/rk3036-power.h" + "include/dt-bindings/power/rk3066-power.h" + "include/dt-bindings/power/rk3128-power.h" + "include/dt-bindings/power/rk3188-power.h" + "include/dt-bindings/power/rk3228-power.h" + "include/dt-bindings/power/rk3288-power.h" + "include/dt-bindings/power/rk3328-power.h" + "include/dt-bindings/power/rk3366-power.h" + "include/dt-bindings/power/rk3368-power.h" + "include/dt-bindings/power/rk3399-power.h" + + clocks: + description: | + A number of phandles to clocks that need to be enabled while power domain + switches state. + + pm_qos: + description: | + A number of phandles to qos blocks which need to be saved and restored + while power domain switches state. + + patternProperties: + "^power-domain@[0-9a-f]+$": + type: object + description: | + Represents a power domain child within a power domain parent node. + + properties: + + "#power-domain-cells": + description: + Must be 0 for nodes representing a single PM domain and 1 for nodes + providing multiple PM domains. + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + reg: + maxItems: 1 + + clocks: + description: | + A number of phandles to clocks that need to be enabled while power domain + switches state. + + pm_qos: + description: | + A number of phandles to qos blocks which need to be saved and restored + while power domain switches state. + + patternProperties: + "^power-domain@[0-9a-f]+$": + type: object + description: | + Represents a power domain child within a power domain parent node. + + properties: + + "#power-domain-cells": + description: + Must be 0 for nodes representing a single PM domain and 1 for nodes + providing multiple PM domains. + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + reg: + maxItems: 1 + + clocks: + description: | + A number of phandles to clocks that need to be enabled while power domain + switches state. + + pm_qos: + description: | + A number of phandles to qos blocks which need to be saved and restored + while power domain switches state. + + required: + - reg + + additionalProperties: false + + required: + - reg + + additionalProperties: false + + required: + - reg + + additionalProperties: false + +required: + - compatible + - "#power-domain-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/rk3399-cru.h> + #include <dt-bindings/power/rk3399-power.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + qos_hdcp: qos@ffa90000 { + compatible = "rockchip,rk3399-qos", "syscon"; + reg = <0x0 0xffa90000 0x0 0x20>; + }; + + qos_iep: qos@ffa98000 { + compatible = "rockchip,rk3399-qos", "syscon"; + reg = <0x0 0xffa98000 0x0 0x20>; + }; + + qos_rga_r: qos@ffab0000 { + compatible = "rockchip,rk3399-qos", "syscon"; + reg = <0x0 0xffab0000 0x0 0x20>; + }; + + qos_rga_w: qos@ffab0080 { + compatible = "rockchip,rk3399-qos", "syscon"; + reg = <0x0 0xffab0080 0x0 0x20>; + }; + + qos_video_m0: qos@ffab8000 { + compatible = "rockchip,rk3399-qos", "syscon"; + reg = <0x0 0xffab8000 0x0 0x20>; + }; + + qos_video_m1_r: qos@ffac0000 { + compatible = "rockchip,rk3399-qos", "syscon"; + reg = <0x0 0xffac0000 0x0 0x20>; + }; + + qos_video_m1_w: qos@ffac0080 { + compatible = "rockchip,rk3399-qos", "syscon"; + reg = <0x0 0xffac0080 0x0 0x20>; + }; + + power-management@ff310000 { + compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; + reg = <0x0 0xff310000 0x0 0x1000>; + + power-controller { + compatible = "rockchip,rk3399-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* These power domains are grouped by VD_CENTER */ + power-domain@RK3399_PD_IEP { + reg = <RK3399_PD_IEP>; + clocks = <&cru ACLK_IEP>, + <&cru HCLK_IEP>; + pm_qos = <&qos_iep>; + #power-domain-cells = <0>; + }; + power-domain@RK3399_PD_RGA { + reg = <RK3399_PD_RGA>; + clocks = <&cru ACLK_RGA>, + <&cru HCLK_RGA>; + pm_qos = <&qos_rga_r>, + <&qos_rga_w>; + #power-domain-cells = <0>; + }; + power-domain@RK3399_PD_VCODEC { + reg = <RK3399_PD_VCODEC>; + clocks = <&cru ACLK_VCODEC>, + <&cru HCLK_VCODEC>; + pm_qos = <&qos_video_m0>; + #power-domain-cells = <0>; + }; + power-domain@RK3399_PD_VDU { + reg = <RK3399_PD_VDU>; + clocks = <&cru ACLK_VDU>, + <&cru HCLK_VDU>; + pm_qos = <&qos_video_m1_r>, + <&qos_video_m1_w>; + #power-domain-cells = <0>; + }; + power-domain@RK3399_PD_VIO { + reg = <RK3399_PD_VIO>; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3399_PD_HDCP { + reg = <RK3399_PD_HDCP>; + clocks = <&cru ACLK_HDCP>, + <&cru HCLK_HDCP>, + <&cru PCLK_HDCP>; + pm_qos = <&qos_hdcp>; + #power-domain-cells = <0>; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt deleted file mode 100644 index 8304eceb62e4..000000000000 --- a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt +++ /dev/null @@ -1,136 +0,0 @@ -* Rockchip Power Domains - -Rockchip processors include support for multiple power domains which can be -powered up/down by software based on different application scenes to save power. - -Required properties for power domain controller: -- compatible: Should be one of the following. - "rockchip,px30-power-controller" - for PX30 SoCs. - "rockchip,rk3036-power-controller" - for RK3036 SoCs. - "rockchip,rk3066-power-controller" - for RK3066 SoCs. - "rockchip,rk3128-power-controller" - for RK3128 SoCs. - "rockchip,rk3188-power-controller" - for RK3188 SoCs. - "rockchip,rk3228-power-controller" - for RK3228 SoCs. - "rockchip,rk3288-power-controller" - for RK3288 SoCs. - "rockchip,rk3328-power-controller" - for RK3328 SoCs. - "rockchip,rk3366-power-controller" - for RK3366 SoCs. - "rockchip,rk3368-power-controller" - for RK3368 SoCs. - "rockchip,rk3399-power-controller" - for RK3399 SoCs. -- #power-domain-cells: Number of cells in a power-domain specifier. - Should be 1 for multiple PM domains. -- #address-cells: Should be 1. -- #size-cells: Should be 0. - -Required properties for power domain sub nodes: -- reg: index of the power domain, should use macros in: - "include/dt-bindings/power/px30-power.h" - for PX30 type power domain. - "include/dt-bindings/power/rk3036-power.h" - for RK3036 type power domain. - "include/dt-bindings/power/rk3066-power.h" - for RK3066 type power domain. - "include/dt-bindings/power/rk3128-power.h" - for RK3128 type power domain. - "include/dt-bindings/power/rk3188-power.h" - for RK3188 type power domain. - "include/dt-bindings/power/rk3228-power.h" - for RK3228 type power domain. - "include/dt-bindings/power/rk3288-power.h" - for RK3288 type power domain. - "include/dt-bindings/power/rk3328-power.h" - for RK3328 type power domain. - "include/dt-bindings/power/rk3366-power.h" - for RK3366 type power domain. - "include/dt-bindings/power/rk3368-power.h" - for RK3368 type power domain. - "include/dt-bindings/power/rk3399-power.h" - for RK3399 type power domain. -- clocks (optional): phandles to clocks which need to be enabled while power domain - switches state. -- pm_qos (optional): phandles to qos blocks which need to be saved and restored - while power domain switches state. - -Qos Example: - - qos_gpu: qos_gpu@ffaf0000 { - compatible ="syscon"; - reg = <0x0 0xffaf0000 0x0 0x20>; - }; - -Example: - - power: power-controller { - compatible = "rockchip,rk3288-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - pd_gpu { - reg = <RK3288_PD_GPU>; - clocks = <&cru ACLK_GPU>; - pm_qos = <&qos_gpu>; - }; - }; - - power: power-controller { - compatible = "rockchip,rk3368-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - pd_gpu_1 { - reg = <RK3368_PD_GPU_1>; - clocks = <&cru ACLK_GPU_CFG>; - }; - }; - -Example 2: - power: power-controller { - compatible = "rockchip,rk3399-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - pd_vio { - #address-cells = <1>; - #size-cells = <0>; - reg = <RK3399_PD_VIO>; - - pd_vo { - #address-cells = <1>; - #size-cells = <0>; - reg = <RK3399_PD_VO>; - - pd_vopb { - reg = <RK3399_PD_VOPB>; - }; - - pd_vopl { - reg = <RK3399_PD_VOPL>; - }; - }; - }; - }; - -Node of a device using power domains must have a power-domains property, -containing a phandle to the power device node and an index specifying which -power domain to use. -The index should use macros in: - "include/dt-bindings/power/px30-power.h" - for px30 type power domain. - "include/dt-bindings/power/rk3036-power.h" - for rk3036 type power domain. - "include/dt-bindings/power/rk3128-power.h" - for rk3128 type power domain. - "include/dt-bindings/power/rk3128-power.h" - for rk3228 type power domain. - "include/dt-bindings/power/rk3288-power.h" - for rk3288 type power domain. - "include/dt-bindings/power/rk3328-power.h" - for rk3328 type power domain. - "include/dt-bindings/power/rk3366-power.h" - for rk3366 type power domain. - "include/dt-bindings/power/rk3368-power.h" - for rk3368 type power domain. - "include/dt-bindings/power/rk3399-power.h" - for rk3399 type power domain. - -Example of the node using power domain: - - node { - /* ... */ - power-domains = <&power RK3288_PD_GPU>; - /* ... */ - }; - - node { - /* ... */ - power-domains = <&power RK3368_PD_GPU_1>; - /* ... */ - }; - - node { - /* ... */ - power-domains = <&power RK3399_PD_VOPB>; - /* ... */ - }; -- 2.17.1 ^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v5 09/11] dt-bindings: power: rockchip: Convert to json-schema @ 2021-03-26 9:18 ` Elaine Zhang 0 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:18 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang, Enric Balletbo i Serra Convert the soc/rockchip/power_domain.txt binding document to json-schema and move to the power bindings directory. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- .../power/rockchip,power-controller.yaml | 291 ++++++++++++++++++ .../bindings/soc/rockchip/power_domain.txt | 136 -------- 2 files changed, 291 insertions(+), 136 deletions(-) create mode 100644 Documentation/devicetree/bindings/power/rockchip,power-controller.yaml delete mode 100644 Documentation/devicetree/bindings/soc/rockchip/power_domain.txt diff --git a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml new file mode 100644 index 000000000000..9fec9e227432 --- /dev/null +++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml @@ -0,0 +1,291 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/rockchip,power-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip Power Domains + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: | + Rockchip processors include support for multiple power domains which can be + powered up/down by software based on different application scenarios to save power. + + Power domains contained within power-controller node are generic power domain + providers documented in Documentation/devicetree/bindings/power/power-domain.yaml. + + IP cores belonging to a power domain should contain a "power-domains" + property that is a phandle for the power domain node representing the domain. + +properties: + $nodename: + const: power-controller + + compatible: + enum: + - rockchip,px30-power-controller + - rockchip,rk3036-power-controller + - rockchip,rk3066-power-controller + - rockchip,rk3128-power-controller + - rockchip,rk3188-power-controller + - rockchip,rk3228-power-controller + - rockchip,rk3288-power-controller + - rockchip,rk3328-power-controller + - rockchip,rk3366-power-controller + - rockchip,rk3368-power-controller + - rockchip,rk3399-power-controller + + "#power-domain-cells": + const: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + clocks: true + + assigned-clocks: + minItems: 1 + + assigned-clock-parents: + minItems: 1 + +patternProperties: + "^power-domain@[0-9a-f]+$": + type: object + description: | + Represents the power domains within the power controller node as documented + in Documentation/devicetree/bindings/power/power-domain.yaml. + + properties: + + "#power-domain-cells": + description: + Must be 0 for nodes representing a single PM domain and 1 for nodes + providing multiple PM domains. + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + reg: + maxItems: 1 + description: | + Power domain index. Valid values are defined in + "include/dt-bindings/power/px30-power.h" + "include/dt-bindings/power/rk3036-power.h" + "include/dt-bindings/power/rk3066-power.h" + "include/dt-bindings/power/rk3128-power.h" + "include/dt-bindings/power/rk3188-power.h" + "include/dt-bindings/power/rk3228-power.h" + "include/dt-bindings/power/rk3288-power.h" + "include/dt-bindings/power/rk3328-power.h" + "include/dt-bindings/power/rk3366-power.h" + "include/dt-bindings/power/rk3368-power.h" + "include/dt-bindings/power/rk3399-power.h" + + clocks: + description: | + A number of phandles to clocks that need to be enabled while power domain + switches state. + + pm_qos: + description: | + A number of phandles to qos blocks which need to be saved and restored + while power domain switches state. + + patternProperties: + "^power-domain@[0-9a-f]+$": + type: object + description: | + Represents a power domain child within a power domain parent node. + + properties: + + "#power-domain-cells": + description: + Must be 0 for nodes representing a single PM domain and 1 for nodes + providing multiple PM domains. + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + reg: + maxItems: 1 + + clocks: + description: | + A number of phandles to clocks that need to be enabled while power domain + switches state. + + pm_qos: + description: | + A number of phandles to qos blocks which need to be saved and restored + while power domain switches state. + + patternProperties: + "^power-domain@[0-9a-f]+$": + type: object + description: | + Represents a power domain child within a power domain parent node. + + properties: + + "#power-domain-cells": + description: + Must be 0 for nodes representing a single PM domain and 1 for nodes + providing multiple PM domains. + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + reg: + maxItems: 1 + + clocks: + description: | + A number of phandles to clocks that need to be enabled while power domain + switches state. + + pm_qos: + description: | + A number of phandles to qos blocks which need to be saved and restored + while power domain switches state. + + required: + - reg + + additionalProperties: false + + required: + - reg + + additionalProperties: false + + required: + - reg + + additionalProperties: false + +required: + - compatible + - "#power-domain-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/rk3399-cru.h> + #include <dt-bindings/power/rk3399-power.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + qos_hdcp: qos@ffa90000 { + compatible = "rockchip,rk3399-qos", "syscon"; + reg = <0x0 0xffa90000 0x0 0x20>; + }; + + qos_iep: qos@ffa98000 { + compatible = "rockchip,rk3399-qos", "syscon"; + reg = <0x0 0xffa98000 0x0 0x20>; + }; + + qos_rga_r: qos@ffab0000 { + compatible = "rockchip,rk3399-qos", "syscon"; + reg = <0x0 0xffab0000 0x0 0x20>; + }; + + qos_rga_w: qos@ffab0080 { + compatible = "rockchip,rk3399-qos", "syscon"; + reg = <0x0 0xffab0080 0x0 0x20>; + }; + + qos_video_m0: qos@ffab8000 { + compatible = "rockchip,rk3399-qos", "syscon"; + reg = <0x0 0xffab8000 0x0 0x20>; + }; + + qos_video_m1_r: qos@ffac0000 { + compatible = "rockchip,rk3399-qos", "syscon"; + reg = <0x0 0xffac0000 0x0 0x20>; + }; + + qos_video_m1_w: qos@ffac0080 { + compatible = "rockchip,rk3399-qos", "syscon"; + reg = <0x0 0xffac0080 0x0 0x20>; + }; + + power-management@ff310000 { + compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; + reg = <0x0 0xff310000 0x0 0x1000>; + + power-controller { + compatible = "rockchip,rk3399-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* These power domains are grouped by VD_CENTER */ + power-domain@RK3399_PD_IEP { + reg = <RK3399_PD_IEP>; + clocks = <&cru ACLK_IEP>, + <&cru HCLK_IEP>; + pm_qos = <&qos_iep>; + #power-domain-cells = <0>; + }; + power-domain@RK3399_PD_RGA { + reg = <RK3399_PD_RGA>; + clocks = <&cru ACLK_RGA>, + <&cru HCLK_RGA>; + pm_qos = <&qos_rga_r>, + <&qos_rga_w>; + #power-domain-cells = <0>; + }; + power-domain@RK3399_PD_VCODEC { + reg = <RK3399_PD_VCODEC>; + clocks = <&cru ACLK_VCODEC>, + <&cru HCLK_VCODEC>; + pm_qos = <&qos_video_m0>; + #power-domain-cells = <0>; + }; + power-domain@RK3399_PD_VDU { + reg = <RK3399_PD_VDU>; + clocks = <&cru ACLK_VDU>, + <&cru HCLK_VDU>; + pm_qos = <&qos_video_m1_r>, + <&qos_video_m1_w>; + #power-domain-cells = <0>; + }; + power-domain@RK3399_PD_VIO { + reg = <RK3399_PD_VIO>; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3399_PD_HDCP { + reg = <RK3399_PD_HDCP>; + clocks = <&cru ACLK_HDCP>, + <&cru HCLK_HDCP>, + <&cru PCLK_HDCP>; + pm_qos = <&qos_hdcp>; + #power-domain-cells = <0>; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt deleted file mode 100644 index 8304eceb62e4..000000000000 --- a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt +++ /dev/null @@ -1,136 +0,0 @@ -* Rockchip Power Domains - -Rockchip processors include support for multiple power domains which can be -powered up/down by software based on different application scenes to save power. - -Required properties for power domain controller: -- compatible: Should be one of the following. - "rockchip,px30-power-controller" - for PX30 SoCs. - "rockchip,rk3036-power-controller" - for RK3036 SoCs. - "rockchip,rk3066-power-controller" - for RK3066 SoCs. - "rockchip,rk3128-power-controller" - for RK3128 SoCs. - "rockchip,rk3188-power-controller" - for RK3188 SoCs. - "rockchip,rk3228-power-controller" - for RK3228 SoCs. - "rockchip,rk3288-power-controller" - for RK3288 SoCs. - "rockchip,rk3328-power-controller" - for RK3328 SoCs. - "rockchip,rk3366-power-controller" - for RK3366 SoCs. - "rockchip,rk3368-power-controller" - for RK3368 SoCs. - "rockchip,rk3399-power-controller" - for RK3399 SoCs. -- #power-domain-cells: Number of cells in a power-domain specifier. - Should be 1 for multiple PM domains. -- #address-cells: Should be 1. -- #size-cells: Should be 0. - -Required properties for power domain sub nodes: -- reg: index of the power domain, should use macros in: - "include/dt-bindings/power/px30-power.h" - for PX30 type power domain. - "include/dt-bindings/power/rk3036-power.h" - for RK3036 type power domain. - "include/dt-bindings/power/rk3066-power.h" - for RK3066 type power domain. - "include/dt-bindings/power/rk3128-power.h" - for RK3128 type power domain. - "include/dt-bindings/power/rk3188-power.h" - for RK3188 type power domain. - "include/dt-bindings/power/rk3228-power.h" - for RK3228 type power domain. - "include/dt-bindings/power/rk3288-power.h" - for RK3288 type power domain. - "include/dt-bindings/power/rk3328-power.h" - for RK3328 type power domain. - "include/dt-bindings/power/rk3366-power.h" - for RK3366 type power domain. - "include/dt-bindings/power/rk3368-power.h" - for RK3368 type power domain. - "include/dt-bindings/power/rk3399-power.h" - for RK3399 type power domain. -- clocks (optional): phandles to clocks which need to be enabled while power domain - switches state. -- pm_qos (optional): phandles to qos blocks which need to be saved and restored - while power domain switches state. - -Qos Example: - - qos_gpu: qos_gpu@ffaf0000 { - compatible ="syscon"; - reg = <0x0 0xffaf0000 0x0 0x20>; - }; - -Example: - - power: power-controller { - compatible = "rockchip,rk3288-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - pd_gpu { - reg = <RK3288_PD_GPU>; - clocks = <&cru ACLK_GPU>; - pm_qos = <&qos_gpu>; - }; - }; - - power: power-controller { - compatible = "rockchip,rk3368-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - pd_gpu_1 { - reg = <RK3368_PD_GPU_1>; - clocks = <&cru ACLK_GPU_CFG>; - }; - }; - -Example 2: - power: power-controller { - compatible = "rockchip,rk3399-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - pd_vio { - #address-cells = <1>; - #size-cells = <0>; - reg = <RK3399_PD_VIO>; - - pd_vo { - #address-cells = <1>; - #size-cells = <0>; - reg = <RK3399_PD_VO>; - - pd_vopb { - reg = <RK3399_PD_VOPB>; - }; - - pd_vopl { - reg = <RK3399_PD_VOPL>; - }; - }; - }; - }; - -Node of a device using power domains must have a power-domains property, -containing a phandle to the power device node and an index specifying which -power domain to use. -The index should use macros in: - "include/dt-bindings/power/px30-power.h" - for px30 type power domain. - "include/dt-bindings/power/rk3036-power.h" - for rk3036 type power domain. - "include/dt-bindings/power/rk3128-power.h" - for rk3128 type power domain. - "include/dt-bindings/power/rk3128-power.h" - for rk3228 type power domain. - "include/dt-bindings/power/rk3288-power.h" - for rk3288 type power domain. - "include/dt-bindings/power/rk3328-power.h" - for rk3328 type power domain. - "include/dt-bindings/power/rk3366-power.h" - for rk3366 type power domain. - "include/dt-bindings/power/rk3368-power.h" - for rk3368 type power domain. - "include/dt-bindings/power/rk3399-power.h" - for rk3399 type power domain. - -Example of the node using power domain: - - node { - /* ... */ - power-domains = <&power RK3288_PD_GPU>; - /* ... */ - }; - - node { - /* ... */ - power-domains = <&power RK3368_PD_GPU_1>; - /* ... */ - }; - - node { - /* ... */ - power-domains = <&power RK3399_PD_VOPB>; - /* ... */ - }; -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 75+ messages in thread
* Re: [PATCH v5 09/11] dt-bindings: power: rockchip: Convert to json-schema 2021-03-26 9:18 ` Elaine Zhang (?) @ 2021-03-26 9:51 ` Heiko Stübner -1 siblings, 0 replies; 75+ messages in thread From: Heiko Stübner @ 2021-03-26 9:51 UTC (permalink / raw) To: robh+dt, Elaine Zhang Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang, Enric Balletbo i Serra Am Freitag, 26. März 2021, 10:18:03 CET schrieb Elaine Zhang: > Convert the soc/rockchip/power_domain.txt binding document to > json-schema and move to the power bindings directory. > > Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> If Enric is the original author of this patch, maybe this needs a matching "From: ... " line? Thanks Heiko > --- > .../power/rockchip,power-controller.yaml | 291 ++++++++++++++++++ > .../bindings/soc/rockchip/power_domain.txt | 136 -------- > 2 files changed, 291 insertions(+), 136 deletions(-) > create mode 100644 Documentation/devicetree/bindings/power/rockchip,power-controller.yaml > delete mode 100644 Documentation/devicetree/bindings/soc/rockchip/power_domain.txt > > diff --git a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml > new file mode 100644 > index 000000000000..9fec9e227432 > --- /dev/null > +++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml > @@ -0,0 +1,291 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/power/rockchip,power-controller.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Rockchip Power Domains > + > +maintainers: > + - Elaine Zhang <zhangqing@rock-chips.com> > + - Heiko Stuebner <heiko@sntech.de> > + > +description: | > + Rockchip processors include support for multiple power domains which can be > + powered up/down by software based on different application scenarios to save power. > + > + Power domains contained within power-controller node are generic power domain > + providers documented in Documentation/devicetree/bindings/power/power-domain.yaml. > + > + IP cores belonging to a power domain should contain a "power-domains" > + property that is a phandle for the power domain node representing the domain. > + > +properties: > + $nodename: > + const: power-controller > + > + compatible: > + enum: > + - rockchip,px30-power-controller > + - rockchip,rk3036-power-controller > + - rockchip,rk3066-power-controller > + - rockchip,rk3128-power-controller > + - rockchip,rk3188-power-controller > + - rockchip,rk3228-power-controller > + - rockchip,rk3288-power-controller > + - rockchip,rk3328-power-controller > + - rockchip,rk3366-power-controller > + - rockchip,rk3368-power-controller > + - rockchip,rk3399-power-controller > + > + "#power-domain-cells": > + const: 1 > + > + "#address-cells": > + const: 1 > + > + "#size-cells": > + const: 0 > + > + clocks: true > + > + assigned-clocks: > + minItems: 1 > + > + assigned-clock-parents: > + minItems: 1 > + > +patternProperties: > + "^power-domain@[0-9a-f]+$": > + type: object > + description: | > + Represents the power domains within the power controller node as documented > + in Documentation/devicetree/bindings/power/power-domain.yaml. > + > + properties: > + > + "#power-domain-cells": > + description: > + Must be 0 for nodes representing a single PM domain and 1 for nodes > + providing multiple PM domains. > + > + "#address-cells": > + const: 1 > + > + "#size-cells": > + const: 0 > + > + reg: > + maxItems: 1 > + description: | > + Power domain index. Valid values are defined in > + "include/dt-bindings/power/px30-power.h" > + "include/dt-bindings/power/rk3036-power.h" > + "include/dt-bindings/power/rk3066-power.h" > + "include/dt-bindings/power/rk3128-power.h" > + "include/dt-bindings/power/rk3188-power.h" > + "include/dt-bindings/power/rk3228-power.h" > + "include/dt-bindings/power/rk3288-power.h" > + "include/dt-bindings/power/rk3328-power.h" > + "include/dt-bindings/power/rk3366-power.h" > + "include/dt-bindings/power/rk3368-power.h" > + "include/dt-bindings/power/rk3399-power.h" > + > + clocks: > + description: | > + A number of phandles to clocks that need to be enabled while power domain > + switches state. > + > + pm_qos: > + description: | > + A number of phandles to qos blocks which need to be saved and restored > + while power domain switches state. > + > + patternProperties: > + "^power-domain@[0-9a-f]+$": > + type: object > + description: | > + Represents a power domain child within a power domain parent node. > + > + properties: > + > + "#power-domain-cells": > + description: > + Must be 0 for nodes representing a single PM domain and 1 for nodes > + providing multiple PM domains. > + > + "#address-cells": > + const: 1 > + > + "#size-cells": > + const: 0 > + > + reg: > + maxItems: 1 > + > + clocks: > + description: | > + A number of phandles to clocks that need to be enabled while power domain > + switches state. > + > + pm_qos: > + description: | > + A number of phandles to qos blocks which need to be saved and restored > + while power domain switches state. > + > + patternProperties: > + "^power-domain@[0-9a-f]+$": > + type: object > + description: | > + Represents a power domain child within a power domain parent node. > + > + properties: > + > + "#power-domain-cells": > + description: > + Must be 0 for nodes representing a single PM domain and 1 for nodes > + providing multiple PM domains. > + > + "#address-cells": > + const: 1 > + > + "#size-cells": > + const: 0 > + > + reg: > + maxItems: 1 > + > + clocks: > + description: | > + A number of phandles to clocks that need to be enabled while power domain > + switches state. > + > + pm_qos: > + description: | > + A number of phandles to qos blocks which need to be saved and restored > + while power domain switches state. > + > + required: > + - reg > + > + additionalProperties: false > + > + required: > + - reg > + > + additionalProperties: false > + > + required: > + - reg > + > + additionalProperties: false > + > +required: > + - compatible > + - "#power-domain-cells" > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/rk3399-cru.h> > + #include <dt-bindings/power/rk3399-power.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + qos_hdcp: qos@ffa90000 { > + compatible = "rockchip,rk3399-qos", "syscon"; > + reg = <0x0 0xffa90000 0x0 0x20>; > + }; > + > + qos_iep: qos@ffa98000 { > + compatible = "rockchip,rk3399-qos", "syscon"; > + reg = <0x0 0xffa98000 0x0 0x20>; > + }; > + > + qos_rga_r: qos@ffab0000 { > + compatible = "rockchip,rk3399-qos", "syscon"; > + reg = <0x0 0xffab0000 0x0 0x20>; > + }; > + > + qos_rga_w: qos@ffab0080 { > + compatible = "rockchip,rk3399-qos", "syscon"; > + reg = <0x0 0xffab0080 0x0 0x20>; > + }; > + > + qos_video_m0: qos@ffab8000 { > + compatible = "rockchip,rk3399-qos", "syscon"; > + reg = <0x0 0xffab8000 0x0 0x20>; > + }; > + > + qos_video_m1_r: qos@ffac0000 { > + compatible = "rockchip,rk3399-qos", "syscon"; > + reg = <0x0 0xffac0000 0x0 0x20>; > + }; > + > + qos_video_m1_w: qos@ffac0080 { > + compatible = "rockchip,rk3399-qos", "syscon"; > + reg = <0x0 0xffac0080 0x0 0x20>; > + }; > + > + power-management@ff310000 { > + compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; > + reg = <0x0 0xff310000 0x0 0x1000>; > + > + power-controller { > + compatible = "rockchip,rk3399-power-controller"; > + #power-domain-cells = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + /* These power domains are grouped by VD_CENTER */ > + power-domain@RK3399_PD_IEP { > + reg = <RK3399_PD_IEP>; > + clocks = <&cru ACLK_IEP>, > + <&cru HCLK_IEP>; > + pm_qos = <&qos_iep>; > + #power-domain-cells = <0>; > + }; > + power-domain@RK3399_PD_RGA { > + reg = <RK3399_PD_RGA>; > + clocks = <&cru ACLK_RGA>, > + <&cru HCLK_RGA>; > + pm_qos = <&qos_rga_r>, > + <&qos_rga_w>; > + #power-domain-cells = <0>; > + }; > + power-domain@RK3399_PD_VCODEC { > + reg = <RK3399_PD_VCODEC>; > + clocks = <&cru ACLK_VCODEC>, > + <&cru HCLK_VCODEC>; > + pm_qos = <&qos_video_m0>; > + #power-domain-cells = <0>; > + }; > + power-domain@RK3399_PD_VDU { > + reg = <RK3399_PD_VDU>; > + clocks = <&cru ACLK_VDU>, > + <&cru HCLK_VDU>; > + pm_qos = <&qos_video_m1_r>, > + <&qos_video_m1_w>; > + #power-domain-cells = <0>; > + }; > + power-domain@RK3399_PD_VIO { > + reg = <RK3399_PD_VIO>; > + #power-domain-cells = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + power-domain@RK3399_PD_HDCP { > + reg = <RK3399_PD_HDCP>; > + clocks = <&cru ACLK_HDCP>, > + <&cru HCLK_HDCP>, > + <&cru PCLK_HDCP>; > + pm_qos = <&qos_hdcp>; > + #power-domain-cells = <0>; > + }; > + }; > + }; > + }; > + }; > diff --git a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt > deleted file mode 100644 > index 8304eceb62e4..000000000000 > --- a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt > +++ /dev/null > @@ -1,136 +0,0 @@ > -* Rockchip Power Domains > - > -Rockchip processors include support for multiple power domains which can be > -powered up/down by software based on different application scenes to save power. > - > -Required properties for power domain controller: > -- compatible: Should be one of the following. > - "rockchip,px30-power-controller" - for PX30 SoCs. > - "rockchip,rk3036-power-controller" - for RK3036 SoCs. > - "rockchip,rk3066-power-controller" - for RK3066 SoCs. > - "rockchip,rk3128-power-controller" - for RK3128 SoCs. > - "rockchip,rk3188-power-controller" - for RK3188 SoCs. > - "rockchip,rk3228-power-controller" - for RK3228 SoCs. > - "rockchip,rk3288-power-controller" - for RK3288 SoCs. > - "rockchip,rk3328-power-controller" - for RK3328 SoCs. > - "rockchip,rk3366-power-controller" - for RK3366 SoCs. > - "rockchip,rk3368-power-controller" - for RK3368 SoCs. > - "rockchip,rk3399-power-controller" - for RK3399 SoCs. > -- #power-domain-cells: Number of cells in a power-domain specifier. > - Should be 1 for multiple PM domains. > -- #address-cells: Should be 1. > -- #size-cells: Should be 0. > - > -Required properties for power domain sub nodes: > -- reg: index of the power domain, should use macros in: > - "include/dt-bindings/power/px30-power.h" - for PX30 type power domain. > - "include/dt-bindings/power/rk3036-power.h" - for RK3036 type power domain. > - "include/dt-bindings/power/rk3066-power.h" - for RK3066 type power domain. > - "include/dt-bindings/power/rk3128-power.h" - for RK3128 type power domain. > - "include/dt-bindings/power/rk3188-power.h" - for RK3188 type power domain. > - "include/dt-bindings/power/rk3228-power.h" - for RK3228 type power domain. > - "include/dt-bindings/power/rk3288-power.h" - for RK3288 type power domain. > - "include/dt-bindings/power/rk3328-power.h" - for RK3328 type power domain. > - "include/dt-bindings/power/rk3366-power.h" - for RK3366 type power domain. > - "include/dt-bindings/power/rk3368-power.h" - for RK3368 type power domain. > - "include/dt-bindings/power/rk3399-power.h" - for RK3399 type power domain. > -- clocks (optional): phandles to clocks which need to be enabled while power domain > - switches state. > -- pm_qos (optional): phandles to qos blocks which need to be saved and restored > - while power domain switches state. > - > -Qos Example: > - > - qos_gpu: qos_gpu@ffaf0000 { > - compatible ="syscon"; > - reg = <0x0 0xffaf0000 0x0 0x20>; > - }; > - > -Example: > - > - power: power-controller { > - compatible = "rockchip,rk3288-power-controller"; > - #power-domain-cells = <1>; > - #address-cells = <1>; > - #size-cells = <0>; > - > - pd_gpu { > - reg = <RK3288_PD_GPU>; > - clocks = <&cru ACLK_GPU>; > - pm_qos = <&qos_gpu>; > - }; > - }; > - > - power: power-controller { > - compatible = "rockchip,rk3368-power-controller"; > - #power-domain-cells = <1>; > - #address-cells = <1>; > - #size-cells = <0>; > - > - pd_gpu_1 { > - reg = <RK3368_PD_GPU_1>; > - clocks = <&cru ACLK_GPU_CFG>; > - }; > - }; > - > -Example 2: > - power: power-controller { > - compatible = "rockchip,rk3399-power-controller"; > - #power-domain-cells = <1>; > - #address-cells = <1>; > - #size-cells = <0>; > - > - pd_vio { > - #address-cells = <1>; > - #size-cells = <0>; > - reg = <RK3399_PD_VIO>; > - > - pd_vo { > - #address-cells = <1>; > - #size-cells = <0>; > - reg = <RK3399_PD_VO>; > - > - pd_vopb { > - reg = <RK3399_PD_VOPB>; > - }; > - > - pd_vopl { > - reg = <RK3399_PD_VOPL>; > - }; > - }; > - }; > - }; > - > -Node of a device using power domains must have a power-domains property, > -containing a phandle to the power device node and an index specifying which > -power domain to use. > -The index should use macros in: > - "include/dt-bindings/power/px30-power.h" - for px30 type power domain. > - "include/dt-bindings/power/rk3036-power.h" - for rk3036 type power domain. > - "include/dt-bindings/power/rk3128-power.h" - for rk3128 type power domain. > - "include/dt-bindings/power/rk3128-power.h" - for rk3228 type power domain. > - "include/dt-bindings/power/rk3288-power.h" - for rk3288 type power domain. > - "include/dt-bindings/power/rk3328-power.h" - for rk3328 type power domain. > - "include/dt-bindings/power/rk3366-power.h" - for rk3366 type power domain. > - "include/dt-bindings/power/rk3368-power.h" - for rk3368 type power domain. > - "include/dt-bindings/power/rk3399-power.h" - for rk3399 type power domain. > - > -Example of the node using power domain: > - > - node { > - /* ... */ > - power-domains = <&power RK3288_PD_GPU>; > - /* ... */ > - }; > - > - node { > - /* ... */ > - power-domains = <&power RK3368_PD_GPU_1>; > - /* ... */ > - }; > - > - node { > - /* ... */ > - power-domains = <&power RK3399_PD_VOPB>; > - /* ... */ > - }; > _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v5 09/11] dt-bindings: power: rockchip: Convert to json-schema @ 2021-03-26 9:51 ` Heiko Stübner 0 siblings, 0 replies; 75+ messages in thread From: Heiko Stübner @ 2021-03-26 9:51 UTC (permalink / raw) To: robh+dt, Elaine Zhang Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang, Enric Balletbo i Serra Am Freitag, 26. März 2021, 10:18:03 CET schrieb Elaine Zhang: > Convert the soc/rockchip/power_domain.txt binding document to > json-schema and move to the power bindings directory. > > Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> If Enric is the original author of this patch, maybe this needs a matching "From: ... " line? Thanks Heiko > --- > .../power/rockchip,power-controller.yaml | 291 ++++++++++++++++++ > .../bindings/soc/rockchip/power_domain.txt | 136 -------- > 2 files changed, 291 insertions(+), 136 deletions(-) > create mode 100644 Documentation/devicetree/bindings/power/rockchip,power-controller.yaml > delete mode 100644 Documentation/devicetree/bindings/soc/rockchip/power_domain.txt > > diff --git a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml > new file mode 100644 > index 000000000000..9fec9e227432 > --- /dev/null > +++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml > @@ -0,0 +1,291 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/power/rockchip,power-controller.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Rockchip Power Domains > + > +maintainers: > + - Elaine Zhang <zhangqing@rock-chips.com> > + - Heiko Stuebner <heiko@sntech.de> > + > +description: | > + Rockchip processors include support for multiple power domains which can be > + powered up/down by software based on different application scenarios to save power. > + > + Power domains contained within power-controller node are generic power domain > + providers documented in Documentation/devicetree/bindings/power/power-domain.yaml. > + > + IP cores belonging to a power domain should contain a "power-domains" > + property that is a phandle for the power domain node representing the domain. > + > +properties: > + $nodename: > + const: power-controller > + > + compatible: > + enum: > + - rockchip,px30-power-controller > + - rockchip,rk3036-power-controller > + - rockchip,rk3066-power-controller > + - rockchip,rk3128-power-controller > + - rockchip,rk3188-power-controller > + - rockchip,rk3228-power-controller > + - rockchip,rk3288-power-controller > + - rockchip,rk3328-power-controller > + - rockchip,rk3366-power-controller > + - rockchip,rk3368-power-controller > + - rockchip,rk3399-power-controller > + > + "#power-domain-cells": > + const: 1 > + > + "#address-cells": > + const: 1 > + > + "#size-cells": > + const: 0 > + > + clocks: true > + > + assigned-clocks: > + minItems: 1 > + > + assigned-clock-parents: > + minItems: 1 > + > +patternProperties: > + "^power-domain@[0-9a-f]+$": > + type: object > + description: | > + Represents the power domains within the power controller node as documented > + in Documentation/devicetree/bindings/power/power-domain.yaml. > + > + properties: > + > + "#power-domain-cells": > + description: > + Must be 0 for nodes representing a single PM domain and 1 for nodes > + providing multiple PM domains. > + > + "#address-cells": > + const: 1 > + > + "#size-cells": > + const: 0 > + > + reg: > + maxItems: 1 > + description: | > + Power domain index. Valid values are defined in > + "include/dt-bindings/power/px30-power.h" > + "include/dt-bindings/power/rk3036-power.h" > + "include/dt-bindings/power/rk3066-power.h" > + "include/dt-bindings/power/rk3128-power.h" > + "include/dt-bindings/power/rk3188-power.h" > + "include/dt-bindings/power/rk3228-power.h" > + "include/dt-bindings/power/rk3288-power.h" > + "include/dt-bindings/power/rk3328-power.h" > + "include/dt-bindings/power/rk3366-power.h" > + "include/dt-bindings/power/rk3368-power.h" > + "include/dt-bindings/power/rk3399-power.h" > + > + clocks: > + description: | > + A number of phandles to clocks that need to be enabled while power domain > + switches state. > + > + pm_qos: > + description: | > + A number of phandles to qos blocks which need to be saved and restored > + while power domain switches state. > + > + patternProperties: > + "^power-domain@[0-9a-f]+$": > + type: object > + description: | > + Represents a power domain child within a power domain parent node. > + > + properties: > + > + "#power-domain-cells": > + description: > + Must be 0 for nodes representing a single PM domain and 1 for nodes > + providing multiple PM domains. > + > + "#address-cells": > + const: 1 > + > + "#size-cells": > + const: 0 > + > + reg: > + maxItems: 1 > + > + clocks: > + description: | > + A number of phandles to clocks that need to be enabled while power domain > + switches state. > + > + pm_qos: > + description: | > + A number of phandles to qos blocks which need to be saved and restored > + while power domain switches state. > + > + patternProperties: > + "^power-domain@[0-9a-f]+$": > + type: object > + description: | > + Represents a power domain child within a power domain parent node. > + > + properties: > + > + "#power-domain-cells": > + description: > + Must be 0 for nodes representing a single PM domain and 1 for nodes > + providing multiple PM domains. > + > + "#address-cells": > + const: 1 > + > + "#size-cells": > + const: 0 > + > + reg: > + maxItems: 1 > + > + clocks: > + description: | > + A number of phandles to clocks that need to be enabled while power domain > + switches state. > + > + pm_qos: > + description: | > + A number of phandles to qos blocks which need to be saved and restored > + while power domain switches state. > + > + required: > + - reg > + > + additionalProperties: false > + > + required: > + - reg > + > + additionalProperties: false > + > + required: > + - reg > + > + additionalProperties: false > + > +required: > + - compatible > + - "#power-domain-cells" > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/rk3399-cru.h> > + #include <dt-bindings/power/rk3399-power.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + qos_hdcp: qos@ffa90000 { > + compatible = "rockchip,rk3399-qos", "syscon"; > + reg = <0x0 0xffa90000 0x0 0x20>; > + }; > + > + qos_iep: qos@ffa98000 { > + compatible = "rockchip,rk3399-qos", "syscon"; > + reg = <0x0 0xffa98000 0x0 0x20>; > + }; > + > + qos_rga_r: qos@ffab0000 { > + compatible = "rockchip,rk3399-qos", "syscon"; > + reg = <0x0 0xffab0000 0x0 0x20>; > + }; > + > + qos_rga_w: qos@ffab0080 { > + compatible = "rockchip,rk3399-qos", "syscon"; > + reg = <0x0 0xffab0080 0x0 0x20>; > + }; > + > + qos_video_m0: qos@ffab8000 { > + compatible = "rockchip,rk3399-qos", "syscon"; > + reg = <0x0 0xffab8000 0x0 0x20>; > + }; > + > + qos_video_m1_r: qos@ffac0000 { > + compatible = "rockchip,rk3399-qos", "syscon"; > + reg = <0x0 0xffac0000 0x0 0x20>; > + }; > + > + qos_video_m1_w: qos@ffac0080 { > + compatible = "rockchip,rk3399-qos", "syscon"; > + reg = <0x0 0xffac0080 0x0 0x20>; > + }; > + > + power-management@ff310000 { > + compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; > + reg = <0x0 0xff310000 0x0 0x1000>; > + > + power-controller { > + compatible = "rockchip,rk3399-power-controller"; > + #power-domain-cells = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + /* These power domains are grouped by VD_CENTER */ > + power-domain@RK3399_PD_IEP { > + reg = <RK3399_PD_IEP>; > + clocks = <&cru ACLK_IEP>, > + <&cru HCLK_IEP>; > + pm_qos = <&qos_iep>; > + #power-domain-cells = <0>; > + }; > + power-domain@RK3399_PD_RGA { > + reg = <RK3399_PD_RGA>; > + clocks = <&cru ACLK_RGA>, > + <&cru HCLK_RGA>; > + pm_qos = <&qos_rga_r>, > + <&qos_rga_w>; > + #power-domain-cells = <0>; > + }; > + power-domain@RK3399_PD_VCODEC { > + reg = <RK3399_PD_VCODEC>; > + clocks = <&cru ACLK_VCODEC>, > + <&cru HCLK_VCODEC>; > + pm_qos = <&qos_video_m0>; > + #power-domain-cells = <0>; > + }; > + power-domain@RK3399_PD_VDU { > + reg = <RK3399_PD_VDU>; > + clocks = <&cru ACLK_VDU>, > + <&cru HCLK_VDU>; > + pm_qos = <&qos_video_m1_r>, > + <&qos_video_m1_w>; > + #power-domain-cells = <0>; > + }; > + power-domain@RK3399_PD_VIO { > + reg = <RK3399_PD_VIO>; > + #power-domain-cells = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + power-domain@RK3399_PD_HDCP { > + reg = <RK3399_PD_HDCP>; > + clocks = <&cru ACLK_HDCP>, > + <&cru HCLK_HDCP>, > + <&cru PCLK_HDCP>; > + pm_qos = <&qos_hdcp>; > + #power-domain-cells = <0>; > + }; > + }; > + }; > + }; > + }; > diff --git a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt > deleted file mode 100644 > index 8304eceb62e4..000000000000 > --- a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt > +++ /dev/null > @@ -1,136 +0,0 @@ > -* Rockchip Power Domains > - > -Rockchip processors include support for multiple power domains which can be > -powered up/down by software based on different application scenes to save power. > - > -Required properties for power domain controller: > -- compatible: Should be one of the following. > - "rockchip,px30-power-controller" - for PX30 SoCs. > - "rockchip,rk3036-power-controller" - for RK3036 SoCs. > - "rockchip,rk3066-power-controller" - for RK3066 SoCs. > - "rockchip,rk3128-power-controller" - for RK3128 SoCs. > - "rockchip,rk3188-power-controller" - for RK3188 SoCs. > - "rockchip,rk3228-power-controller" - for RK3228 SoCs. > - "rockchip,rk3288-power-controller" - for RK3288 SoCs. > - "rockchip,rk3328-power-controller" - for RK3328 SoCs. > - "rockchip,rk3366-power-controller" - for RK3366 SoCs. > - "rockchip,rk3368-power-controller" - for RK3368 SoCs. > - "rockchip,rk3399-power-controller" - for RK3399 SoCs. > -- #power-domain-cells: Number of cells in a power-domain specifier. > - Should be 1 for multiple PM domains. > -- #address-cells: Should be 1. > -- #size-cells: Should be 0. > - > -Required properties for power domain sub nodes: > -- reg: index of the power domain, should use macros in: > - "include/dt-bindings/power/px30-power.h" - for PX30 type power domain. > - "include/dt-bindings/power/rk3036-power.h" - for RK3036 type power domain. > - "include/dt-bindings/power/rk3066-power.h" - for RK3066 type power domain. > - "include/dt-bindings/power/rk3128-power.h" - for RK3128 type power domain. > - "include/dt-bindings/power/rk3188-power.h" - for RK3188 type power domain. > - "include/dt-bindings/power/rk3228-power.h" - for RK3228 type power domain. > - "include/dt-bindings/power/rk3288-power.h" - for RK3288 type power domain. > - "include/dt-bindings/power/rk3328-power.h" - for RK3328 type power domain. > - "include/dt-bindings/power/rk3366-power.h" - for RK3366 type power domain. > - "include/dt-bindings/power/rk3368-power.h" - for RK3368 type power domain. > - "include/dt-bindings/power/rk3399-power.h" - for RK3399 type power domain. > -- clocks (optional): phandles to clocks which need to be enabled while power domain > - switches state. > -- pm_qos (optional): phandles to qos blocks which need to be saved and restored > - while power domain switches state. > - > -Qos Example: > - > - qos_gpu: qos_gpu@ffaf0000 { > - compatible ="syscon"; > - reg = <0x0 0xffaf0000 0x0 0x20>; > - }; > - > -Example: > - > - power: power-controller { > - compatible = "rockchip,rk3288-power-controller"; > - #power-domain-cells = <1>; > - #address-cells = <1>; > - #size-cells = <0>; > - > - pd_gpu { > - reg = <RK3288_PD_GPU>; > - clocks = <&cru ACLK_GPU>; > - pm_qos = <&qos_gpu>; > - }; > - }; > - > - power: power-controller { > - compatible = "rockchip,rk3368-power-controller"; > - #power-domain-cells = <1>; > - #address-cells = <1>; > - #size-cells = <0>; > - > - pd_gpu_1 { > - reg = <RK3368_PD_GPU_1>; > - clocks = <&cru ACLK_GPU_CFG>; > - }; > - }; > - > -Example 2: > - power: power-controller { > - compatible = "rockchip,rk3399-power-controller"; > - #power-domain-cells = <1>; > - #address-cells = <1>; > - #size-cells = <0>; > - > - pd_vio { > - #address-cells = <1>; > - #size-cells = <0>; > - reg = <RK3399_PD_VIO>; > - > - pd_vo { > - #address-cells = <1>; > - #size-cells = <0>; > - reg = <RK3399_PD_VO>; > - > - pd_vopb { > - reg = <RK3399_PD_VOPB>; > - }; > - > - pd_vopl { > - reg = <RK3399_PD_VOPL>; > - }; > - }; > - }; > - }; > - > -Node of a device using power domains must have a power-domains property, > -containing a phandle to the power device node and an index specifying which > -power domain to use. > -The index should use macros in: > - "include/dt-bindings/power/px30-power.h" - for px30 type power domain. > - "include/dt-bindings/power/rk3036-power.h" - for rk3036 type power domain. > - "include/dt-bindings/power/rk3128-power.h" - for rk3128 type power domain. > - "include/dt-bindings/power/rk3128-power.h" - for rk3228 type power domain. > - "include/dt-bindings/power/rk3288-power.h" - for rk3288 type power domain. > - "include/dt-bindings/power/rk3328-power.h" - for rk3328 type power domain. > - "include/dt-bindings/power/rk3366-power.h" - for rk3366 type power domain. > - "include/dt-bindings/power/rk3368-power.h" - for rk3368 type power domain. > - "include/dt-bindings/power/rk3399-power.h" - for rk3399 type power domain. > - > -Example of the node using power domain: > - > - node { > - /* ... */ > - power-domains = <&power RK3288_PD_GPU>; > - /* ... */ > - }; > - > - node { > - /* ... */ > - power-domains = <&power RK3368_PD_GPU_1>; > - /* ... */ > - }; > - > - node { > - /* ... */ > - power-domains = <&power RK3399_PD_VOPB>; > - /* ... */ > - }; > ^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v5 09/11] dt-bindings: power: rockchip: Convert to json-schema @ 2021-03-26 9:51 ` Heiko Stübner 0 siblings, 0 replies; 75+ messages in thread From: Heiko Stübner @ 2021-03-26 9:51 UTC (permalink / raw) To: robh+dt, Elaine Zhang Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang, Enric Balletbo i Serra Am Freitag, 26. März 2021, 10:18:03 CET schrieb Elaine Zhang: > Convert the soc/rockchip/power_domain.txt binding document to > json-schema and move to the power bindings directory. > > Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> If Enric is the original author of this patch, maybe this needs a matching "From: ... " line? Thanks Heiko > --- > .../power/rockchip,power-controller.yaml | 291 ++++++++++++++++++ > .../bindings/soc/rockchip/power_domain.txt | 136 -------- > 2 files changed, 291 insertions(+), 136 deletions(-) > create mode 100644 Documentation/devicetree/bindings/power/rockchip,power-controller.yaml > delete mode 100644 Documentation/devicetree/bindings/soc/rockchip/power_domain.txt > > diff --git a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml > new file mode 100644 > index 000000000000..9fec9e227432 > --- /dev/null > +++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml > @@ -0,0 +1,291 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/power/rockchip,power-controller.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Rockchip Power Domains > + > +maintainers: > + - Elaine Zhang <zhangqing@rock-chips.com> > + - Heiko Stuebner <heiko@sntech.de> > + > +description: | > + Rockchip processors include support for multiple power domains which can be > + powered up/down by software based on different application scenarios to save power. > + > + Power domains contained within power-controller node are generic power domain > + providers documented in Documentation/devicetree/bindings/power/power-domain.yaml. > + > + IP cores belonging to a power domain should contain a "power-domains" > + property that is a phandle for the power domain node representing the domain. > + > +properties: > + $nodename: > + const: power-controller > + > + compatible: > + enum: > + - rockchip,px30-power-controller > + - rockchip,rk3036-power-controller > + - rockchip,rk3066-power-controller > + - rockchip,rk3128-power-controller > + - rockchip,rk3188-power-controller > + - rockchip,rk3228-power-controller > + - rockchip,rk3288-power-controller > + - rockchip,rk3328-power-controller > + - rockchip,rk3366-power-controller > + - rockchip,rk3368-power-controller > + - rockchip,rk3399-power-controller > + > + "#power-domain-cells": > + const: 1 > + > + "#address-cells": > + const: 1 > + > + "#size-cells": > + const: 0 > + > + clocks: true > + > + assigned-clocks: > + minItems: 1 > + > + assigned-clock-parents: > + minItems: 1 > + > +patternProperties: > + "^power-domain@[0-9a-f]+$": > + type: object > + description: | > + Represents the power domains within the power controller node as documented > + in Documentation/devicetree/bindings/power/power-domain.yaml. > + > + properties: > + > + "#power-domain-cells": > + description: > + Must be 0 for nodes representing a single PM domain and 1 for nodes > + providing multiple PM domains. > + > + "#address-cells": > + const: 1 > + > + "#size-cells": > + const: 0 > + > + reg: > + maxItems: 1 > + description: | > + Power domain index. Valid values are defined in > + "include/dt-bindings/power/px30-power.h" > + "include/dt-bindings/power/rk3036-power.h" > + "include/dt-bindings/power/rk3066-power.h" > + "include/dt-bindings/power/rk3128-power.h" > + "include/dt-bindings/power/rk3188-power.h" > + "include/dt-bindings/power/rk3228-power.h" > + "include/dt-bindings/power/rk3288-power.h" > + "include/dt-bindings/power/rk3328-power.h" > + "include/dt-bindings/power/rk3366-power.h" > + "include/dt-bindings/power/rk3368-power.h" > + "include/dt-bindings/power/rk3399-power.h" > + > + clocks: > + description: | > + A number of phandles to clocks that need to be enabled while power domain > + switches state. > + > + pm_qos: > + description: | > + A number of phandles to qos blocks which need to be saved and restored > + while power domain switches state. > + > + patternProperties: > + "^power-domain@[0-9a-f]+$": > + type: object > + description: | > + Represents a power domain child within a power domain parent node. > + > + properties: > + > + "#power-domain-cells": > + description: > + Must be 0 for nodes representing a single PM domain and 1 for nodes > + providing multiple PM domains. > + > + "#address-cells": > + const: 1 > + > + "#size-cells": > + const: 0 > + > + reg: > + maxItems: 1 > + > + clocks: > + description: | > + A number of phandles to clocks that need to be enabled while power domain > + switches state. > + > + pm_qos: > + description: | > + A number of phandles to qos blocks which need to be saved and restored > + while power domain switches state. > + > + patternProperties: > + "^power-domain@[0-9a-f]+$": > + type: object > + description: | > + Represents a power domain child within a power domain parent node. > + > + properties: > + > + "#power-domain-cells": > + description: > + Must be 0 for nodes representing a single PM domain and 1 for nodes > + providing multiple PM domains. > + > + "#address-cells": > + const: 1 > + > + "#size-cells": > + const: 0 > + > + reg: > + maxItems: 1 > + > + clocks: > + description: | > + A number of phandles to clocks that need to be enabled while power domain > + switches state. > + > + pm_qos: > + description: | > + A number of phandles to qos blocks which need to be saved and restored > + while power domain switches state. > + > + required: > + - reg > + > + additionalProperties: false > + > + required: > + - reg > + > + additionalProperties: false > + > + required: > + - reg > + > + additionalProperties: false > + > +required: > + - compatible > + - "#power-domain-cells" > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/rk3399-cru.h> > + #include <dt-bindings/power/rk3399-power.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + qos_hdcp: qos@ffa90000 { > + compatible = "rockchip,rk3399-qos", "syscon"; > + reg = <0x0 0xffa90000 0x0 0x20>; > + }; > + > + qos_iep: qos@ffa98000 { > + compatible = "rockchip,rk3399-qos", "syscon"; > + reg = <0x0 0xffa98000 0x0 0x20>; > + }; > + > + qos_rga_r: qos@ffab0000 { > + compatible = "rockchip,rk3399-qos", "syscon"; > + reg = <0x0 0xffab0000 0x0 0x20>; > + }; > + > + qos_rga_w: qos@ffab0080 { > + compatible = "rockchip,rk3399-qos", "syscon"; > + reg = <0x0 0xffab0080 0x0 0x20>; > + }; > + > + qos_video_m0: qos@ffab8000 { > + compatible = "rockchip,rk3399-qos", "syscon"; > + reg = <0x0 0xffab8000 0x0 0x20>; > + }; > + > + qos_video_m1_r: qos@ffac0000 { > + compatible = "rockchip,rk3399-qos", "syscon"; > + reg = <0x0 0xffac0000 0x0 0x20>; > + }; > + > + qos_video_m1_w: qos@ffac0080 { > + compatible = "rockchip,rk3399-qos", "syscon"; > + reg = <0x0 0xffac0080 0x0 0x20>; > + }; > + > + power-management@ff310000 { > + compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; > + reg = <0x0 0xff310000 0x0 0x1000>; > + > + power-controller { > + compatible = "rockchip,rk3399-power-controller"; > + #power-domain-cells = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + /* These power domains are grouped by VD_CENTER */ > + power-domain@RK3399_PD_IEP { > + reg = <RK3399_PD_IEP>; > + clocks = <&cru ACLK_IEP>, > + <&cru HCLK_IEP>; > + pm_qos = <&qos_iep>; > + #power-domain-cells = <0>; > + }; > + power-domain@RK3399_PD_RGA { > + reg = <RK3399_PD_RGA>; > + clocks = <&cru ACLK_RGA>, > + <&cru HCLK_RGA>; > + pm_qos = <&qos_rga_r>, > + <&qos_rga_w>; > + #power-domain-cells = <0>; > + }; > + power-domain@RK3399_PD_VCODEC { > + reg = <RK3399_PD_VCODEC>; > + clocks = <&cru ACLK_VCODEC>, > + <&cru HCLK_VCODEC>; > + pm_qos = <&qos_video_m0>; > + #power-domain-cells = <0>; > + }; > + power-domain@RK3399_PD_VDU { > + reg = <RK3399_PD_VDU>; > + clocks = <&cru ACLK_VDU>, > + <&cru HCLK_VDU>; > + pm_qos = <&qos_video_m1_r>, > + <&qos_video_m1_w>; > + #power-domain-cells = <0>; > + }; > + power-domain@RK3399_PD_VIO { > + reg = <RK3399_PD_VIO>; > + #power-domain-cells = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + power-domain@RK3399_PD_HDCP { > + reg = <RK3399_PD_HDCP>; > + clocks = <&cru ACLK_HDCP>, > + <&cru HCLK_HDCP>, > + <&cru PCLK_HDCP>; > + pm_qos = <&qos_hdcp>; > + #power-domain-cells = <0>; > + }; > + }; > + }; > + }; > + }; > diff --git a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt > deleted file mode 100644 > index 8304eceb62e4..000000000000 > --- a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt > +++ /dev/null > @@ -1,136 +0,0 @@ > -* Rockchip Power Domains > - > -Rockchip processors include support for multiple power domains which can be > -powered up/down by software based on different application scenes to save power. > - > -Required properties for power domain controller: > -- compatible: Should be one of the following. > - "rockchip,px30-power-controller" - for PX30 SoCs. > - "rockchip,rk3036-power-controller" - for RK3036 SoCs. > - "rockchip,rk3066-power-controller" - for RK3066 SoCs. > - "rockchip,rk3128-power-controller" - for RK3128 SoCs. > - "rockchip,rk3188-power-controller" - for RK3188 SoCs. > - "rockchip,rk3228-power-controller" - for RK3228 SoCs. > - "rockchip,rk3288-power-controller" - for RK3288 SoCs. > - "rockchip,rk3328-power-controller" - for RK3328 SoCs. > - "rockchip,rk3366-power-controller" - for RK3366 SoCs. > - "rockchip,rk3368-power-controller" - for RK3368 SoCs. > - "rockchip,rk3399-power-controller" - for RK3399 SoCs. > -- #power-domain-cells: Number of cells in a power-domain specifier. > - Should be 1 for multiple PM domains. > -- #address-cells: Should be 1. > -- #size-cells: Should be 0. > - > -Required properties for power domain sub nodes: > -- reg: index of the power domain, should use macros in: > - "include/dt-bindings/power/px30-power.h" - for PX30 type power domain. > - "include/dt-bindings/power/rk3036-power.h" - for RK3036 type power domain. > - "include/dt-bindings/power/rk3066-power.h" - for RK3066 type power domain. > - "include/dt-bindings/power/rk3128-power.h" - for RK3128 type power domain. > - "include/dt-bindings/power/rk3188-power.h" - for RK3188 type power domain. > - "include/dt-bindings/power/rk3228-power.h" - for RK3228 type power domain. > - "include/dt-bindings/power/rk3288-power.h" - for RK3288 type power domain. > - "include/dt-bindings/power/rk3328-power.h" - for RK3328 type power domain. > - "include/dt-bindings/power/rk3366-power.h" - for RK3366 type power domain. > - "include/dt-bindings/power/rk3368-power.h" - for RK3368 type power domain. > - "include/dt-bindings/power/rk3399-power.h" - for RK3399 type power domain. > -- clocks (optional): phandles to clocks which need to be enabled while power domain > - switches state. > -- pm_qos (optional): phandles to qos blocks which need to be saved and restored > - while power domain switches state. > - > -Qos Example: > - > - qos_gpu: qos_gpu@ffaf0000 { > - compatible ="syscon"; > - reg = <0x0 0xffaf0000 0x0 0x20>; > - }; > - > -Example: > - > - power: power-controller { > - compatible = "rockchip,rk3288-power-controller"; > - #power-domain-cells = <1>; > - #address-cells = <1>; > - #size-cells = <0>; > - > - pd_gpu { > - reg = <RK3288_PD_GPU>; > - clocks = <&cru ACLK_GPU>; > - pm_qos = <&qos_gpu>; > - }; > - }; > - > - power: power-controller { > - compatible = "rockchip,rk3368-power-controller"; > - #power-domain-cells = <1>; > - #address-cells = <1>; > - #size-cells = <0>; > - > - pd_gpu_1 { > - reg = <RK3368_PD_GPU_1>; > - clocks = <&cru ACLK_GPU_CFG>; > - }; > - }; > - > -Example 2: > - power: power-controller { > - compatible = "rockchip,rk3399-power-controller"; > - #power-domain-cells = <1>; > - #address-cells = <1>; > - #size-cells = <0>; > - > - pd_vio { > - #address-cells = <1>; > - #size-cells = <0>; > - reg = <RK3399_PD_VIO>; > - > - pd_vo { > - #address-cells = <1>; > - #size-cells = <0>; > - reg = <RK3399_PD_VO>; > - > - pd_vopb { > - reg = <RK3399_PD_VOPB>; > - }; > - > - pd_vopl { > - reg = <RK3399_PD_VOPL>; > - }; > - }; > - }; > - }; > - > -Node of a device using power domains must have a power-domains property, > -containing a phandle to the power device node and an index specifying which > -power domain to use. > -The index should use macros in: > - "include/dt-bindings/power/px30-power.h" - for px30 type power domain. > - "include/dt-bindings/power/rk3036-power.h" - for rk3036 type power domain. > - "include/dt-bindings/power/rk3128-power.h" - for rk3128 type power domain. > - "include/dt-bindings/power/rk3128-power.h" - for rk3228 type power domain. > - "include/dt-bindings/power/rk3288-power.h" - for rk3288 type power domain. > - "include/dt-bindings/power/rk3328-power.h" - for rk3328 type power domain. > - "include/dt-bindings/power/rk3366-power.h" - for rk3366 type power domain. > - "include/dt-bindings/power/rk3368-power.h" - for rk3368 type power domain. > - "include/dt-bindings/power/rk3399-power.h" - for rk3399 type power domain. > - > -Example of the node using power domain: > - > - node { > - /* ... */ > - power-domains = <&power RK3288_PD_GPU>; > - /* ... */ > - }; > - > - node { > - /* ... */ > - power-domains = <&power RK3368_PD_GPU_1>; > - /* ... */ > - }; > - > - node { > - /* ... */ > - power-domains = <&power RK3399_PD_VOPB>; > - /* ... */ > - }; > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v5 10/11] dt-bindings: power: rockchip: Add bindings for RK3568 Soc 2021-03-26 9:15 ` Elaine Zhang (?) @ 2021-03-26 9:18 ` Elaine Zhang -1 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:18 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Add the compatible string for RK3568 SoC. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- .../devicetree/bindings/power/rockchip,power-controller.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml index 9fec9e227432..a4d223255c3b 100644 --- a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml @@ -37,6 +37,7 @@ properties: - rockchip,rk3366-power-controller - rockchip,rk3368-power-controller - rockchip,rk3399-power-controller + - rockchip,rk3568-power-controller "#power-domain-cells": const: 1 @@ -90,6 +91,7 @@ patternProperties: "include/dt-bindings/power/rk3366-power.h" "include/dt-bindings/power/rk3368-power.h" "include/dt-bindings/power/rk3399-power.h" + "include/dt-bindings/power/rk3568-power.h" clocks: description: | -- 2.17.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v5 10/11] dt-bindings: power: rockchip: Add bindings for RK3568 Soc @ 2021-03-26 9:18 ` Elaine Zhang 0 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:18 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Add the compatible string for RK3568 SoC. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- .../devicetree/bindings/power/rockchip,power-controller.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml index 9fec9e227432..a4d223255c3b 100644 --- a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml @@ -37,6 +37,7 @@ properties: - rockchip,rk3366-power-controller - rockchip,rk3368-power-controller - rockchip,rk3399-power-controller + - rockchip,rk3568-power-controller "#power-domain-cells": const: 1 @@ -90,6 +91,7 @@ patternProperties: "include/dt-bindings/power/rk3366-power.h" "include/dt-bindings/power/rk3368-power.h" "include/dt-bindings/power/rk3399-power.h" + "include/dt-bindings/power/rk3568-power.h" clocks: description: | -- 2.17.1 ^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v5 10/11] dt-bindings: power: rockchip: Add bindings for RK3568 Soc @ 2021-03-26 9:18 ` Elaine Zhang 0 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:18 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Add the compatible string for RK3568 SoC. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- .../devicetree/bindings/power/rockchip,power-controller.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml index 9fec9e227432..a4d223255c3b 100644 --- a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml @@ -37,6 +37,7 @@ properties: - rockchip,rk3366-power-controller - rockchip,rk3368-power-controller - rockchip,rk3399-power-controller + - rockchip,rk3568-power-controller "#power-domain-cells": const: 1 @@ -90,6 +91,7 @@ patternProperties: "include/dt-bindings/power/rk3366-power.h" "include/dt-bindings/power/rk3368-power.h" "include/dt-bindings/power/rk3399-power.h" + "include/dt-bindings/power/rk3568-power.h" clocks: description: | -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 75+ messages in thread
* Re: [PATCH v5 10/11] dt-bindings: power: rockchip: Add bindings for RK3568 Soc 2021-03-26 9:18 ` Elaine Zhang (?) @ 2021-03-26 9:51 ` Enric Balletbo Serra -1 siblings, 0 replies; 75+ messages in thread From: Enric Balletbo Serra @ 2021-03-26 9:51 UTC (permalink / raw) To: Elaine Zhang Cc: Rob Herring, Heiko Stübner, devicetree@vger.kernel.org, Linux ARM, open list:ARM/Rockchip SoC..., linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao Missatge de Elaine Zhang <zhangqing@rock-chips.com> del dia dv., 26 de març 2021 a les 10:19: > > Add the compatible string for RK3568 SoC. > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > --- > .../devicetree/bindings/power/rockchip,power-controller.yaml | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml > index 9fec9e227432..a4d223255c3b 100644 > --- a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml > +++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml > @@ -37,6 +37,7 @@ properties: > - rockchip,rk3366-power-controller > - rockchip,rk3368-power-controller > - rockchip,rk3399-power-controller > + - rockchip,rk3568-power-controller > > "#power-domain-cells": > const: 1 > @@ -90,6 +91,7 @@ patternProperties: > "include/dt-bindings/power/rk3366-power.h" > "include/dt-bindings/power/rk3368-power.h" > "include/dt-bindings/power/rk3399-power.h" > + "include/dt-bindings/power/rk3568-power.h" > > clocks: > description: | > -- > 2.17.1 > > > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v5 10/11] dt-bindings: power: rockchip: Add bindings for RK3568 Soc @ 2021-03-26 9:51 ` Enric Balletbo Serra 0 siblings, 0 replies; 75+ messages in thread From: Enric Balletbo Serra @ 2021-03-26 9:51 UTC (permalink / raw) To: Elaine Zhang Cc: Rob Herring, Heiko Stübner, devicetree@vger.kernel.org, Linux ARM, open list:ARM/Rockchip SoC..., linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao Missatge de Elaine Zhang <zhangqing@rock-chips.com> del dia dv., 26 de març 2021 a les 10:19: > > Add the compatible string for RK3568 SoC. > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > --- > .../devicetree/bindings/power/rockchip,power-controller.yaml | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml > index 9fec9e227432..a4d223255c3b 100644 > --- a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml > +++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml > @@ -37,6 +37,7 @@ properties: > - rockchip,rk3366-power-controller > - rockchip,rk3368-power-controller > - rockchip,rk3399-power-controller > + - rockchip,rk3568-power-controller > > "#power-domain-cells": > const: 1 > @@ -90,6 +91,7 @@ patternProperties: > "include/dt-bindings/power/rk3366-power.h" > "include/dt-bindings/power/rk3368-power.h" > "include/dt-bindings/power/rk3399-power.h" > + "include/dt-bindings/power/rk3568-power.h" > > clocks: > description: | > -- > 2.17.1 > > > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v5 10/11] dt-bindings: power: rockchip: Add bindings for RK3568 Soc @ 2021-03-26 9:51 ` Enric Balletbo Serra 0 siblings, 0 replies; 75+ messages in thread From: Enric Balletbo Serra @ 2021-03-26 9:51 UTC (permalink / raw) To: Elaine Zhang Cc: Rob Herring, Heiko Stübner, devicetree@vger.kernel.org, Linux ARM, open list:ARM/Rockchip SoC..., linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao Missatge de Elaine Zhang <zhangqing@rock-chips.com> del dia dv., 26 de març 2021 a les 10:19: > > Add the compatible string for RK3568 SoC. > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > --- > .../devicetree/bindings/power/rockchip,power-controller.yaml | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml > index 9fec9e227432..a4d223255c3b 100644 > --- a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml > +++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml > @@ -37,6 +37,7 @@ properties: > - rockchip,rk3366-power-controller > - rockchip,rk3368-power-controller > - rockchip,rk3399-power-controller > + - rockchip,rk3568-power-controller > > "#power-domain-cells": > const: 1 > @@ -90,6 +91,7 @@ patternProperties: > "include/dt-bindings/power/rk3366-power.h" > "include/dt-bindings/power/rk3368-power.h" > "include/dt-bindings/power/rk3399-power.h" > + "include/dt-bindings/power/rk3568-power.h" > > clocks: > description: | > -- > 2.17.1 > > > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v5 11/11] soc: rockchip: power-domain: add rk3568 powerdomains 2021-03-26 9:15 ` Elaine Zhang (?) @ 2021-03-26 9:18 ` Elaine Zhang -1 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:18 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Add power-domains found on rk3568 socs. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- drivers/soc/rockchip/pm_domains.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c index d661d967079f..7b231cbcc17b 100644 --- a/drivers/soc/rockchip/pm_domains.c +++ b/drivers/soc/rockchip/pm_domains.c @@ -27,6 +27,7 @@ #include <dt-bindings/power/rk3366-power.h> #include <dt-bindings/power/rk3368-power.h> #include <dt-bindings/power/rk3399-power.h> +#include <dt-bindings/power/rk3568-power.h> struct rockchip_domain_info { const char *name; @@ -135,6 +136,9 @@ struct rockchip_pmu { #define DOMAIN_RK3399(name, pwr, status, req, wakeup) \ DOMAIN(name, pwr, status, req, req, req, wakeup) +#define DOMAIN_RK3568(name, pwr, req, wakeup) \ + DOMAIN_M(name, pwr, pwr, req, req, req, wakeup) + static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd) { struct rockchip_pmu *pmu = pd->pmu; @@ -848,6 +852,18 @@ static const struct rockchip_domain_info rk3399_pm_domains[] = { [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true), }; +static const struct rockchip_domain_info rk3568_pm_domains[] = { + [RK3568_PD_NPU] = DOMAIN_RK3568("npu", BIT(1), BIT(2), false), + [RK3568_PD_GPU] = DOMAIN_RK3568("gpu", BIT(0), BIT(1), false), + [RK3568_PD_VI] = DOMAIN_RK3568("vi", BIT(6), BIT(3), false), + [RK3568_PD_VO] = DOMAIN_RK3568("vo", BIT(7), BIT(4), false), + [RK3568_PD_RGA] = DOMAIN_RK3568("rga", BIT(5), BIT(5), false), + [RK3568_PD_VPU] = DOMAIN_RK3568("vpu", BIT(2), BIT(6), false), + [RK3568_PD_RKVDEC] = DOMAIN_RK3568("vdec", BIT(4), BIT(8), false), + [RK3568_PD_RKVENC] = DOMAIN_RK3568("venc", BIT(3), BIT(7), false), + [RK3568_PD_PIPE] = DOMAIN_RK3568("pipe", BIT(8), BIT(11), false), +}; + static const struct rockchip_pmu_info px30_pmu = { .pwr_offset = 0x18, .status_offset = 0x20, @@ -983,6 +999,17 @@ static const struct rockchip_pmu_info rk3399_pmu = { .domain_info = rk3399_pm_domains, }; +static const struct rockchip_pmu_info rk3568_pmu = { + .pwr_offset = 0xa0, + .status_offset = 0x98, + .req_offset = 0x50, + .idle_offset = 0x68, + .ack_offset = 0x60, + + .num_domains = ARRAY_SIZE(rk3568_pm_domains), + .domain_info = rk3568_pm_domains, +}; + static const struct of_device_id rockchip_pm_domain_dt_match[] = { { .compatible = "rockchip,px30-power-controller", @@ -1028,6 +1055,10 @@ static const struct of_device_id rockchip_pm_domain_dt_match[] = { .compatible = "rockchip,rk3399-power-controller", .data = (void *)&rk3399_pmu, }, + { + .compatible = "rockchip,rk3568-power-controller", + .data = (void *)&rk3568_pmu, + }, { /* sentinel */ }, }; -- 2.17.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v5 11/11] soc: rockchip: power-domain: add rk3568 powerdomains @ 2021-03-26 9:18 ` Elaine Zhang 0 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:18 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Add power-domains found on rk3568 socs. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- drivers/soc/rockchip/pm_domains.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c index d661d967079f..7b231cbcc17b 100644 --- a/drivers/soc/rockchip/pm_domains.c +++ b/drivers/soc/rockchip/pm_domains.c @@ -27,6 +27,7 @@ #include <dt-bindings/power/rk3366-power.h> #include <dt-bindings/power/rk3368-power.h> #include <dt-bindings/power/rk3399-power.h> +#include <dt-bindings/power/rk3568-power.h> struct rockchip_domain_info { const char *name; @@ -135,6 +136,9 @@ struct rockchip_pmu { #define DOMAIN_RK3399(name, pwr, status, req, wakeup) \ DOMAIN(name, pwr, status, req, req, req, wakeup) +#define DOMAIN_RK3568(name, pwr, req, wakeup) \ + DOMAIN_M(name, pwr, pwr, req, req, req, wakeup) + static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd) { struct rockchip_pmu *pmu = pd->pmu; @@ -848,6 +852,18 @@ static const struct rockchip_domain_info rk3399_pm_domains[] = { [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true), }; +static const struct rockchip_domain_info rk3568_pm_domains[] = { + [RK3568_PD_NPU] = DOMAIN_RK3568("npu", BIT(1), BIT(2), false), + [RK3568_PD_GPU] = DOMAIN_RK3568("gpu", BIT(0), BIT(1), false), + [RK3568_PD_VI] = DOMAIN_RK3568("vi", BIT(6), BIT(3), false), + [RK3568_PD_VO] = DOMAIN_RK3568("vo", BIT(7), BIT(4), false), + [RK3568_PD_RGA] = DOMAIN_RK3568("rga", BIT(5), BIT(5), false), + [RK3568_PD_VPU] = DOMAIN_RK3568("vpu", BIT(2), BIT(6), false), + [RK3568_PD_RKVDEC] = DOMAIN_RK3568("vdec", BIT(4), BIT(8), false), + [RK3568_PD_RKVENC] = DOMAIN_RK3568("venc", BIT(3), BIT(7), false), + [RK3568_PD_PIPE] = DOMAIN_RK3568("pipe", BIT(8), BIT(11), false), +}; + static const struct rockchip_pmu_info px30_pmu = { .pwr_offset = 0x18, .status_offset = 0x20, @@ -983,6 +999,17 @@ static const struct rockchip_pmu_info rk3399_pmu = { .domain_info = rk3399_pm_domains, }; +static const struct rockchip_pmu_info rk3568_pmu = { + .pwr_offset = 0xa0, + .status_offset = 0x98, + .req_offset = 0x50, + .idle_offset = 0x68, + .ack_offset = 0x60, + + .num_domains = ARRAY_SIZE(rk3568_pm_domains), + .domain_info = rk3568_pm_domains, +}; + static const struct of_device_id rockchip_pm_domain_dt_match[] = { { .compatible = "rockchip,px30-power-controller", @@ -1028,6 +1055,10 @@ static const struct of_device_id rockchip_pm_domain_dt_match[] = { .compatible = "rockchip,rk3399-power-controller", .data = (void *)&rk3399_pmu, }, + { + .compatible = "rockchip,rk3568-power-controller", + .data = (void *)&rk3568_pmu, + }, { /* sentinel */ }, }; -- 2.17.1 ^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v5 11/11] soc: rockchip: power-domain: add rk3568 powerdomains @ 2021-03-26 9:18 ` Elaine Zhang 0 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:18 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Add power-domains found on rk3568 socs. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- drivers/soc/rockchip/pm_domains.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c index d661d967079f..7b231cbcc17b 100644 --- a/drivers/soc/rockchip/pm_domains.c +++ b/drivers/soc/rockchip/pm_domains.c @@ -27,6 +27,7 @@ #include <dt-bindings/power/rk3366-power.h> #include <dt-bindings/power/rk3368-power.h> #include <dt-bindings/power/rk3399-power.h> +#include <dt-bindings/power/rk3568-power.h> struct rockchip_domain_info { const char *name; @@ -135,6 +136,9 @@ struct rockchip_pmu { #define DOMAIN_RK3399(name, pwr, status, req, wakeup) \ DOMAIN(name, pwr, status, req, req, req, wakeup) +#define DOMAIN_RK3568(name, pwr, req, wakeup) \ + DOMAIN_M(name, pwr, pwr, req, req, req, wakeup) + static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd) { struct rockchip_pmu *pmu = pd->pmu; @@ -848,6 +852,18 @@ static const struct rockchip_domain_info rk3399_pm_domains[] = { [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true), }; +static const struct rockchip_domain_info rk3568_pm_domains[] = { + [RK3568_PD_NPU] = DOMAIN_RK3568("npu", BIT(1), BIT(2), false), + [RK3568_PD_GPU] = DOMAIN_RK3568("gpu", BIT(0), BIT(1), false), + [RK3568_PD_VI] = DOMAIN_RK3568("vi", BIT(6), BIT(3), false), + [RK3568_PD_VO] = DOMAIN_RK3568("vo", BIT(7), BIT(4), false), + [RK3568_PD_RGA] = DOMAIN_RK3568("rga", BIT(5), BIT(5), false), + [RK3568_PD_VPU] = DOMAIN_RK3568("vpu", BIT(2), BIT(6), false), + [RK3568_PD_RKVDEC] = DOMAIN_RK3568("vdec", BIT(4), BIT(8), false), + [RK3568_PD_RKVENC] = DOMAIN_RK3568("venc", BIT(3), BIT(7), false), + [RK3568_PD_PIPE] = DOMAIN_RK3568("pipe", BIT(8), BIT(11), false), +}; + static const struct rockchip_pmu_info px30_pmu = { .pwr_offset = 0x18, .status_offset = 0x20, @@ -983,6 +999,17 @@ static const struct rockchip_pmu_info rk3399_pmu = { .domain_info = rk3399_pm_domains, }; +static const struct rockchip_pmu_info rk3568_pmu = { + .pwr_offset = 0xa0, + .status_offset = 0x98, + .req_offset = 0x50, + .idle_offset = 0x68, + .ack_offset = 0x60, + + .num_domains = ARRAY_SIZE(rk3568_pm_domains), + .domain_info = rk3568_pm_domains, +}; + static const struct of_device_id rockchip_pm_domain_dt_match[] = { { .compatible = "rockchip,px30-power-controller", @@ -1028,6 +1055,10 @@ static const struct of_device_id rockchip_pm_domain_dt_match[] = { .compatible = "rockchip,rk3399-power-controller", .data = (void *)&rk3399_pmu, }, + { + .compatible = "rockchip,rk3568-power-controller", + .data = (void *)&rk3568_pmu, + }, { /* sentinel */ }, }; -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 75+ messages in thread
* [RESEND PATCH v5 07/11] soc: rockchip: pm-domains: Add a meaningful power domain name 2021-03-26 9:15 ` Elaine Zhang (?) @ 2021-03-26 9:37 ` Elaine Zhang -1 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:37 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Add the power domains names to the power domain info struct so we have meaningful name for every power domain. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- drivers/soc/rockchip/pm_domains.c | 221 +++++++++++++++--------------- 1 file changed, 114 insertions(+), 107 deletions(-) diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c index 54eb6cfc5d5b..3e6268c30d7e 100644 --- a/drivers/soc/rockchip/pm_domains.c +++ b/drivers/soc/rockchip/pm_domains.c @@ -29,6 +29,7 @@ #include <dt-bindings/power/rk3399-power.h> struct rockchip_domain_info { + const char *name; int pwr_mask; int status_mask; int req_mask; @@ -85,8 +86,9 @@ struct rockchip_pmu { #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd) -#define DOMAIN(pwr, status, req, idle, ack, wakeup) \ +#define DOMAIN(_name, pwr, status, req, idle, ack, wakeup) \ { \ + .name = _name, \ .pwr_mask = (pwr), \ .status_mask = (status), \ .req_mask = (req), \ @@ -95,8 +97,9 @@ struct rockchip_pmu { .active_wakeup = (wakeup), \ } -#define DOMAIN_M(pwr, status, req, idle, ack, wakeup) \ +#define DOMAIN_M(_name, pwr, status, req, idle, ack, wakeup) \ { \ + .name = _name, \ .pwr_w_mask = (pwr) << 16, \ .pwr_mask = (pwr), \ .status_mask = (status), \ @@ -107,8 +110,9 @@ struct rockchip_pmu { .active_wakeup = wakeup, \ } -#define DOMAIN_RK3036(req, ack, idle, wakeup) \ +#define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \ { \ + .name = _name, \ .req_mask = (req), \ .req_w_mask = (req) << 16, \ .ack_mask = (ack), \ @@ -116,20 +120,20 @@ struct rockchip_pmu { .active_wakeup = wakeup, \ } -#define DOMAIN_PX30(pwr, status, req, wakeup) \ - DOMAIN_M(pwr, status, req, (req) << 16, req, wakeup) +#define DOMAIN_PX30(name, pwr, status, req, wakeup) \ + DOMAIN_M(name, pwr, status, req, (req) << 16, req, wakeup) -#define DOMAIN_RK3288(pwr, status, req, wakeup) \ - DOMAIN(pwr, status, req, req, (req) << 16, wakeup) +#define DOMAIN_RK3288(name, pwr, status, req, wakeup) \ + DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup) -#define DOMAIN_RK3328(pwr, status, req, wakeup) \ - DOMAIN_M(pwr, pwr, req, (req) << 10, req, wakeup) +#define DOMAIN_RK3328(name, pwr, status, req, wakeup) \ + DOMAIN_M(name, pwr, pwr, req, (req) << 10, req, wakeup) -#define DOMAIN_RK3368(pwr, status, req, wakeup) \ - DOMAIN(pwr, status, req, (req) << 16, req, wakeup) +#define DOMAIN_RK3368(name, pwr, status, req, wakeup) \ + DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup) -#define DOMAIN_RK3399(pwr, status, req, wakeup) \ - DOMAIN(pwr, status, req, req, req, wakeup) +#define DOMAIN_RK3399(name, pwr, status, req, wakeup) \ + DOMAIN(name, pwr, status, req, req, req, wakeup) static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd) { @@ -490,7 +494,10 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, goto err_unprepare_clocks; } - pd->genpd.name = node->name; + if (!pd->info->name) + pd->genpd.name = node->name; + else + pd->genpd.name = pd->info->name; pd->genpd.power_off = rockchip_pd_power_off; pd->genpd.power_on = rockchip_pd_power_on; pd->genpd.attach_dev = rockchip_pd_attach_dev; @@ -716,129 +723,129 @@ static int rockchip_pm_domain_probe(struct platform_device *pdev) } static const struct rockchip_domain_info px30_pm_domains[] = { - [PX30_PD_USB] = DOMAIN_PX30(BIT(5), BIT(5), BIT(10), false), - [PX30_PD_SDCARD] = DOMAIN_PX30(BIT(8), BIT(8), BIT(9), false), - [PX30_PD_GMAC] = DOMAIN_PX30(BIT(10), BIT(10), BIT(6), false), - [PX30_PD_MMC_NAND] = DOMAIN_PX30(BIT(11), BIT(11), BIT(5), false), - [PX30_PD_VPU] = DOMAIN_PX30(BIT(12), BIT(12), BIT(14), false), - [PX30_PD_VO] = DOMAIN_PX30(BIT(13), BIT(13), BIT(7), false), - [PX30_PD_VI] = DOMAIN_PX30(BIT(14), BIT(14), BIT(8), false), - [PX30_PD_GPU] = DOMAIN_PX30(BIT(15), BIT(15), BIT(2), false), + [PX30_PD_USB] = DOMAIN_PX30("usb", BIT(5), BIT(5), BIT(10), false), + [PX30_PD_SDCARD] = DOMAIN_PX30("sdcard", BIT(8), BIT(8), BIT(9), false), + [PX30_PD_GMAC] = DOMAIN_PX30("gmac", BIT(10), BIT(10), BIT(6), false), + [PX30_PD_MMC_NAND] = DOMAIN_PX30("mmc_nand", BIT(11), BIT(11), BIT(5), false), + [PX30_PD_VPU] = DOMAIN_PX30("vpu", BIT(12), BIT(12), BIT(14), false), + [PX30_PD_VO] = DOMAIN_PX30("vo", BIT(13), BIT(13), BIT(7), false), + [PX30_PD_VI] = DOMAIN_PX30("vi", BIT(14), BIT(14), BIT(8), false), + [PX30_PD_GPU] = DOMAIN_PX30("gpu", BIT(15), BIT(15), BIT(2), false), }; static const struct rockchip_domain_info rk3036_pm_domains[] = { - [RK3036_PD_MSCH] = DOMAIN_RK3036(BIT(14), BIT(23), BIT(30), true), - [RK3036_PD_CORE] = DOMAIN_RK3036(BIT(13), BIT(17), BIT(24), false), - [RK3036_PD_PERI] = DOMAIN_RK3036(BIT(12), BIT(18), BIT(25), false), - [RK3036_PD_VIO] = DOMAIN_RK3036(BIT(11), BIT(19), BIT(26), false), - [RK3036_PD_VPU] = DOMAIN_RK3036(BIT(10), BIT(20), BIT(27), false), - [RK3036_PD_GPU] = DOMAIN_RK3036(BIT(9), BIT(21), BIT(28), false), - [RK3036_PD_SYS] = DOMAIN_RK3036(BIT(8), BIT(22), BIT(29), false), + [RK3036_PD_MSCH] = DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true), + [RK3036_PD_CORE] = DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false), + [RK3036_PD_PERI] = DOMAIN_RK3036("peri", BIT(12), BIT(18), BIT(25), false), + [RK3036_PD_VIO] = DOMAIN_RK3036("vio", BIT(11), BIT(19), BIT(26), false), + [RK3036_PD_VPU] = DOMAIN_RK3036("vpu", BIT(10), BIT(20), BIT(27), false), + [RK3036_PD_GPU] = DOMAIN_RK3036("gpu", BIT(9), BIT(21), BIT(28), false), + [RK3036_PD_SYS] = DOMAIN_RK3036("sys", BIT(8), BIT(22), BIT(29), false), }; static const struct rockchip_domain_info rk3066_pm_domains[] = { - [RK3066_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), - [RK3066_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), - [RK3066_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), - [RK3066_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), - [RK3066_PD_CPU] = DOMAIN(0, BIT(5), BIT(1), BIT(26), BIT(31), false), + [RK3066_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), + [RK3066_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), + [RK3066_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), + [RK3066_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), + [RK3066_PD_CPU] = DOMAIN("cpu", 0, BIT(5), BIT(1), BIT(26), BIT(31), false), }; static const struct rockchip_domain_info rk3128_pm_domains[] = { - [RK3128_PD_CORE] = DOMAIN_RK3288(BIT(0), BIT(0), BIT(4), false), - [RK3128_PD_MSCH] = DOMAIN_RK3288(0, 0, BIT(6), true), - [RK3128_PD_VIO] = DOMAIN_RK3288(BIT(3), BIT(3), BIT(2), false), - [RK3128_PD_VIDEO] = DOMAIN_RK3288(BIT(2), BIT(2), BIT(1), false), - [RK3128_PD_GPU] = DOMAIN_RK3288(BIT(1), BIT(1), BIT(3), false), + [RK3128_PD_CORE] = DOMAIN_RK3288("core", BIT(0), BIT(0), BIT(4), false), + [RK3128_PD_MSCH] = DOMAIN_RK3288("msch", 0, 0, BIT(6), true), + [RK3128_PD_VIO] = DOMAIN_RK3288("vio", BIT(3), BIT(3), BIT(2), false), + [RK3128_PD_VIDEO] = DOMAIN_RK3288("video", BIT(2), BIT(2), BIT(1), false), + [RK3128_PD_GPU] = DOMAIN_RK3288("gpu", BIT(1), BIT(1), BIT(3), false), }; static const struct rockchip_domain_info rk3188_pm_domains[] = { - [RK3188_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), - [RK3188_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), - [RK3188_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), - [RK3188_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), - [RK3188_PD_CPU] = DOMAIN(BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false), + [RK3188_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), + [RK3188_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), + [RK3188_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), + [RK3188_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), + [RK3188_PD_CPU] = DOMAIN("cpu", BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false), }; static const struct rockchip_domain_info rk3228_pm_domains[] = { - [RK3228_PD_CORE] = DOMAIN_RK3036(BIT(0), BIT(0), BIT(16), true), - [RK3228_PD_MSCH] = DOMAIN_RK3036(BIT(1), BIT(1), BIT(17), true), - [RK3228_PD_BUS] = DOMAIN_RK3036(BIT(2), BIT(2), BIT(18), true), - [RK3228_PD_SYS] = DOMAIN_RK3036(BIT(3), BIT(3), BIT(19), true), - [RK3228_PD_VIO] = DOMAIN_RK3036(BIT(4), BIT(4), BIT(20), false), - [RK3228_PD_VOP] = DOMAIN_RK3036(BIT(5), BIT(5), BIT(21), false), - [RK3228_PD_VPU] = DOMAIN_RK3036(BIT(6), BIT(6), BIT(22), false), - [RK3228_PD_RKVDEC] = DOMAIN_RK3036(BIT(7), BIT(7), BIT(23), false), - [RK3228_PD_GPU] = DOMAIN_RK3036(BIT(8), BIT(8), BIT(24), false), - [RK3228_PD_PERI] = DOMAIN_RK3036(BIT(9), BIT(9), BIT(25), true), - [RK3228_PD_GMAC] = DOMAIN_RK3036(BIT(10), BIT(10), BIT(26), false), + [RK3228_PD_CORE] = DOMAIN_RK3036("core", BIT(0), BIT(0), BIT(16), true), + [RK3228_PD_MSCH] = DOMAIN_RK3036("msch", BIT(1), BIT(1), BIT(17), true), + [RK3228_PD_BUS] = DOMAIN_RK3036("bus", BIT(2), BIT(2), BIT(18), true), + [RK3228_PD_SYS] = DOMAIN_RK3036("sys", BIT(3), BIT(3), BIT(19), true), + [RK3228_PD_VIO] = DOMAIN_RK3036("vio", BIT(4), BIT(4), BIT(20), false), + [RK3228_PD_VOP] = DOMAIN_RK3036("vop", BIT(5), BIT(5), BIT(21), false), + [RK3228_PD_VPU] = DOMAIN_RK3036("vpu", BIT(6), BIT(6), BIT(22), false), + [RK3228_PD_RKVDEC] = DOMAIN_RK3036("vdec", BIT(7), BIT(7), BIT(23), false), + [RK3228_PD_GPU] = DOMAIN_RK3036("gpu", BIT(8), BIT(8), BIT(24), false), + [RK3228_PD_PERI] = DOMAIN_RK3036("peri", BIT(9), BIT(9), BIT(25), true), + [RK3228_PD_GMAC] = DOMAIN_RK3036("gmac", BIT(10), BIT(10), BIT(26), false), }; static const struct rockchip_domain_info rk3288_pm_domains[] = { - [RK3288_PD_VIO] = DOMAIN_RK3288(BIT(7), BIT(7), BIT(4), false), - [RK3288_PD_HEVC] = DOMAIN_RK3288(BIT(14), BIT(10), BIT(9), false), - [RK3288_PD_VIDEO] = DOMAIN_RK3288(BIT(8), BIT(8), BIT(3), false), - [RK3288_PD_GPU] = DOMAIN_RK3288(BIT(9), BIT(9), BIT(2), false), + [RK3288_PD_VIO] = DOMAIN_RK3288("vio", BIT(7), BIT(7), BIT(4), false), + [RK3288_PD_HEVC] = DOMAIN_RK3288("hevc", BIT(14), BIT(10), BIT(9), false), + [RK3288_PD_VIDEO] = DOMAIN_RK3288("video", BIT(8), BIT(8), BIT(3), false), + [RK3288_PD_GPU] = DOMAIN_RK3288("gpu", BIT(9), BIT(9), BIT(2), false), }; static const struct rockchip_domain_info rk3328_pm_domains[] = { - [RK3328_PD_CORE] = DOMAIN_RK3328(0, BIT(0), BIT(0), false), - [RK3328_PD_GPU] = DOMAIN_RK3328(0, BIT(1), BIT(1), false), - [RK3328_PD_BUS] = DOMAIN_RK3328(0, BIT(2), BIT(2), true), - [RK3328_PD_MSCH] = DOMAIN_RK3328(0, BIT(3), BIT(3), true), - [RK3328_PD_PERI] = DOMAIN_RK3328(0, BIT(4), BIT(4), true), - [RK3328_PD_VIDEO] = DOMAIN_RK3328(0, BIT(5), BIT(5), false), - [RK3328_PD_HEVC] = DOMAIN_RK3328(0, BIT(6), BIT(6), false), - [RK3328_PD_VIO] = DOMAIN_RK3328(0, BIT(8), BIT(8), false), - [RK3328_PD_VPU] = DOMAIN_RK3328(0, BIT(9), BIT(9), false), + [RK3328_PD_CORE] = DOMAIN_RK3328("core", 0, BIT(0), BIT(0), false), + [RK3328_PD_GPU] = DOMAIN_RK3328("gpu", 0, BIT(1), BIT(1), false), + [RK3328_PD_BUS] = DOMAIN_RK3328("bus", 0, BIT(2), BIT(2), true), + [RK3328_PD_MSCH] = DOMAIN_RK3328("msch", 0, BIT(3), BIT(3), true), + [RK3328_PD_PERI] = DOMAIN_RK3328("peri", 0, BIT(4), BIT(4), true), + [RK3328_PD_VIDEO] = DOMAIN_RK3328("video", 0, BIT(5), BIT(5), false), + [RK3328_PD_HEVC] = DOMAIN_RK3328("hevc", 0, BIT(6), BIT(6), false), + [RK3328_PD_VIO] = DOMAIN_RK3328("vio", 0, BIT(8), BIT(8), false), + [RK3328_PD_VPU] = DOMAIN_RK3328("vpu", 0, BIT(9), BIT(9), false), }; static const struct rockchip_domain_info rk3366_pm_domains[] = { - [RK3366_PD_PERI] = DOMAIN_RK3368(BIT(10), BIT(10), BIT(6), true), - [RK3366_PD_VIO] = DOMAIN_RK3368(BIT(14), BIT(14), BIT(8), false), - [RK3366_PD_VIDEO] = DOMAIN_RK3368(BIT(13), BIT(13), BIT(7), false), - [RK3366_PD_RKVDEC] = DOMAIN_RK3368(BIT(11), BIT(11), BIT(7), false), - [RK3366_PD_WIFIBT] = DOMAIN_RK3368(BIT(8), BIT(8), BIT(9), false), - [RK3366_PD_VPU] = DOMAIN_RK3368(BIT(12), BIT(12), BIT(7), false), - [RK3366_PD_GPU] = DOMAIN_RK3368(BIT(15), BIT(15), BIT(2), false), + [RK3366_PD_PERI] = DOMAIN_RK3368("peri", BIT(10), BIT(10), BIT(6), true), + [RK3366_PD_VIO] = DOMAIN_RK3368("vio", BIT(14), BIT(14), BIT(8), false), + [RK3366_PD_VIDEO] = DOMAIN_RK3368("video", BIT(13), BIT(13), BIT(7), false), + [RK3366_PD_RKVDEC] = DOMAIN_RK3368("vdec", BIT(11), BIT(11), BIT(7), false), + [RK3366_PD_WIFIBT] = DOMAIN_RK3368("wifibt", BIT(8), BIT(8), BIT(9), false), + [RK3366_PD_VPU] = DOMAIN_RK3368("vpu", BIT(12), BIT(12), BIT(7), false), + [RK3366_PD_GPU] = DOMAIN_RK3368("gpu", BIT(15), BIT(15), BIT(2), false), }; static const struct rockchip_domain_info rk3368_pm_domains[] = { - [RK3368_PD_PERI] = DOMAIN_RK3368(BIT(13), BIT(12), BIT(6), true), - [RK3368_PD_VIO] = DOMAIN_RK3368(BIT(15), BIT(14), BIT(8), false), - [RK3368_PD_VIDEO] = DOMAIN_RK3368(BIT(14), BIT(13), BIT(7), false), - [RK3368_PD_GPU_0] = DOMAIN_RK3368(BIT(16), BIT(15), BIT(2), false), - [RK3368_PD_GPU_1] = DOMAIN_RK3368(BIT(17), BIT(16), BIT(2), false), + [RK3368_PD_PERI] = DOMAIN_RK3368("peri", BIT(13), BIT(12), BIT(6), true), + [RK3368_PD_VIO] = DOMAIN_RK3368("vio", BIT(15), BIT(14), BIT(8), false), + [RK3368_PD_VIDEO] = DOMAIN_RK3368("video", BIT(14), BIT(13), BIT(7), false), + [RK3368_PD_GPU_0] = DOMAIN_RK3368("gpu_0", BIT(16), BIT(15), BIT(2), false), + [RK3368_PD_GPU_1] = DOMAIN_RK3368("gpu_1", BIT(17), BIT(16), BIT(2), false), }; static const struct rockchip_domain_info rk3399_pm_domains[] = { - [RK3399_PD_TCPD0] = DOMAIN_RK3399(BIT(8), BIT(8), 0, false), - [RK3399_PD_TCPD1] = DOMAIN_RK3399(BIT(9), BIT(9), 0, false), - [RK3399_PD_CCI] = DOMAIN_RK3399(BIT(10), BIT(10), 0, true), - [RK3399_PD_CCI0] = DOMAIN_RK3399(0, 0, BIT(15), true), - [RK3399_PD_CCI1] = DOMAIN_RK3399(0, 0, BIT(16), true), - [RK3399_PD_PERILP] = DOMAIN_RK3399(BIT(11), BIT(11), BIT(1), true), - [RK3399_PD_PERIHP] = DOMAIN_RK3399(BIT(12), BIT(12), BIT(2), true), - [RK3399_PD_CENTER] = DOMAIN_RK3399(BIT(13), BIT(13), BIT(14), true), - [RK3399_PD_VIO] = DOMAIN_RK3399(BIT(14), BIT(14), BIT(17), false), - [RK3399_PD_GPU] = DOMAIN_RK3399(BIT(15), BIT(15), BIT(0), false), - [RK3399_PD_VCODEC] = DOMAIN_RK3399(BIT(16), BIT(16), BIT(3), false), - [RK3399_PD_VDU] = DOMAIN_RK3399(BIT(17), BIT(17), BIT(4), false), - [RK3399_PD_RGA] = DOMAIN_RK3399(BIT(18), BIT(18), BIT(5), false), - [RK3399_PD_IEP] = DOMAIN_RK3399(BIT(19), BIT(19), BIT(6), false), - [RK3399_PD_VO] = DOMAIN_RK3399(BIT(20), BIT(20), 0, false), - [RK3399_PD_VOPB] = DOMAIN_RK3399(0, 0, BIT(7), false), - [RK3399_PD_VOPL] = DOMAIN_RK3399(0, 0, BIT(8), false), - [RK3399_PD_ISP0] = DOMAIN_RK3399(BIT(22), BIT(22), BIT(9), false), - [RK3399_PD_ISP1] = DOMAIN_RK3399(BIT(23), BIT(23), BIT(10), false), - [RK3399_PD_HDCP] = DOMAIN_RK3399(BIT(24), BIT(24), BIT(11), false), - [RK3399_PD_GMAC] = DOMAIN_RK3399(BIT(25), BIT(25), BIT(23), true), - [RK3399_PD_EMMC] = DOMAIN_RK3399(BIT(26), BIT(26), BIT(24), true), - [RK3399_PD_USB3] = DOMAIN_RK3399(BIT(27), BIT(27), BIT(12), true), - [RK3399_PD_EDP] = DOMAIN_RK3399(BIT(28), BIT(28), BIT(22), false), - [RK3399_PD_GIC] = DOMAIN_RK3399(BIT(29), BIT(29), BIT(27), true), - [RK3399_PD_SD] = DOMAIN_RK3399(BIT(30), BIT(30), BIT(28), true), - [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399(BIT(31), BIT(31), BIT(29), true), + [RK3399_PD_TCPD0] = DOMAIN_RK3399("tcpd0", BIT(8), BIT(8), 0, false), + [RK3399_PD_TCPD1] = DOMAIN_RK3399("tcpd1", BIT(9), BIT(9), 0, false), + [RK3399_PD_CCI] = DOMAIN_RK3399("cci", BIT(10), BIT(10), 0, true), + [RK3399_PD_CCI0] = DOMAIN_RK3399("cci0", 0, 0, BIT(15), true), + [RK3399_PD_CCI1] = DOMAIN_RK3399("cci1", 0, 0, BIT(16), true), + [RK3399_PD_PERILP] = DOMAIN_RK3399("perilp", BIT(11), BIT(11), BIT(1), true), + [RK3399_PD_PERIHP] = DOMAIN_RK3399("perihp", BIT(12), BIT(12), BIT(2), true), + [RK3399_PD_CENTER] = DOMAIN_RK3399("center", BIT(13), BIT(13), BIT(14), true), + [RK3399_PD_VIO] = DOMAIN_RK3399("vio", BIT(14), BIT(14), BIT(17), false), + [RK3399_PD_GPU] = DOMAIN_RK3399("gpu", BIT(15), BIT(15), BIT(0), false), + [RK3399_PD_VCODEC] = DOMAIN_RK3399("vcodec", BIT(16), BIT(16), BIT(3), false), + [RK3399_PD_VDU] = DOMAIN_RK3399("vdu", BIT(17), BIT(17), BIT(4), false), + [RK3399_PD_RGA] = DOMAIN_RK3399("rga", BIT(18), BIT(18), BIT(5), false), + [RK3399_PD_IEP] = DOMAIN_RK3399("iep", BIT(19), BIT(19), BIT(6), false), + [RK3399_PD_VO] = DOMAIN_RK3399("vo", BIT(20), BIT(20), 0, false), + [RK3399_PD_VOPB] = DOMAIN_RK3399("vopb", 0, 0, BIT(7), false), + [RK3399_PD_VOPL] = DOMAIN_RK3399("vopl", 0, 0, BIT(8), false), + [RK3399_PD_ISP0] = DOMAIN_RK3399("isp0", BIT(22), BIT(22), BIT(9), false), + [RK3399_PD_ISP1] = DOMAIN_RK3399("isp1", BIT(23), BIT(23), BIT(10), false), + [RK3399_PD_HDCP] = DOMAIN_RK3399("hdcp", BIT(24), BIT(24), BIT(11), false), + [RK3399_PD_GMAC] = DOMAIN_RK3399("gmac", BIT(25), BIT(25), BIT(23), true), + [RK3399_PD_EMMC] = DOMAIN_RK3399("emmc", BIT(26), BIT(26), BIT(24), true), + [RK3399_PD_USB3] = DOMAIN_RK3399("usb3", BIT(27), BIT(27), BIT(12), true), + [RK3399_PD_EDP] = DOMAIN_RK3399("edp", BIT(28), BIT(28), BIT(22), false), + [RK3399_PD_GIC] = DOMAIN_RK3399("gic", BIT(29), BIT(29), BIT(27), true), + [RK3399_PD_SD] = DOMAIN_RK3399("sd", BIT(30), BIT(30), BIT(28), true), + [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true), }; static const struct rockchip_pmu_info px30_pmu = { -- 2.17.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 75+ messages in thread
* [RESEND PATCH v5 07/11] soc: rockchip: pm-domains: Add a meaningful power domain name @ 2021-03-26 9:37 ` Elaine Zhang 0 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:37 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Add the power domains names to the power domain info struct so we have meaningful name for every power domain. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- drivers/soc/rockchip/pm_domains.c | 221 +++++++++++++++--------------- 1 file changed, 114 insertions(+), 107 deletions(-) diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c index 54eb6cfc5d5b..3e6268c30d7e 100644 --- a/drivers/soc/rockchip/pm_domains.c +++ b/drivers/soc/rockchip/pm_domains.c @@ -29,6 +29,7 @@ #include <dt-bindings/power/rk3399-power.h> struct rockchip_domain_info { + const char *name; int pwr_mask; int status_mask; int req_mask; @@ -85,8 +86,9 @@ struct rockchip_pmu { #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd) -#define DOMAIN(pwr, status, req, idle, ack, wakeup) \ +#define DOMAIN(_name, pwr, status, req, idle, ack, wakeup) \ { \ + .name = _name, \ .pwr_mask = (pwr), \ .status_mask = (status), \ .req_mask = (req), \ @@ -95,8 +97,9 @@ struct rockchip_pmu { .active_wakeup = (wakeup), \ } -#define DOMAIN_M(pwr, status, req, idle, ack, wakeup) \ +#define DOMAIN_M(_name, pwr, status, req, idle, ack, wakeup) \ { \ + .name = _name, \ .pwr_w_mask = (pwr) << 16, \ .pwr_mask = (pwr), \ .status_mask = (status), \ @@ -107,8 +110,9 @@ struct rockchip_pmu { .active_wakeup = wakeup, \ } -#define DOMAIN_RK3036(req, ack, idle, wakeup) \ +#define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \ { \ + .name = _name, \ .req_mask = (req), \ .req_w_mask = (req) << 16, \ .ack_mask = (ack), \ @@ -116,20 +120,20 @@ struct rockchip_pmu { .active_wakeup = wakeup, \ } -#define DOMAIN_PX30(pwr, status, req, wakeup) \ - DOMAIN_M(pwr, status, req, (req) << 16, req, wakeup) +#define DOMAIN_PX30(name, pwr, status, req, wakeup) \ + DOMAIN_M(name, pwr, status, req, (req) << 16, req, wakeup) -#define DOMAIN_RK3288(pwr, status, req, wakeup) \ - DOMAIN(pwr, status, req, req, (req) << 16, wakeup) +#define DOMAIN_RK3288(name, pwr, status, req, wakeup) \ + DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup) -#define DOMAIN_RK3328(pwr, status, req, wakeup) \ - DOMAIN_M(pwr, pwr, req, (req) << 10, req, wakeup) +#define DOMAIN_RK3328(name, pwr, status, req, wakeup) \ + DOMAIN_M(name, pwr, pwr, req, (req) << 10, req, wakeup) -#define DOMAIN_RK3368(pwr, status, req, wakeup) \ - DOMAIN(pwr, status, req, (req) << 16, req, wakeup) +#define DOMAIN_RK3368(name, pwr, status, req, wakeup) \ + DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup) -#define DOMAIN_RK3399(pwr, status, req, wakeup) \ - DOMAIN(pwr, status, req, req, req, wakeup) +#define DOMAIN_RK3399(name, pwr, status, req, wakeup) \ + DOMAIN(name, pwr, status, req, req, req, wakeup) static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd) { @@ -490,7 +494,10 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, goto err_unprepare_clocks; } - pd->genpd.name = node->name; + if (!pd->info->name) + pd->genpd.name = node->name; + else + pd->genpd.name = pd->info->name; pd->genpd.power_off = rockchip_pd_power_off; pd->genpd.power_on = rockchip_pd_power_on; pd->genpd.attach_dev = rockchip_pd_attach_dev; @@ -716,129 +723,129 @@ static int rockchip_pm_domain_probe(struct platform_device *pdev) } static const struct rockchip_domain_info px30_pm_domains[] = { - [PX30_PD_USB] = DOMAIN_PX30(BIT(5), BIT(5), BIT(10), false), - [PX30_PD_SDCARD] = DOMAIN_PX30(BIT(8), BIT(8), BIT(9), false), - [PX30_PD_GMAC] = DOMAIN_PX30(BIT(10), BIT(10), BIT(6), false), - [PX30_PD_MMC_NAND] = DOMAIN_PX30(BIT(11), BIT(11), BIT(5), false), - [PX30_PD_VPU] = DOMAIN_PX30(BIT(12), BIT(12), BIT(14), false), - [PX30_PD_VO] = DOMAIN_PX30(BIT(13), BIT(13), BIT(7), false), - [PX30_PD_VI] = DOMAIN_PX30(BIT(14), BIT(14), BIT(8), false), - [PX30_PD_GPU] = DOMAIN_PX30(BIT(15), BIT(15), BIT(2), false), + [PX30_PD_USB] = DOMAIN_PX30("usb", BIT(5), BIT(5), BIT(10), false), + [PX30_PD_SDCARD] = DOMAIN_PX30("sdcard", BIT(8), BIT(8), BIT(9), false), + [PX30_PD_GMAC] = DOMAIN_PX30("gmac", BIT(10), BIT(10), BIT(6), false), + [PX30_PD_MMC_NAND] = DOMAIN_PX30("mmc_nand", BIT(11), BIT(11), BIT(5), false), + [PX30_PD_VPU] = DOMAIN_PX30("vpu", BIT(12), BIT(12), BIT(14), false), + [PX30_PD_VO] = DOMAIN_PX30("vo", BIT(13), BIT(13), BIT(7), false), + [PX30_PD_VI] = DOMAIN_PX30("vi", BIT(14), BIT(14), BIT(8), false), + [PX30_PD_GPU] = DOMAIN_PX30("gpu", BIT(15), BIT(15), BIT(2), false), }; static const struct rockchip_domain_info rk3036_pm_domains[] = { - [RK3036_PD_MSCH] = DOMAIN_RK3036(BIT(14), BIT(23), BIT(30), true), - [RK3036_PD_CORE] = DOMAIN_RK3036(BIT(13), BIT(17), BIT(24), false), - [RK3036_PD_PERI] = DOMAIN_RK3036(BIT(12), BIT(18), BIT(25), false), - [RK3036_PD_VIO] = DOMAIN_RK3036(BIT(11), BIT(19), BIT(26), false), - [RK3036_PD_VPU] = DOMAIN_RK3036(BIT(10), BIT(20), BIT(27), false), - [RK3036_PD_GPU] = DOMAIN_RK3036(BIT(9), BIT(21), BIT(28), false), - [RK3036_PD_SYS] = DOMAIN_RK3036(BIT(8), BIT(22), BIT(29), false), + [RK3036_PD_MSCH] = DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true), + [RK3036_PD_CORE] = DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false), + [RK3036_PD_PERI] = DOMAIN_RK3036("peri", BIT(12), BIT(18), BIT(25), false), + [RK3036_PD_VIO] = DOMAIN_RK3036("vio", BIT(11), BIT(19), BIT(26), false), + [RK3036_PD_VPU] = DOMAIN_RK3036("vpu", BIT(10), BIT(20), BIT(27), false), + [RK3036_PD_GPU] = DOMAIN_RK3036("gpu", BIT(9), BIT(21), BIT(28), false), + [RK3036_PD_SYS] = DOMAIN_RK3036("sys", BIT(8), BIT(22), BIT(29), false), }; static const struct rockchip_domain_info rk3066_pm_domains[] = { - [RK3066_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), - [RK3066_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), - [RK3066_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), - [RK3066_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), - [RK3066_PD_CPU] = DOMAIN(0, BIT(5), BIT(1), BIT(26), BIT(31), false), + [RK3066_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), + [RK3066_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), + [RK3066_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), + [RK3066_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), + [RK3066_PD_CPU] = DOMAIN("cpu", 0, BIT(5), BIT(1), BIT(26), BIT(31), false), }; static const struct rockchip_domain_info rk3128_pm_domains[] = { - [RK3128_PD_CORE] = DOMAIN_RK3288(BIT(0), BIT(0), BIT(4), false), - [RK3128_PD_MSCH] = DOMAIN_RK3288(0, 0, BIT(6), true), - [RK3128_PD_VIO] = DOMAIN_RK3288(BIT(3), BIT(3), BIT(2), false), - [RK3128_PD_VIDEO] = DOMAIN_RK3288(BIT(2), BIT(2), BIT(1), false), - [RK3128_PD_GPU] = DOMAIN_RK3288(BIT(1), BIT(1), BIT(3), false), + [RK3128_PD_CORE] = DOMAIN_RK3288("core", BIT(0), BIT(0), BIT(4), false), + [RK3128_PD_MSCH] = DOMAIN_RK3288("msch", 0, 0, BIT(6), true), + [RK3128_PD_VIO] = DOMAIN_RK3288("vio", BIT(3), BIT(3), BIT(2), false), + [RK3128_PD_VIDEO] = DOMAIN_RK3288("video", BIT(2), BIT(2), BIT(1), false), + [RK3128_PD_GPU] = DOMAIN_RK3288("gpu", BIT(1), BIT(1), BIT(3), false), }; static const struct rockchip_domain_info rk3188_pm_domains[] = { - [RK3188_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), - [RK3188_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), - [RK3188_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), - [RK3188_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), - [RK3188_PD_CPU] = DOMAIN(BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false), + [RK3188_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), + [RK3188_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), + [RK3188_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), + [RK3188_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), + [RK3188_PD_CPU] = DOMAIN("cpu", BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false), }; static const struct rockchip_domain_info rk3228_pm_domains[] = { - [RK3228_PD_CORE] = DOMAIN_RK3036(BIT(0), BIT(0), BIT(16), true), - [RK3228_PD_MSCH] = DOMAIN_RK3036(BIT(1), BIT(1), BIT(17), true), - [RK3228_PD_BUS] = DOMAIN_RK3036(BIT(2), BIT(2), BIT(18), true), - [RK3228_PD_SYS] = DOMAIN_RK3036(BIT(3), BIT(3), BIT(19), true), - [RK3228_PD_VIO] = DOMAIN_RK3036(BIT(4), BIT(4), BIT(20), false), - [RK3228_PD_VOP] = DOMAIN_RK3036(BIT(5), BIT(5), BIT(21), false), - [RK3228_PD_VPU] = DOMAIN_RK3036(BIT(6), BIT(6), BIT(22), false), - [RK3228_PD_RKVDEC] = DOMAIN_RK3036(BIT(7), BIT(7), BIT(23), false), - [RK3228_PD_GPU] = DOMAIN_RK3036(BIT(8), BIT(8), BIT(24), false), - [RK3228_PD_PERI] = DOMAIN_RK3036(BIT(9), BIT(9), BIT(25), true), - [RK3228_PD_GMAC] = DOMAIN_RK3036(BIT(10), BIT(10), BIT(26), false), + [RK3228_PD_CORE] = DOMAIN_RK3036("core", BIT(0), BIT(0), BIT(16), true), + [RK3228_PD_MSCH] = DOMAIN_RK3036("msch", BIT(1), BIT(1), BIT(17), true), + [RK3228_PD_BUS] = DOMAIN_RK3036("bus", BIT(2), BIT(2), BIT(18), true), + [RK3228_PD_SYS] = DOMAIN_RK3036("sys", BIT(3), BIT(3), BIT(19), true), + [RK3228_PD_VIO] = DOMAIN_RK3036("vio", BIT(4), BIT(4), BIT(20), false), + [RK3228_PD_VOP] = DOMAIN_RK3036("vop", BIT(5), BIT(5), BIT(21), false), + [RK3228_PD_VPU] = DOMAIN_RK3036("vpu", BIT(6), BIT(6), BIT(22), false), + [RK3228_PD_RKVDEC] = DOMAIN_RK3036("vdec", BIT(7), BIT(7), BIT(23), false), + [RK3228_PD_GPU] = DOMAIN_RK3036("gpu", BIT(8), BIT(8), BIT(24), false), + [RK3228_PD_PERI] = DOMAIN_RK3036("peri", BIT(9), BIT(9), BIT(25), true), + [RK3228_PD_GMAC] = DOMAIN_RK3036("gmac", BIT(10), BIT(10), BIT(26), false), }; static const struct rockchip_domain_info rk3288_pm_domains[] = { - [RK3288_PD_VIO] = DOMAIN_RK3288(BIT(7), BIT(7), BIT(4), false), - [RK3288_PD_HEVC] = DOMAIN_RK3288(BIT(14), BIT(10), BIT(9), false), - [RK3288_PD_VIDEO] = DOMAIN_RK3288(BIT(8), BIT(8), BIT(3), false), - [RK3288_PD_GPU] = DOMAIN_RK3288(BIT(9), BIT(9), BIT(2), false), + [RK3288_PD_VIO] = DOMAIN_RK3288("vio", BIT(7), BIT(7), BIT(4), false), + [RK3288_PD_HEVC] = DOMAIN_RK3288("hevc", BIT(14), BIT(10), BIT(9), false), + [RK3288_PD_VIDEO] = DOMAIN_RK3288("video", BIT(8), BIT(8), BIT(3), false), + [RK3288_PD_GPU] = DOMAIN_RK3288("gpu", BIT(9), BIT(9), BIT(2), false), }; static const struct rockchip_domain_info rk3328_pm_domains[] = { - [RK3328_PD_CORE] = DOMAIN_RK3328(0, BIT(0), BIT(0), false), - [RK3328_PD_GPU] = DOMAIN_RK3328(0, BIT(1), BIT(1), false), - [RK3328_PD_BUS] = DOMAIN_RK3328(0, BIT(2), BIT(2), true), - [RK3328_PD_MSCH] = DOMAIN_RK3328(0, BIT(3), BIT(3), true), - [RK3328_PD_PERI] = DOMAIN_RK3328(0, BIT(4), BIT(4), true), - [RK3328_PD_VIDEO] = DOMAIN_RK3328(0, BIT(5), BIT(5), false), - [RK3328_PD_HEVC] = DOMAIN_RK3328(0, BIT(6), BIT(6), false), - [RK3328_PD_VIO] = DOMAIN_RK3328(0, BIT(8), BIT(8), false), - [RK3328_PD_VPU] = DOMAIN_RK3328(0, BIT(9), BIT(9), false), + [RK3328_PD_CORE] = DOMAIN_RK3328("core", 0, BIT(0), BIT(0), false), + [RK3328_PD_GPU] = DOMAIN_RK3328("gpu", 0, BIT(1), BIT(1), false), + [RK3328_PD_BUS] = DOMAIN_RK3328("bus", 0, BIT(2), BIT(2), true), + [RK3328_PD_MSCH] = DOMAIN_RK3328("msch", 0, BIT(3), BIT(3), true), + [RK3328_PD_PERI] = DOMAIN_RK3328("peri", 0, BIT(4), BIT(4), true), + [RK3328_PD_VIDEO] = DOMAIN_RK3328("video", 0, BIT(5), BIT(5), false), + [RK3328_PD_HEVC] = DOMAIN_RK3328("hevc", 0, BIT(6), BIT(6), false), + [RK3328_PD_VIO] = DOMAIN_RK3328("vio", 0, BIT(8), BIT(8), false), + [RK3328_PD_VPU] = DOMAIN_RK3328("vpu", 0, BIT(9), BIT(9), false), }; static const struct rockchip_domain_info rk3366_pm_domains[] = { - [RK3366_PD_PERI] = DOMAIN_RK3368(BIT(10), BIT(10), BIT(6), true), - [RK3366_PD_VIO] = DOMAIN_RK3368(BIT(14), BIT(14), BIT(8), false), - [RK3366_PD_VIDEO] = DOMAIN_RK3368(BIT(13), BIT(13), BIT(7), false), - [RK3366_PD_RKVDEC] = DOMAIN_RK3368(BIT(11), BIT(11), BIT(7), false), - [RK3366_PD_WIFIBT] = DOMAIN_RK3368(BIT(8), BIT(8), BIT(9), false), - [RK3366_PD_VPU] = DOMAIN_RK3368(BIT(12), BIT(12), BIT(7), false), - [RK3366_PD_GPU] = DOMAIN_RK3368(BIT(15), BIT(15), BIT(2), false), + [RK3366_PD_PERI] = DOMAIN_RK3368("peri", BIT(10), BIT(10), BIT(6), true), + [RK3366_PD_VIO] = DOMAIN_RK3368("vio", BIT(14), BIT(14), BIT(8), false), + [RK3366_PD_VIDEO] = DOMAIN_RK3368("video", BIT(13), BIT(13), BIT(7), false), + [RK3366_PD_RKVDEC] = DOMAIN_RK3368("vdec", BIT(11), BIT(11), BIT(7), false), + [RK3366_PD_WIFIBT] = DOMAIN_RK3368("wifibt", BIT(8), BIT(8), BIT(9), false), + [RK3366_PD_VPU] = DOMAIN_RK3368("vpu", BIT(12), BIT(12), BIT(7), false), + [RK3366_PD_GPU] = DOMAIN_RK3368("gpu", BIT(15), BIT(15), BIT(2), false), }; static const struct rockchip_domain_info rk3368_pm_domains[] = { - [RK3368_PD_PERI] = DOMAIN_RK3368(BIT(13), BIT(12), BIT(6), true), - [RK3368_PD_VIO] = DOMAIN_RK3368(BIT(15), BIT(14), BIT(8), false), - [RK3368_PD_VIDEO] = DOMAIN_RK3368(BIT(14), BIT(13), BIT(7), false), - [RK3368_PD_GPU_0] = DOMAIN_RK3368(BIT(16), BIT(15), BIT(2), false), - [RK3368_PD_GPU_1] = DOMAIN_RK3368(BIT(17), BIT(16), BIT(2), false), + [RK3368_PD_PERI] = DOMAIN_RK3368("peri", BIT(13), BIT(12), BIT(6), true), + [RK3368_PD_VIO] = DOMAIN_RK3368("vio", BIT(15), BIT(14), BIT(8), false), + [RK3368_PD_VIDEO] = DOMAIN_RK3368("video", BIT(14), BIT(13), BIT(7), false), + [RK3368_PD_GPU_0] = DOMAIN_RK3368("gpu_0", BIT(16), BIT(15), BIT(2), false), + [RK3368_PD_GPU_1] = DOMAIN_RK3368("gpu_1", BIT(17), BIT(16), BIT(2), false), }; static const struct rockchip_domain_info rk3399_pm_domains[] = { - [RK3399_PD_TCPD0] = DOMAIN_RK3399(BIT(8), BIT(8), 0, false), - [RK3399_PD_TCPD1] = DOMAIN_RK3399(BIT(9), BIT(9), 0, false), - [RK3399_PD_CCI] = DOMAIN_RK3399(BIT(10), BIT(10), 0, true), - [RK3399_PD_CCI0] = DOMAIN_RK3399(0, 0, BIT(15), true), - [RK3399_PD_CCI1] = DOMAIN_RK3399(0, 0, BIT(16), true), - [RK3399_PD_PERILP] = DOMAIN_RK3399(BIT(11), BIT(11), BIT(1), true), - [RK3399_PD_PERIHP] = DOMAIN_RK3399(BIT(12), BIT(12), BIT(2), true), - [RK3399_PD_CENTER] = DOMAIN_RK3399(BIT(13), BIT(13), BIT(14), true), - [RK3399_PD_VIO] = DOMAIN_RK3399(BIT(14), BIT(14), BIT(17), false), - [RK3399_PD_GPU] = DOMAIN_RK3399(BIT(15), BIT(15), BIT(0), false), - [RK3399_PD_VCODEC] = DOMAIN_RK3399(BIT(16), BIT(16), BIT(3), false), - [RK3399_PD_VDU] = DOMAIN_RK3399(BIT(17), BIT(17), BIT(4), false), - [RK3399_PD_RGA] = DOMAIN_RK3399(BIT(18), BIT(18), BIT(5), false), - [RK3399_PD_IEP] = DOMAIN_RK3399(BIT(19), BIT(19), BIT(6), false), - [RK3399_PD_VO] = DOMAIN_RK3399(BIT(20), BIT(20), 0, false), - [RK3399_PD_VOPB] = DOMAIN_RK3399(0, 0, BIT(7), false), - [RK3399_PD_VOPL] = DOMAIN_RK3399(0, 0, BIT(8), false), - [RK3399_PD_ISP0] = DOMAIN_RK3399(BIT(22), BIT(22), BIT(9), false), - [RK3399_PD_ISP1] = DOMAIN_RK3399(BIT(23), BIT(23), BIT(10), false), - [RK3399_PD_HDCP] = DOMAIN_RK3399(BIT(24), BIT(24), BIT(11), false), - [RK3399_PD_GMAC] = DOMAIN_RK3399(BIT(25), BIT(25), BIT(23), true), - [RK3399_PD_EMMC] = DOMAIN_RK3399(BIT(26), BIT(26), BIT(24), true), - [RK3399_PD_USB3] = DOMAIN_RK3399(BIT(27), BIT(27), BIT(12), true), - [RK3399_PD_EDP] = DOMAIN_RK3399(BIT(28), BIT(28), BIT(22), false), - [RK3399_PD_GIC] = DOMAIN_RK3399(BIT(29), BIT(29), BIT(27), true), - [RK3399_PD_SD] = DOMAIN_RK3399(BIT(30), BIT(30), BIT(28), true), - [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399(BIT(31), BIT(31), BIT(29), true), + [RK3399_PD_TCPD0] = DOMAIN_RK3399("tcpd0", BIT(8), BIT(8), 0, false), + [RK3399_PD_TCPD1] = DOMAIN_RK3399("tcpd1", BIT(9), BIT(9), 0, false), + [RK3399_PD_CCI] = DOMAIN_RK3399("cci", BIT(10), BIT(10), 0, true), + [RK3399_PD_CCI0] = DOMAIN_RK3399("cci0", 0, 0, BIT(15), true), + [RK3399_PD_CCI1] = DOMAIN_RK3399("cci1", 0, 0, BIT(16), true), + [RK3399_PD_PERILP] = DOMAIN_RK3399("perilp", BIT(11), BIT(11), BIT(1), true), + [RK3399_PD_PERIHP] = DOMAIN_RK3399("perihp", BIT(12), BIT(12), BIT(2), true), + [RK3399_PD_CENTER] = DOMAIN_RK3399("center", BIT(13), BIT(13), BIT(14), true), + [RK3399_PD_VIO] = DOMAIN_RK3399("vio", BIT(14), BIT(14), BIT(17), false), + [RK3399_PD_GPU] = DOMAIN_RK3399("gpu", BIT(15), BIT(15), BIT(0), false), + [RK3399_PD_VCODEC] = DOMAIN_RK3399("vcodec", BIT(16), BIT(16), BIT(3), false), + [RK3399_PD_VDU] = DOMAIN_RK3399("vdu", BIT(17), BIT(17), BIT(4), false), + [RK3399_PD_RGA] = DOMAIN_RK3399("rga", BIT(18), BIT(18), BIT(5), false), + [RK3399_PD_IEP] = DOMAIN_RK3399("iep", BIT(19), BIT(19), BIT(6), false), + [RK3399_PD_VO] = DOMAIN_RK3399("vo", BIT(20), BIT(20), 0, false), + [RK3399_PD_VOPB] = DOMAIN_RK3399("vopb", 0, 0, BIT(7), false), + [RK3399_PD_VOPL] = DOMAIN_RK3399("vopl", 0, 0, BIT(8), false), + [RK3399_PD_ISP0] = DOMAIN_RK3399("isp0", BIT(22), BIT(22), BIT(9), false), + [RK3399_PD_ISP1] = DOMAIN_RK3399("isp1", BIT(23), BIT(23), BIT(10), false), + [RK3399_PD_HDCP] = DOMAIN_RK3399("hdcp", BIT(24), BIT(24), BIT(11), false), + [RK3399_PD_GMAC] = DOMAIN_RK3399("gmac", BIT(25), BIT(25), BIT(23), true), + [RK3399_PD_EMMC] = DOMAIN_RK3399("emmc", BIT(26), BIT(26), BIT(24), true), + [RK3399_PD_USB3] = DOMAIN_RK3399("usb3", BIT(27), BIT(27), BIT(12), true), + [RK3399_PD_EDP] = DOMAIN_RK3399("edp", BIT(28), BIT(28), BIT(22), false), + [RK3399_PD_GIC] = DOMAIN_RK3399("gic", BIT(29), BIT(29), BIT(27), true), + [RK3399_PD_SD] = DOMAIN_RK3399("sd", BIT(30), BIT(30), BIT(28), true), + [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true), }; static const struct rockchip_pmu_info px30_pmu = { -- 2.17.1 ^ permalink raw reply related [flat|nested] 75+ messages in thread
* [RESEND PATCH v5 07/11] soc: rockchip: pm-domains: Add a meaningful power domain name @ 2021-03-26 9:37 ` Elaine Zhang 0 siblings, 0 replies; 75+ messages in thread From: Elaine Zhang @ 2021-03-26 9:37 UTC (permalink / raw) To: robh+dt, heiko Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang Add the power domains names to the power domain info struct so we have meaningful name for every power domain. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- drivers/soc/rockchip/pm_domains.c | 221 +++++++++++++++--------------- 1 file changed, 114 insertions(+), 107 deletions(-) diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c index 54eb6cfc5d5b..3e6268c30d7e 100644 --- a/drivers/soc/rockchip/pm_domains.c +++ b/drivers/soc/rockchip/pm_domains.c @@ -29,6 +29,7 @@ #include <dt-bindings/power/rk3399-power.h> struct rockchip_domain_info { + const char *name; int pwr_mask; int status_mask; int req_mask; @@ -85,8 +86,9 @@ struct rockchip_pmu { #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd) -#define DOMAIN(pwr, status, req, idle, ack, wakeup) \ +#define DOMAIN(_name, pwr, status, req, idle, ack, wakeup) \ { \ + .name = _name, \ .pwr_mask = (pwr), \ .status_mask = (status), \ .req_mask = (req), \ @@ -95,8 +97,9 @@ struct rockchip_pmu { .active_wakeup = (wakeup), \ } -#define DOMAIN_M(pwr, status, req, idle, ack, wakeup) \ +#define DOMAIN_M(_name, pwr, status, req, idle, ack, wakeup) \ { \ + .name = _name, \ .pwr_w_mask = (pwr) << 16, \ .pwr_mask = (pwr), \ .status_mask = (status), \ @@ -107,8 +110,9 @@ struct rockchip_pmu { .active_wakeup = wakeup, \ } -#define DOMAIN_RK3036(req, ack, idle, wakeup) \ +#define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \ { \ + .name = _name, \ .req_mask = (req), \ .req_w_mask = (req) << 16, \ .ack_mask = (ack), \ @@ -116,20 +120,20 @@ struct rockchip_pmu { .active_wakeup = wakeup, \ } -#define DOMAIN_PX30(pwr, status, req, wakeup) \ - DOMAIN_M(pwr, status, req, (req) << 16, req, wakeup) +#define DOMAIN_PX30(name, pwr, status, req, wakeup) \ + DOMAIN_M(name, pwr, status, req, (req) << 16, req, wakeup) -#define DOMAIN_RK3288(pwr, status, req, wakeup) \ - DOMAIN(pwr, status, req, req, (req) << 16, wakeup) +#define DOMAIN_RK3288(name, pwr, status, req, wakeup) \ + DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup) -#define DOMAIN_RK3328(pwr, status, req, wakeup) \ - DOMAIN_M(pwr, pwr, req, (req) << 10, req, wakeup) +#define DOMAIN_RK3328(name, pwr, status, req, wakeup) \ + DOMAIN_M(name, pwr, pwr, req, (req) << 10, req, wakeup) -#define DOMAIN_RK3368(pwr, status, req, wakeup) \ - DOMAIN(pwr, status, req, (req) << 16, req, wakeup) +#define DOMAIN_RK3368(name, pwr, status, req, wakeup) \ + DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup) -#define DOMAIN_RK3399(pwr, status, req, wakeup) \ - DOMAIN(pwr, status, req, req, req, wakeup) +#define DOMAIN_RK3399(name, pwr, status, req, wakeup) \ + DOMAIN(name, pwr, status, req, req, req, wakeup) static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd) { @@ -490,7 +494,10 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, goto err_unprepare_clocks; } - pd->genpd.name = node->name; + if (!pd->info->name) + pd->genpd.name = node->name; + else + pd->genpd.name = pd->info->name; pd->genpd.power_off = rockchip_pd_power_off; pd->genpd.power_on = rockchip_pd_power_on; pd->genpd.attach_dev = rockchip_pd_attach_dev; @@ -716,129 +723,129 @@ static int rockchip_pm_domain_probe(struct platform_device *pdev) } static const struct rockchip_domain_info px30_pm_domains[] = { - [PX30_PD_USB] = DOMAIN_PX30(BIT(5), BIT(5), BIT(10), false), - [PX30_PD_SDCARD] = DOMAIN_PX30(BIT(8), BIT(8), BIT(9), false), - [PX30_PD_GMAC] = DOMAIN_PX30(BIT(10), BIT(10), BIT(6), false), - [PX30_PD_MMC_NAND] = DOMAIN_PX30(BIT(11), BIT(11), BIT(5), false), - [PX30_PD_VPU] = DOMAIN_PX30(BIT(12), BIT(12), BIT(14), false), - [PX30_PD_VO] = DOMAIN_PX30(BIT(13), BIT(13), BIT(7), false), - [PX30_PD_VI] = DOMAIN_PX30(BIT(14), BIT(14), BIT(8), false), - [PX30_PD_GPU] = DOMAIN_PX30(BIT(15), BIT(15), BIT(2), false), + [PX30_PD_USB] = DOMAIN_PX30("usb", BIT(5), BIT(5), BIT(10), false), + [PX30_PD_SDCARD] = DOMAIN_PX30("sdcard", BIT(8), BIT(8), BIT(9), false), + [PX30_PD_GMAC] = DOMAIN_PX30("gmac", BIT(10), BIT(10), BIT(6), false), + [PX30_PD_MMC_NAND] = DOMAIN_PX30("mmc_nand", BIT(11), BIT(11), BIT(5), false), + [PX30_PD_VPU] = DOMAIN_PX30("vpu", BIT(12), BIT(12), BIT(14), false), + [PX30_PD_VO] = DOMAIN_PX30("vo", BIT(13), BIT(13), BIT(7), false), + [PX30_PD_VI] = DOMAIN_PX30("vi", BIT(14), BIT(14), BIT(8), false), + [PX30_PD_GPU] = DOMAIN_PX30("gpu", BIT(15), BIT(15), BIT(2), false), }; static const struct rockchip_domain_info rk3036_pm_domains[] = { - [RK3036_PD_MSCH] = DOMAIN_RK3036(BIT(14), BIT(23), BIT(30), true), - [RK3036_PD_CORE] = DOMAIN_RK3036(BIT(13), BIT(17), BIT(24), false), - [RK3036_PD_PERI] = DOMAIN_RK3036(BIT(12), BIT(18), BIT(25), false), - [RK3036_PD_VIO] = DOMAIN_RK3036(BIT(11), BIT(19), BIT(26), false), - [RK3036_PD_VPU] = DOMAIN_RK3036(BIT(10), BIT(20), BIT(27), false), - [RK3036_PD_GPU] = DOMAIN_RK3036(BIT(9), BIT(21), BIT(28), false), - [RK3036_PD_SYS] = DOMAIN_RK3036(BIT(8), BIT(22), BIT(29), false), + [RK3036_PD_MSCH] = DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true), + [RK3036_PD_CORE] = DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false), + [RK3036_PD_PERI] = DOMAIN_RK3036("peri", BIT(12), BIT(18), BIT(25), false), + [RK3036_PD_VIO] = DOMAIN_RK3036("vio", BIT(11), BIT(19), BIT(26), false), + [RK3036_PD_VPU] = DOMAIN_RK3036("vpu", BIT(10), BIT(20), BIT(27), false), + [RK3036_PD_GPU] = DOMAIN_RK3036("gpu", BIT(9), BIT(21), BIT(28), false), + [RK3036_PD_SYS] = DOMAIN_RK3036("sys", BIT(8), BIT(22), BIT(29), false), }; static const struct rockchip_domain_info rk3066_pm_domains[] = { - [RK3066_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), - [RK3066_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), - [RK3066_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), - [RK3066_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), - [RK3066_PD_CPU] = DOMAIN(0, BIT(5), BIT(1), BIT(26), BIT(31), false), + [RK3066_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), + [RK3066_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), + [RK3066_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), + [RK3066_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), + [RK3066_PD_CPU] = DOMAIN("cpu", 0, BIT(5), BIT(1), BIT(26), BIT(31), false), }; static const struct rockchip_domain_info rk3128_pm_domains[] = { - [RK3128_PD_CORE] = DOMAIN_RK3288(BIT(0), BIT(0), BIT(4), false), - [RK3128_PD_MSCH] = DOMAIN_RK3288(0, 0, BIT(6), true), - [RK3128_PD_VIO] = DOMAIN_RK3288(BIT(3), BIT(3), BIT(2), false), - [RK3128_PD_VIDEO] = DOMAIN_RK3288(BIT(2), BIT(2), BIT(1), false), - [RK3128_PD_GPU] = DOMAIN_RK3288(BIT(1), BIT(1), BIT(3), false), + [RK3128_PD_CORE] = DOMAIN_RK3288("core", BIT(0), BIT(0), BIT(4), false), + [RK3128_PD_MSCH] = DOMAIN_RK3288("msch", 0, 0, BIT(6), true), + [RK3128_PD_VIO] = DOMAIN_RK3288("vio", BIT(3), BIT(3), BIT(2), false), + [RK3128_PD_VIDEO] = DOMAIN_RK3288("video", BIT(2), BIT(2), BIT(1), false), + [RK3128_PD_GPU] = DOMAIN_RK3288("gpu", BIT(1), BIT(1), BIT(3), false), }; static const struct rockchip_domain_info rk3188_pm_domains[] = { - [RK3188_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), - [RK3188_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), - [RK3188_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), - [RK3188_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), - [RK3188_PD_CPU] = DOMAIN(BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false), + [RK3188_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), + [RK3188_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), + [RK3188_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), + [RK3188_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), + [RK3188_PD_CPU] = DOMAIN("cpu", BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false), }; static const struct rockchip_domain_info rk3228_pm_domains[] = { - [RK3228_PD_CORE] = DOMAIN_RK3036(BIT(0), BIT(0), BIT(16), true), - [RK3228_PD_MSCH] = DOMAIN_RK3036(BIT(1), BIT(1), BIT(17), true), - [RK3228_PD_BUS] = DOMAIN_RK3036(BIT(2), BIT(2), BIT(18), true), - [RK3228_PD_SYS] = DOMAIN_RK3036(BIT(3), BIT(3), BIT(19), true), - [RK3228_PD_VIO] = DOMAIN_RK3036(BIT(4), BIT(4), BIT(20), false), - [RK3228_PD_VOP] = DOMAIN_RK3036(BIT(5), BIT(5), BIT(21), false), - [RK3228_PD_VPU] = DOMAIN_RK3036(BIT(6), BIT(6), BIT(22), false), - [RK3228_PD_RKVDEC] = DOMAIN_RK3036(BIT(7), BIT(7), BIT(23), false), - [RK3228_PD_GPU] = DOMAIN_RK3036(BIT(8), BIT(8), BIT(24), false), - [RK3228_PD_PERI] = DOMAIN_RK3036(BIT(9), BIT(9), BIT(25), true), - [RK3228_PD_GMAC] = DOMAIN_RK3036(BIT(10), BIT(10), BIT(26), false), + [RK3228_PD_CORE] = DOMAIN_RK3036("core", BIT(0), BIT(0), BIT(16), true), + [RK3228_PD_MSCH] = DOMAIN_RK3036("msch", BIT(1), BIT(1), BIT(17), true), + [RK3228_PD_BUS] = DOMAIN_RK3036("bus", BIT(2), BIT(2), BIT(18), true), + [RK3228_PD_SYS] = DOMAIN_RK3036("sys", BIT(3), BIT(3), BIT(19), true), + [RK3228_PD_VIO] = DOMAIN_RK3036("vio", BIT(4), BIT(4), BIT(20), false), + [RK3228_PD_VOP] = DOMAIN_RK3036("vop", BIT(5), BIT(5), BIT(21), false), + [RK3228_PD_VPU] = DOMAIN_RK3036("vpu", BIT(6), BIT(6), BIT(22), false), + [RK3228_PD_RKVDEC] = DOMAIN_RK3036("vdec", BIT(7), BIT(7), BIT(23), false), + [RK3228_PD_GPU] = DOMAIN_RK3036("gpu", BIT(8), BIT(8), BIT(24), false), + [RK3228_PD_PERI] = DOMAIN_RK3036("peri", BIT(9), BIT(9), BIT(25), true), + [RK3228_PD_GMAC] = DOMAIN_RK3036("gmac", BIT(10), BIT(10), BIT(26), false), }; static const struct rockchip_domain_info rk3288_pm_domains[] = { - [RK3288_PD_VIO] = DOMAIN_RK3288(BIT(7), BIT(7), BIT(4), false), - [RK3288_PD_HEVC] = DOMAIN_RK3288(BIT(14), BIT(10), BIT(9), false), - [RK3288_PD_VIDEO] = DOMAIN_RK3288(BIT(8), BIT(8), BIT(3), false), - [RK3288_PD_GPU] = DOMAIN_RK3288(BIT(9), BIT(9), BIT(2), false), + [RK3288_PD_VIO] = DOMAIN_RK3288("vio", BIT(7), BIT(7), BIT(4), false), + [RK3288_PD_HEVC] = DOMAIN_RK3288("hevc", BIT(14), BIT(10), BIT(9), false), + [RK3288_PD_VIDEO] = DOMAIN_RK3288("video", BIT(8), BIT(8), BIT(3), false), + [RK3288_PD_GPU] = DOMAIN_RK3288("gpu", BIT(9), BIT(9), BIT(2), false), }; static const struct rockchip_domain_info rk3328_pm_domains[] = { - [RK3328_PD_CORE] = DOMAIN_RK3328(0, BIT(0), BIT(0), false), - [RK3328_PD_GPU] = DOMAIN_RK3328(0, BIT(1), BIT(1), false), - [RK3328_PD_BUS] = DOMAIN_RK3328(0, BIT(2), BIT(2), true), - [RK3328_PD_MSCH] = DOMAIN_RK3328(0, BIT(3), BIT(3), true), - [RK3328_PD_PERI] = DOMAIN_RK3328(0, BIT(4), BIT(4), true), - [RK3328_PD_VIDEO] = DOMAIN_RK3328(0, BIT(5), BIT(5), false), - [RK3328_PD_HEVC] = DOMAIN_RK3328(0, BIT(6), BIT(6), false), - [RK3328_PD_VIO] = DOMAIN_RK3328(0, BIT(8), BIT(8), false), - [RK3328_PD_VPU] = DOMAIN_RK3328(0, BIT(9), BIT(9), false), + [RK3328_PD_CORE] = DOMAIN_RK3328("core", 0, BIT(0), BIT(0), false), + [RK3328_PD_GPU] = DOMAIN_RK3328("gpu", 0, BIT(1), BIT(1), false), + [RK3328_PD_BUS] = DOMAIN_RK3328("bus", 0, BIT(2), BIT(2), true), + [RK3328_PD_MSCH] = DOMAIN_RK3328("msch", 0, BIT(3), BIT(3), true), + [RK3328_PD_PERI] = DOMAIN_RK3328("peri", 0, BIT(4), BIT(4), true), + [RK3328_PD_VIDEO] = DOMAIN_RK3328("video", 0, BIT(5), BIT(5), false), + [RK3328_PD_HEVC] = DOMAIN_RK3328("hevc", 0, BIT(6), BIT(6), false), + [RK3328_PD_VIO] = DOMAIN_RK3328("vio", 0, BIT(8), BIT(8), false), + [RK3328_PD_VPU] = DOMAIN_RK3328("vpu", 0, BIT(9), BIT(9), false), }; static const struct rockchip_domain_info rk3366_pm_domains[] = { - [RK3366_PD_PERI] = DOMAIN_RK3368(BIT(10), BIT(10), BIT(6), true), - [RK3366_PD_VIO] = DOMAIN_RK3368(BIT(14), BIT(14), BIT(8), false), - [RK3366_PD_VIDEO] = DOMAIN_RK3368(BIT(13), BIT(13), BIT(7), false), - [RK3366_PD_RKVDEC] = DOMAIN_RK3368(BIT(11), BIT(11), BIT(7), false), - [RK3366_PD_WIFIBT] = DOMAIN_RK3368(BIT(8), BIT(8), BIT(9), false), - [RK3366_PD_VPU] = DOMAIN_RK3368(BIT(12), BIT(12), BIT(7), false), - [RK3366_PD_GPU] = DOMAIN_RK3368(BIT(15), BIT(15), BIT(2), false), + [RK3366_PD_PERI] = DOMAIN_RK3368("peri", BIT(10), BIT(10), BIT(6), true), + [RK3366_PD_VIO] = DOMAIN_RK3368("vio", BIT(14), BIT(14), BIT(8), false), + [RK3366_PD_VIDEO] = DOMAIN_RK3368("video", BIT(13), BIT(13), BIT(7), false), + [RK3366_PD_RKVDEC] = DOMAIN_RK3368("vdec", BIT(11), BIT(11), BIT(7), false), + [RK3366_PD_WIFIBT] = DOMAIN_RK3368("wifibt", BIT(8), BIT(8), BIT(9), false), + [RK3366_PD_VPU] = DOMAIN_RK3368("vpu", BIT(12), BIT(12), BIT(7), false), + [RK3366_PD_GPU] = DOMAIN_RK3368("gpu", BIT(15), BIT(15), BIT(2), false), }; static const struct rockchip_domain_info rk3368_pm_domains[] = { - [RK3368_PD_PERI] = DOMAIN_RK3368(BIT(13), BIT(12), BIT(6), true), - [RK3368_PD_VIO] = DOMAIN_RK3368(BIT(15), BIT(14), BIT(8), false), - [RK3368_PD_VIDEO] = DOMAIN_RK3368(BIT(14), BIT(13), BIT(7), false), - [RK3368_PD_GPU_0] = DOMAIN_RK3368(BIT(16), BIT(15), BIT(2), false), - [RK3368_PD_GPU_1] = DOMAIN_RK3368(BIT(17), BIT(16), BIT(2), false), + [RK3368_PD_PERI] = DOMAIN_RK3368("peri", BIT(13), BIT(12), BIT(6), true), + [RK3368_PD_VIO] = DOMAIN_RK3368("vio", BIT(15), BIT(14), BIT(8), false), + [RK3368_PD_VIDEO] = DOMAIN_RK3368("video", BIT(14), BIT(13), BIT(7), false), + [RK3368_PD_GPU_0] = DOMAIN_RK3368("gpu_0", BIT(16), BIT(15), BIT(2), false), + [RK3368_PD_GPU_1] = DOMAIN_RK3368("gpu_1", BIT(17), BIT(16), BIT(2), false), }; static const struct rockchip_domain_info rk3399_pm_domains[] = { - [RK3399_PD_TCPD0] = DOMAIN_RK3399(BIT(8), BIT(8), 0, false), - [RK3399_PD_TCPD1] = DOMAIN_RK3399(BIT(9), BIT(9), 0, false), - [RK3399_PD_CCI] = DOMAIN_RK3399(BIT(10), BIT(10), 0, true), - [RK3399_PD_CCI0] = DOMAIN_RK3399(0, 0, BIT(15), true), - [RK3399_PD_CCI1] = DOMAIN_RK3399(0, 0, BIT(16), true), - [RK3399_PD_PERILP] = DOMAIN_RK3399(BIT(11), BIT(11), BIT(1), true), - [RK3399_PD_PERIHP] = DOMAIN_RK3399(BIT(12), BIT(12), BIT(2), true), - [RK3399_PD_CENTER] = DOMAIN_RK3399(BIT(13), BIT(13), BIT(14), true), - [RK3399_PD_VIO] = DOMAIN_RK3399(BIT(14), BIT(14), BIT(17), false), - [RK3399_PD_GPU] = DOMAIN_RK3399(BIT(15), BIT(15), BIT(0), false), - [RK3399_PD_VCODEC] = DOMAIN_RK3399(BIT(16), BIT(16), BIT(3), false), - [RK3399_PD_VDU] = DOMAIN_RK3399(BIT(17), BIT(17), BIT(4), false), - [RK3399_PD_RGA] = DOMAIN_RK3399(BIT(18), BIT(18), BIT(5), false), - [RK3399_PD_IEP] = DOMAIN_RK3399(BIT(19), BIT(19), BIT(6), false), - [RK3399_PD_VO] = DOMAIN_RK3399(BIT(20), BIT(20), 0, false), - [RK3399_PD_VOPB] = DOMAIN_RK3399(0, 0, BIT(7), false), - [RK3399_PD_VOPL] = DOMAIN_RK3399(0, 0, BIT(8), false), - [RK3399_PD_ISP0] = DOMAIN_RK3399(BIT(22), BIT(22), BIT(9), false), - [RK3399_PD_ISP1] = DOMAIN_RK3399(BIT(23), BIT(23), BIT(10), false), - [RK3399_PD_HDCP] = DOMAIN_RK3399(BIT(24), BIT(24), BIT(11), false), - [RK3399_PD_GMAC] = DOMAIN_RK3399(BIT(25), BIT(25), BIT(23), true), - [RK3399_PD_EMMC] = DOMAIN_RK3399(BIT(26), BIT(26), BIT(24), true), - [RK3399_PD_USB3] = DOMAIN_RK3399(BIT(27), BIT(27), BIT(12), true), - [RK3399_PD_EDP] = DOMAIN_RK3399(BIT(28), BIT(28), BIT(22), false), - [RK3399_PD_GIC] = DOMAIN_RK3399(BIT(29), BIT(29), BIT(27), true), - [RK3399_PD_SD] = DOMAIN_RK3399(BIT(30), BIT(30), BIT(28), true), - [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399(BIT(31), BIT(31), BIT(29), true), + [RK3399_PD_TCPD0] = DOMAIN_RK3399("tcpd0", BIT(8), BIT(8), 0, false), + [RK3399_PD_TCPD1] = DOMAIN_RK3399("tcpd1", BIT(9), BIT(9), 0, false), + [RK3399_PD_CCI] = DOMAIN_RK3399("cci", BIT(10), BIT(10), 0, true), + [RK3399_PD_CCI0] = DOMAIN_RK3399("cci0", 0, 0, BIT(15), true), + [RK3399_PD_CCI1] = DOMAIN_RK3399("cci1", 0, 0, BIT(16), true), + [RK3399_PD_PERILP] = DOMAIN_RK3399("perilp", BIT(11), BIT(11), BIT(1), true), + [RK3399_PD_PERIHP] = DOMAIN_RK3399("perihp", BIT(12), BIT(12), BIT(2), true), + [RK3399_PD_CENTER] = DOMAIN_RK3399("center", BIT(13), BIT(13), BIT(14), true), + [RK3399_PD_VIO] = DOMAIN_RK3399("vio", BIT(14), BIT(14), BIT(17), false), + [RK3399_PD_GPU] = DOMAIN_RK3399("gpu", BIT(15), BIT(15), BIT(0), false), + [RK3399_PD_VCODEC] = DOMAIN_RK3399("vcodec", BIT(16), BIT(16), BIT(3), false), + [RK3399_PD_VDU] = DOMAIN_RK3399("vdu", BIT(17), BIT(17), BIT(4), false), + [RK3399_PD_RGA] = DOMAIN_RK3399("rga", BIT(18), BIT(18), BIT(5), false), + [RK3399_PD_IEP] = DOMAIN_RK3399("iep", BIT(19), BIT(19), BIT(6), false), + [RK3399_PD_VO] = DOMAIN_RK3399("vo", BIT(20), BIT(20), 0, false), + [RK3399_PD_VOPB] = DOMAIN_RK3399("vopb", 0, 0, BIT(7), false), + [RK3399_PD_VOPL] = DOMAIN_RK3399("vopl", 0, 0, BIT(8), false), + [RK3399_PD_ISP0] = DOMAIN_RK3399("isp0", BIT(22), BIT(22), BIT(9), false), + [RK3399_PD_ISP1] = DOMAIN_RK3399("isp1", BIT(23), BIT(23), BIT(10), false), + [RK3399_PD_HDCP] = DOMAIN_RK3399("hdcp", BIT(24), BIT(24), BIT(11), false), + [RK3399_PD_GMAC] = DOMAIN_RK3399("gmac", BIT(25), BIT(25), BIT(23), true), + [RK3399_PD_EMMC] = DOMAIN_RK3399("emmc", BIT(26), BIT(26), BIT(24), true), + [RK3399_PD_USB3] = DOMAIN_RK3399("usb3", BIT(27), BIT(27), BIT(12), true), + [RK3399_PD_EDP] = DOMAIN_RK3399("edp", BIT(28), BIT(28), BIT(22), false), + [RK3399_PD_GIC] = DOMAIN_RK3399("gic", BIT(29), BIT(29), BIT(27), true), + [RK3399_PD_SD] = DOMAIN_RK3399("sd", BIT(30), BIT(30), BIT(28), true), + [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true), }; static const struct rockchip_pmu_info px30_pmu = { -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 75+ messages in thread
* Re: [RESEND PATCH v5 07/11] soc: rockchip: pm-domains: Add a meaningful power domain name 2021-03-26 9:37 ` Elaine Zhang (?) @ 2021-03-26 9:52 ` Heiko Stübner -1 siblings, 0 replies; 75+ messages in thread From: Heiko Stübner @ 2021-03-26 9:52 UTC (permalink / raw) To: robh+dt, Elaine Zhang Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang, enric.balletbo Hi Elaine, [also adding that answer to the resend :-) ] Am Freitag, 26. März 2021, 10:17:39 CET schrieb Elaine Zhang: > Add the power domains names to the power domain info struct so we > have meaningful name for every power domain. > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> I like that approach very much, there is one tiny comment below. > --- > drivers/soc/rockchip/pm_domains.c | 217 +++++++++++++++--------------- > 1 file changed, 112 insertions(+), 105 deletions(-) > > diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c > index 54eb6cfc5d5b..d661d967079f 100644 > --- a/drivers/soc/rockchip/pm_domains.c > +++ b/drivers/soc/rockchip/pm_domains.c > @@ -29,6 +29,7 @@ > #include <dt-bindings/power/rk3399-power.h> > > struct rockchip_domain_info { > + const char *name; > int pwr_mask; > int status_mask; > int req_mask; > @@ -85,8 +86,9 @@ struct rockchip_pmu { > > #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd) > > -#define DOMAIN(pwr, status, req, idle, ack, wakeup) \ > +#define DOMAIN(_name, pwr, status, req, idle, ack, wakeup) \ > { \ > + .name = _name, \ > .pwr_mask = (pwr), \ > .status_mask = (status), \ > .req_mask = (req), \ > @@ -95,8 +97,9 @@ struct rockchip_pmu { > .active_wakeup = (wakeup), \ > } > > -#define DOMAIN_M(pwr, status, req, idle, ack, wakeup) \ > +#define DOMAIN_M(_name, pwr, status, req, idle, ack, wakeup) \ > { \ > + .name = _name, \ > .pwr_w_mask = (pwr) << 16, \ > .pwr_mask = (pwr), \ > .status_mask = (status), \ > @@ -107,8 +110,9 @@ struct rockchip_pmu { > .active_wakeup = wakeup, \ > } > > -#define DOMAIN_RK3036(req, ack, idle, wakeup) \ > +#define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \ > { \ > + .name = _name, \ > .req_mask = (req), \ > .req_w_mask = (req) << 16, \ > .ack_mask = (ack), \ > @@ -119,17 +123,17 @@ struct rockchip_pmu { > #define DOMAIN_PX30(pwr, status, req, wakeup) \ > DOMAIN_M(pwr, status, req, (req) << 16, req, wakeup) > > -#define DOMAIN_RK3288(pwr, status, req, wakeup) \ > - DOMAIN(pwr, status, req, req, (req) << 16, wakeup) > +#define DOMAIN_RK3288(name, pwr, status, req, wakeup) \ > + DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup) > > -#define DOMAIN_RK3328(pwr, status, req, wakeup) \ > - DOMAIN_M(pwr, pwr, req, (req) << 10, req, wakeup) > +#define DOMAIN_RK3328(name, pwr, status, req, wakeup) \ > + DOMAIN_M(name, pwr, pwr, req, (req) << 10, req, wakeup) > > -#define DOMAIN_RK3368(pwr, status, req, wakeup) \ > - DOMAIN(pwr, status, req, (req) << 16, req, wakeup) > +#define DOMAIN_RK3368(name, pwr, status, req, wakeup) \ > + DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup) > > -#define DOMAIN_RK3399(pwr, status, req, wakeup) \ > - DOMAIN(pwr, status, req, req, req, wakeup) > +#define DOMAIN_RK3399(name, pwr, status, req, wakeup) \ > + DOMAIN(name, pwr, status, req, req, req, wakeup) > > static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd) > { > @@ -490,7 +494,10 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, > goto err_unprepare_clocks; > } > > - pd->genpd.name = node->name; > + if (!pd->info->name) > + pd->genpd.name = node->name; I guess we should make that "node->full_name" perhaps? And I guess it might be nicer to swap the cases if (pd->info->name) pd->genpd.name = pd->info->name else pd->genpd.name = node->full_name; for easier readability Heiko > + else > + pd->genpd.name = pd->info->name; > pd->genpd.power_off = rockchip_pd_power_off; > pd->genpd.power_on = rockchip_pd_power_on; > pd->genpd.attach_dev = rockchip_pd_attach_dev; > @@ -716,129 +723,129 @@ static int rockchip_pm_domain_probe(struct platform_device *pdev) > } > > static const struct rockchip_domain_info px30_pm_domains[] = { > - [PX30_PD_USB] = DOMAIN_PX30(BIT(5), BIT(5), BIT(10), false), > - [PX30_PD_SDCARD] = DOMAIN_PX30(BIT(8), BIT(8), BIT(9), false), > - [PX30_PD_GMAC] = DOMAIN_PX30(BIT(10), BIT(10), BIT(6), false), > - [PX30_PD_MMC_NAND] = DOMAIN_PX30(BIT(11), BIT(11), BIT(5), false), > - [PX30_PD_VPU] = DOMAIN_PX30(BIT(12), BIT(12), BIT(14), false), > - [PX30_PD_VO] = DOMAIN_PX30(BIT(13), BIT(13), BIT(7), false), > - [PX30_PD_VI] = DOMAIN_PX30(BIT(14), BIT(14), BIT(8), false), > - [PX30_PD_GPU] = DOMAIN_PX30(BIT(15), BIT(15), BIT(2), false), > + [PX30_PD_USB] = DOMAIN_PX30("usb", BIT(5), BIT(5), BIT(10), false), > + [PX30_PD_SDCARD] = DOMAIN_PX30("sdcard", BIT(8), BIT(8), BIT(9), false), > + [PX30_PD_GMAC] = DOMAIN_PX30("gmac", BIT(10), BIT(10), BIT(6), false), > + [PX30_PD_MMC_NAND] = DOMAIN_PX30("mmc_nand", BIT(11), BIT(11), BIT(5), false), > + [PX30_PD_VPU] = DOMAIN_PX30("vpu", BIT(12), BIT(12), BIT(14), false), > + [PX30_PD_VO] = DOMAIN_PX30("vo", BIT(13), BIT(13), BIT(7), false), > + [PX30_PD_VI] = DOMAIN_PX30("vi", BIT(14), BIT(14), BIT(8), false), > + [PX30_PD_GPU] = DOMAIN_PX30("gpu", BIT(15), BIT(15), BIT(2), false), > }; > > static const struct rockchip_domain_info rk3036_pm_domains[] = { > - [RK3036_PD_MSCH] = DOMAIN_RK3036(BIT(14), BIT(23), BIT(30), true), > - [RK3036_PD_CORE] = DOMAIN_RK3036(BIT(13), BIT(17), BIT(24), false), > - [RK3036_PD_PERI] = DOMAIN_RK3036(BIT(12), BIT(18), BIT(25), false), > - [RK3036_PD_VIO] = DOMAIN_RK3036(BIT(11), BIT(19), BIT(26), false), > - [RK3036_PD_VPU] = DOMAIN_RK3036(BIT(10), BIT(20), BIT(27), false), > - [RK3036_PD_GPU] = DOMAIN_RK3036(BIT(9), BIT(21), BIT(28), false), > - [RK3036_PD_SYS] = DOMAIN_RK3036(BIT(8), BIT(22), BIT(29), false), > + [RK3036_PD_MSCH] = DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true), > + [RK3036_PD_CORE] = DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false), > + [RK3036_PD_PERI] = DOMAIN_RK3036("peri", BIT(12), BIT(18), BIT(25), false), > + [RK3036_PD_VIO] = DOMAIN_RK3036("vio", BIT(11), BIT(19), BIT(26), false), > + [RK3036_PD_VPU] = DOMAIN_RK3036("vpu", BIT(10), BIT(20), BIT(27), false), > + [RK3036_PD_GPU] = DOMAIN_RK3036("gpu", BIT(9), BIT(21), BIT(28), false), > + [RK3036_PD_SYS] = DOMAIN_RK3036("sys", BIT(8), BIT(22), BIT(29), false), > }; > > static const struct rockchip_domain_info rk3066_pm_domains[] = { > - [RK3066_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > - [RK3066_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > - [RK3066_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > - [RK3066_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > - [RK3066_PD_CPU] = DOMAIN(0, BIT(5), BIT(1), BIT(26), BIT(31), false), > + [RK3066_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > + [RK3066_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > + [RK3066_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > + [RK3066_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > + [RK3066_PD_CPU] = DOMAIN("cpu", 0, BIT(5), BIT(1), BIT(26), BIT(31), false), > }; > > static const struct rockchip_domain_info rk3128_pm_domains[] = { > - [RK3128_PD_CORE] = DOMAIN_RK3288(BIT(0), BIT(0), BIT(4), false), > - [RK3128_PD_MSCH] = DOMAIN_RK3288(0, 0, BIT(6), true), > - [RK3128_PD_VIO] = DOMAIN_RK3288(BIT(3), BIT(3), BIT(2), false), > - [RK3128_PD_VIDEO] = DOMAIN_RK3288(BIT(2), BIT(2), BIT(1), false), > - [RK3128_PD_GPU] = DOMAIN_RK3288(BIT(1), BIT(1), BIT(3), false), > + [RK3128_PD_CORE] = DOMAIN_RK3288("core", BIT(0), BIT(0), BIT(4), false), > + [RK3128_PD_MSCH] = DOMAIN_RK3288("msch", 0, 0, BIT(6), true), > + [RK3128_PD_VIO] = DOMAIN_RK3288("vio", BIT(3), BIT(3), BIT(2), false), > + [RK3128_PD_VIDEO] = DOMAIN_RK3288("video", BIT(2), BIT(2), BIT(1), false), > + [RK3128_PD_GPU] = DOMAIN_RK3288("gpu", BIT(1), BIT(1), BIT(3), false), > }; > > static const struct rockchip_domain_info rk3188_pm_domains[] = { > - [RK3188_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > - [RK3188_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > - [RK3188_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > - [RK3188_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > - [RK3188_PD_CPU] = DOMAIN(BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false), > + [RK3188_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > + [RK3188_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > + [RK3188_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > + [RK3188_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > + [RK3188_PD_CPU] = DOMAIN("cpu", BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false), > }; > > static const struct rockchip_domain_info rk3228_pm_domains[] = { > - [RK3228_PD_CORE] = DOMAIN_RK3036(BIT(0), BIT(0), BIT(16), true), > - [RK3228_PD_MSCH] = DOMAIN_RK3036(BIT(1), BIT(1), BIT(17), true), > - [RK3228_PD_BUS] = DOMAIN_RK3036(BIT(2), BIT(2), BIT(18), true), > - [RK3228_PD_SYS] = DOMAIN_RK3036(BIT(3), BIT(3), BIT(19), true), > - [RK3228_PD_VIO] = DOMAIN_RK3036(BIT(4), BIT(4), BIT(20), false), > - [RK3228_PD_VOP] = DOMAIN_RK3036(BIT(5), BIT(5), BIT(21), false), > - [RK3228_PD_VPU] = DOMAIN_RK3036(BIT(6), BIT(6), BIT(22), false), > - [RK3228_PD_RKVDEC] = DOMAIN_RK3036(BIT(7), BIT(7), BIT(23), false), > - [RK3228_PD_GPU] = DOMAIN_RK3036(BIT(8), BIT(8), BIT(24), false), > - [RK3228_PD_PERI] = DOMAIN_RK3036(BIT(9), BIT(9), BIT(25), true), > - [RK3228_PD_GMAC] = DOMAIN_RK3036(BIT(10), BIT(10), BIT(26), false), > + [RK3228_PD_CORE] = DOMAIN_RK3036("core", BIT(0), BIT(0), BIT(16), true), > + [RK3228_PD_MSCH] = DOMAIN_RK3036("msch", BIT(1), BIT(1), BIT(17), true), > + [RK3228_PD_BUS] = DOMAIN_RK3036("bus", BIT(2), BIT(2), BIT(18), true), > + [RK3228_PD_SYS] = DOMAIN_RK3036("sys", BIT(3), BIT(3), BIT(19), true), > + [RK3228_PD_VIO] = DOMAIN_RK3036("vio", BIT(4), BIT(4), BIT(20), false), > + [RK3228_PD_VOP] = DOMAIN_RK3036("vop", BIT(5), BIT(5), BIT(21), false), > + [RK3228_PD_VPU] = DOMAIN_RK3036("vpu", BIT(6), BIT(6), BIT(22), false), > + [RK3228_PD_RKVDEC] = DOMAIN_RK3036("vdec", BIT(7), BIT(7), BIT(23), false), > + [RK3228_PD_GPU] = DOMAIN_RK3036("gpu", BIT(8), BIT(8), BIT(24), false), > + [RK3228_PD_PERI] = DOMAIN_RK3036("peri", BIT(9), BIT(9), BIT(25), true), > + [RK3228_PD_GMAC] = DOMAIN_RK3036("gmac", BIT(10), BIT(10), BIT(26), false), > }; > > static const struct rockchip_domain_info rk3288_pm_domains[] = { > - [RK3288_PD_VIO] = DOMAIN_RK3288(BIT(7), BIT(7), BIT(4), false), > - [RK3288_PD_HEVC] = DOMAIN_RK3288(BIT(14), BIT(10), BIT(9), false), > - [RK3288_PD_VIDEO] = DOMAIN_RK3288(BIT(8), BIT(8), BIT(3), false), > - [RK3288_PD_GPU] = DOMAIN_RK3288(BIT(9), BIT(9), BIT(2), false), > + [RK3288_PD_VIO] = DOMAIN_RK3288("vio", BIT(7), BIT(7), BIT(4), false), > + [RK3288_PD_HEVC] = DOMAIN_RK3288("hevc", BIT(14), BIT(10), BIT(9), false), > + [RK3288_PD_VIDEO] = DOMAIN_RK3288("video", BIT(8), BIT(8), BIT(3), false), > + [RK3288_PD_GPU] = DOMAIN_RK3288("gpu", BIT(9), BIT(9), BIT(2), false), > }; > > static const struct rockchip_domain_info rk3328_pm_domains[] = { > - [RK3328_PD_CORE] = DOMAIN_RK3328(0, BIT(0), BIT(0), false), > - [RK3328_PD_GPU] = DOMAIN_RK3328(0, BIT(1), BIT(1), false), > - [RK3328_PD_BUS] = DOMAIN_RK3328(0, BIT(2), BIT(2), true), > - [RK3328_PD_MSCH] = DOMAIN_RK3328(0, BIT(3), BIT(3), true), > - [RK3328_PD_PERI] = DOMAIN_RK3328(0, BIT(4), BIT(4), true), > - [RK3328_PD_VIDEO] = DOMAIN_RK3328(0, BIT(5), BIT(5), false), > - [RK3328_PD_HEVC] = DOMAIN_RK3328(0, BIT(6), BIT(6), false), > - [RK3328_PD_VIO] = DOMAIN_RK3328(0, BIT(8), BIT(8), false), > - [RK3328_PD_VPU] = DOMAIN_RK3328(0, BIT(9), BIT(9), false), > + [RK3328_PD_CORE] = DOMAIN_RK3328("core", 0, BIT(0), BIT(0), false), > + [RK3328_PD_GPU] = DOMAIN_RK3328("gpu", 0, BIT(1), BIT(1), false), > + [RK3328_PD_BUS] = DOMAIN_RK3328("bus", 0, BIT(2), BIT(2), true), > + [RK3328_PD_MSCH] = DOMAIN_RK3328("msch", 0, BIT(3), BIT(3), true), > + [RK3328_PD_PERI] = DOMAIN_RK3328("peri", 0, BIT(4), BIT(4), true), > + [RK3328_PD_VIDEO] = DOMAIN_RK3328("video", 0, BIT(5), BIT(5), false), > + [RK3328_PD_HEVC] = DOMAIN_RK3328("hevc", 0, BIT(6), BIT(6), false), > + [RK3328_PD_VIO] = DOMAIN_RK3328("vio", 0, BIT(8), BIT(8), false), > + [RK3328_PD_VPU] = DOMAIN_RK3328("vpu", 0, BIT(9), BIT(9), false), > }; > > static const struct rockchip_domain_info rk3366_pm_domains[] = { > - [RK3366_PD_PERI] = DOMAIN_RK3368(BIT(10), BIT(10), BIT(6), true), > - [RK3366_PD_VIO] = DOMAIN_RK3368(BIT(14), BIT(14), BIT(8), false), > - [RK3366_PD_VIDEO] = DOMAIN_RK3368(BIT(13), BIT(13), BIT(7), false), > - [RK3366_PD_RKVDEC] = DOMAIN_RK3368(BIT(11), BIT(11), BIT(7), false), > - [RK3366_PD_WIFIBT] = DOMAIN_RK3368(BIT(8), BIT(8), BIT(9), false), > - [RK3366_PD_VPU] = DOMAIN_RK3368(BIT(12), BIT(12), BIT(7), false), > - [RK3366_PD_GPU] = DOMAIN_RK3368(BIT(15), BIT(15), BIT(2), false), > + [RK3366_PD_PERI] = DOMAIN_RK3368("peri", BIT(10), BIT(10), BIT(6), true), > + [RK3366_PD_VIO] = DOMAIN_RK3368("vio", BIT(14), BIT(14), BIT(8), false), > + [RK3366_PD_VIDEO] = DOMAIN_RK3368("video", BIT(13), BIT(13), BIT(7), false), > + [RK3366_PD_RKVDEC] = DOMAIN_RK3368("vdec", BIT(11), BIT(11), BIT(7), false), > + [RK3366_PD_WIFIBT] = DOMAIN_RK3368("wifibt", BIT(8), BIT(8), BIT(9), false), > + [RK3366_PD_VPU] = DOMAIN_RK3368("vpu", BIT(12), BIT(12), BIT(7), false), > + [RK3366_PD_GPU] = DOMAIN_RK3368("gpu", BIT(15), BIT(15), BIT(2), false), > }; > > static const struct rockchip_domain_info rk3368_pm_domains[] = { > - [RK3368_PD_PERI] = DOMAIN_RK3368(BIT(13), BIT(12), BIT(6), true), > - [RK3368_PD_VIO] = DOMAIN_RK3368(BIT(15), BIT(14), BIT(8), false), > - [RK3368_PD_VIDEO] = DOMAIN_RK3368(BIT(14), BIT(13), BIT(7), false), > - [RK3368_PD_GPU_0] = DOMAIN_RK3368(BIT(16), BIT(15), BIT(2), false), > - [RK3368_PD_GPU_1] = DOMAIN_RK3368(BIT(17), BIT(16), BIT(2), false), > + [RK3368_PD_PERI] = DOMAIN_RK3368("peri", BIT(13), BIT(12), BIT(6), true), > + [RK3368_PD_VIO] = DOMAIN_RK3368("vio", BIT(15), BIT(14), BIT(8), false), > + [RK3368_PD_VIDEO] = DOMAIN_RK3368("video", BIT(14), BIT(13), BIT(7), false), > + [RK3368_PD_GPU_0] = DOMAIN_RK3368("gpu_0", BIT(16), BIT(15), BIT(2), false), > + [RK3368_PD_GPU_1] = DOMAIN_RK3368("gpu_1", BIT(17), BIT(16), BIT(2), false), > }; > > static const struct rockchip_domain_info rk3399_pm_domains[] = { > - [RK3399_PD_TCPD0] = DOMAIN_RK3399(BIT(8), BIT(8), 0, false), > - [RK3399_PD_TCPD1] = DOMAIN_RK3399(BIT(9), BIT(9), 0, false), > - [RK3399_PD_CCI] = DOMAIN_RK3399(BIT(10), BIT(10), 0, true), > - [RK3399_PD_CCI0] = DOMAIN_RK3399(0, 0, BIT(15), true), > - [RK3399_PD_CCI1] = DOMAIN_RK3399(0, 0, BIT(16), true), > - [RK3399_PD_PERILP] = DOMAIN_RK3399(BIT(11), BIT(11), BIT(1), true), > - [RK3399_PD_PERIHP] = DOMAIN_RK3399(BIT(12), BIT(12), BIT(2), true), > - [RK3399_PD_CENTER] = DOMAIN_RK3399(BIT(13), BIT(13), BIT(14), true), > - [RK3399_PD_VIO] = DOMAIN_RK3399(BIT(14), BIT(14), BIT(17), false), > - [RK3399_PD_GPU] = DOMAIN_RK3399(BIT(15), BIT(15), BIT(0), false), > - [RK3399_PD_VCODEC] = DOMAIN_RK3399(BIT(16), BIT(16), BIT(3), false), > - [RK3399_PD_VDU] = DOMAIN_RK3399(BIT(17), BIT(17), BIT(4), false), > - [RK3399_PD_RGA] = DOMAIN_RK3399(BIT(18), BIT(18), BIT(5), false), > - [RK3399_PD_IEP] = DOMAIN_RK3399(BIT(19), BIT(19), BIT(6), false), > - [RK3399_PD_VO] = DOMAIN_RK3399(BIT(20), BIT(20), 0, false), > - [RK3399_PD_VOPB] = DOMAIN_RK3399(0, 0, BIT(7), false), > - [RK3399_PD_VOPL] = DOMAIN_RK3399(0, 0, BIT(8), false), > - [RK3399_PD_ISP0] = DOMAIN_RK3399(BIT(22), BIT(22), BIT(9), false), > - [RK3399_PD_ISP1] = DOMAIN_RK3399(BIT(23), BIT(23), BIT(10), false), > - [RK3399_PD_HDCP] = DOMAIN_RK3399(BIT(24), BIT(24), BIT(11), false), > - [RK3399_PD_GMAC] = DOMAIN_RK3399(BIT(25), BIT(25), BIT(23), true), > - [RK3399_PD_EMMC] = DOMAIN_RK3399(BIT(26), BIT(26), BIT(24), true), > - [RK3399_PD_USB3] = DOMAIN_RK3399(BIT(27), BIT(27), BIT(12), true), > - [RK3399_PD_EDP] = DOMAIN_RK3399(BIT(28), BIT(28), BIT(22), false), > - [RK3399_PD_GIC] = DOMAIN_RK3399(BIT(29), BIT(29), BIT(27), true), > - [RK3399_PD_SD] = DOMAIN_RK3399(BIT(30), BIT(30), BIT(28), true), > - [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399(BIT(31), BIT(31), BIT(29), true), > + [RK3399_PD_TCPD0] = DOMAIN_RK3399("tcpd0", BIT(8), BIT(8), 0, false), > + [RK3399_PD_TCPD1] = DOMAIN_RK3399("tcpd1", BIT(9), BIT(9), 0, false), > + [RK3399_PD_CCI] = DOMAIN_RK3399("cci", BIT(10), BIT(10), 0, true), > + [RK3399_PD_CCI0] = DOMAIN_RK3399("cci0", 0, 0, BIT(15), true), > + [RK3399_PD_CCI1] = DOMAIN_RK3399("cci1", 0, 0, BIT(16), true), > + [RK3399_PD_PERILP] = DOMAIN_RK3399("perilp", BIT(11), BIT(11), BIT(1), true), > + [RK3399_PD_PERIHP] = DOMAIN_RK3399("perihp", BIT(12), BIT(12), BIT(2), true), > + [RK3399_PD_CENTER] = DOMAIN_RK3399("center", BIT(13), BIT(13), BIT(14), true), > + [RK3399_PD_VIO] = DOMAIN_RK3399("vio", BIT(14), BIT(14), BIT(17), false), > + [RK3399_PD_GPU] = DOMAIN_RK3399("gpu", BIT(15), BIT(15), BIT(0), false), > + [RK3399_PD_VCODEC] = DOMAIN_RK3399("vcodec", BIT(16), BIT(16), BIT(3), false), > + [RK3399_PD_VDU] = DOMAIN_RK3399("vdu", BIT(17), BIT(17), BIT(4), false), > + [RK3399_PD_RGA] = DOMAIN_RK3399("rga", BIT(18), BIT(18), BIT(5), false), > + [RK3399_PD_IEP] = DOMAIN_RK3399("iep", BIT(19), BIT(19), BIT(6), false), > + [RK3399_PD_VO] = DOMAIN_RK3399("vo", BIT(20), BIT(20), 0, false), > + [RK3399_PD_VOPB] = DOMAIN_RK3399("vopb", 0, 0, BIT(7), false), > + [RK3399_PD_VOPL] = DOMAIN_RK3399("vopl", 0, 0, BIT(8), false), > + [RK3399_PD_ISP0] = DOMAIN_RK3399("isp0", BIT(22), BIT(22), BIT(9), false), > + [RK3399_PD_ISP1] = DOMAIN_RK3399("isp1", BIT(23), BIT(23), BIT(10), false), > + [RK3399_PD_HDCP] = DOMAIN_RK3399("hdcp", BIT(24), BIT(24), BIT(11), false), > + [RK3399_PD_GMAC] = DOMAIN_RK3399("gmac", BIT(25), BIT(25), BIT(23), true), > + [RK3399_PD_EMMC] = DOMAIN_RK3399("emmc", BIT(26), BIT(26), BIT(24), true), > + [RK3399_PD_USB3] = DOMAIN_RK3399("usb3", BIT(27), BIT(27), BIT(12), true), > + [RK3399_PD_EDP] = DOMAIN_RK3399("edp", BIT(28), BIT(28), BIT(22), false), > + [RK3399_PD_GIC] = DOMAIN_RK3399("gic", BIT(29), BIT(29), BIT(27), true), > + [RK3399_PD_SD] = DOMAIN_RK3399("sd", BIT(30), BIT(30), BIT(28), true), > + [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true), > }; > > static const struct rockchip_pmu_info px30_pmu = { > _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [RESEND PATCH v5 07/11] soc: rockchip: pm-domains: Add a meaningful power domain name @ 2021-03-26 9:52 ` Heiko Stübner 0 siblings, 0 replies; 75+ messages in thread From: Heiko Stübner @ 2021-03-26 9:52 UTC (permalink / raw) To: robh+dt, Elaine Zhang Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang, enric.balletbo Hi Elaine, [also adding that answer to the resend :-) ] Am Freitag, 26. März 2021, 10:17:39 CET schrieb Elaine Zhang: > Add the power domains names to the power domain info struct so we > have meaningful name for every power domain. > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> I like that approach very much, there is one tiny comment below. > --- > drivers/soc/rockchip/pm_domains.c | 217 +++++++++++++++--------------- > 1 file changed, 112 insertions(+), 105 deletions(-) > > diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c > index 54eb6cfc5d5b..d661d967079f 100644 > --- a/drivers/soc/rockchip/pm_domains.c > +++ b/drivers/soc/rockchip/pm_domains.c > @@ -29,6 +29,7 @@ > #include <dt-bindings/power/rk3399-power.h> > > struct rockchip_domain_info { > + const char *name; > int pwr_mask; > int status_mask; > int req_mask; > @@ -85,8 +86,9 @@ struct rockchip_pmu { > > #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd) > > -#define DOMAIN(pwr, status, req, idle, ack, wakeup) \ > +#define DOMAIN(_name, pwr, status, req, idle, ack, wakeup) \ > { \ > + .name = _name, \ > .pwr_mask = (pwr), \ > .status_mask = (status), \ > .req_mask = (req), \ > @@ -95,8 +97,9 @@ struct rockchip_pmu { > .active_wakeup = (wakeup), \ > } > > -#define DOMAIN_M(pwr, status, req, idle, ack, wakeup) \ > +#define DOMAIN_M(_name, pwr, status, req, idle, ack, wakeup) \ > { \ > + .name = _name, \ > .pwr_w_mask = (pwr) << 16, \ > .pwr_mask = (pwr), \ > .status_mask = (status), \ > @@ -107,8 +110,9 @@ struct rockchip_pmu { > .active_wakeup = wakeup, \ > } > > -#define DOMAIN_RK3036(req, ack, idle, wakeup) \ > +#define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \ > { \ > + .name = _name, \ > .req_mask = (req), \ > .req_w_mask = (req) << 16, \ > .ack_mask = (ack), \ > @@ -119,17 +123,17 @@ struct rockchip_pmu { > #define DOMAIN_PX30(pwr, status, req, wakeup) \ > DOMAIN_M(pwr, status, req, (req) << 16, req, wakeup) > > -#define DOMAIN_RK3288(pwr, status, req, wakeup) \ > - DOMAIN(pwr, status, req, req, (req) << 16, wakeup) > +#define DOMAIN_RK3288(name, pwr, status, req, wakeup) \ > + DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup) > > -#define DOMAIN_RK3328(pwr, status, req, wakeup) \ > - DOMAIN_M(pwr, pwr, req, (req) << 10, req, wakeup) > +#define DOMAIN_RK3328(name, pwr, status, req, wakeup) \ > + DOMAIN_M(name, pwr, pwr, req, (req) << 10, req, wakeup) > > -#define DOMAIN_RK3368(pwr, status, req, wakeup) \ > - DOMAIN(pwr, status, req, (req) << 16, req, wakeup) > +#define DOMAIN_RK3368(name, pwr, status, req, wakeup) \ > + DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup) > > -#define DOMAIN_RK3399(pwr, status, req, wakeup) \ > - DOMAIN(pwr, status, req, req, req, wakeup) > +#define DOMAIN_RK3399(name, pwr, status, req, wakeup) \ > + DOMAIN(name, pwr, status, req, req, req, wakeup) > > static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd) > { > @@ -490,7 +494,10 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, > goto err_unprepare_clocks; > } > > - pd->genpd.name = node->name; > + if (!pd->info->name) > + pd->genpd.name = node->name; I guess we should make that "node->full_name" perhaps? And I guess it might be nicer to swap the cases if (pd->info->name) pd->genpd.name = pd->info->name else pd->genpd.name = node->full_name; for easier readability Heiko > + else > + pd->genpd.name = pd->info->name; > pd->genpd.power_off = rockchip_pd_power_off; > pd->genpd.power_on = rockchip_pd_power_on; > pd->genpd.attach_dev = rockchip_pd_attach_dev; > @@ -716,129 +723,129 @@ static int rockchip_pm_domain_probe(struct platform_device *pdev) > } > > static const struct rockchip_domain_info px30_pm_domains[] = { > - [PX30_PD_USB] = DOMAIN_PX30(BIT(5), BIT(5), BIT(10), false), > - [PX30_PD_SDCARD] = DOMAIN_PX30(BIT(8), BIT(8), BIT(9), false), > - [PX30_PD_GMAC] = DOMAIN_PX30(BIT(10), BIT(10), BIT(6), false), > - [PX30_PD_MMC_NAND] = DOMAIN_PX30(BIT(11), BIT(11), BIT(5), false), > - [PX30_PD_VPU] = DOMAIN_PX30(BIT(12), BIT(12), BIT(14), false), > - [PX30_PD_VO] = DOMAIN_PX30(BIT(13), BIT(13), BIT(7), false), > - [PX30_PD_VI] = DOMAIN_PX30(BIT(14), BIT(14), BIT(8), false), > - [PX30_PD_GPU] = DOMAIN_PX30(BIT(15), BIT(15), BIT(2), false), > + [PX30_PD_USB] = DOMAIN_PX30("usb", BIT(5), BIT(5), BIT(10), false), > + [PX30_PD_SDCARD] = DOMAIN_PX30("sdcard", BIT(8), BIT(8), BIT(9), false), > + [PX30_PD_GMAC] = DOMAIN_PX30("gmac", BIT(10), BIT(10), BIT(6), false), > + [PX30_PD_MMC_NAND] = DOMAIN_PX30("mmc_nand", BIT(11), BIT(11), BIT(5), false), > + [PX30_PD_VPU] = DOMAIN_PX30("vpu", BIT(12), BIT(12), BIT(14), false), > + [PX30_PD_VO] = DOMAIN_PX30("vo", BIT(13), BIT(13), BIT(7), false), > + [PX30_PD_VI] = DOMAIN_PX30("vi", BIT(14), BIT(14), BIT(8), false), > + [PX30_PD_GPU] = DOMAIN_PX30("gpu", BIT(15), BIT(15), BIT(2), false), > }; > > static const struct rockchip_domain_info rk3036_pm_domains[] = { > - [RK3036_PD_MSCH] = DOMAIN_RK3036(BIT(14), BIT(23), BIT(30), true), > - [RK3036_PD_CORE] = DOMAIN_RK3036(BIT(13), BIT(17), BIT(24), false), > - [RK3036_PD_PERI] = DOMAIN_RK3036(BIT(12), BIT(18), BIT(25), false), > - [RK3036_PD_VIO] = DOMAIN_RK3036(BIT(11), BIT(19), BIT(26), false), > - [RK3036_PD_VPU] = DOMAIN_RK3036(BIT(10), BIT(20), BIT(27), false), > - [RK3036_PD_GPU] = DOMAIN_RK3036(BIT(9), BIT(21), BIT(28), false), > - [RK3036_PD_SYS] = DOMAIN_RK3036(BIT(8), BIT(22), BIT(29), false), > + [RK3036_PD_MSCH] = DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true), > + [RK3036_PD_CORE] = DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false), > + [RK3036_PD_PERI] = DOMAIN_RK3036("peri", BIT(12), BIT(18), BIT(25), false), > + [RK3036_PD_VIO] = DOMAIN_RK3036("vio", BIT(11), BIT(19), BIT(26), false), > + [RK3036_PD_VPU] = DOMAIN_RK3036("vpu", BIT(10), BIT(20), BIT(27), false), > + [RK3036_PD_GPU] = DOMAIN_RK3036("gpu", BIT(9), BIT(21), BIT(28), false), > + [RK3036_PD_SYS] = DOMAIN_RK3036("sys", BIT(8), BIT(22), BIT(29), false), > }; > > static const struct rockchip_domain_info rk3066_pm_domains[] = { > - [RK3066_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > - [RK3066_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > - [RK3066_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > - [RK3066_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > - [RK3066_PD_CPU] = DOMAIN(0, BIT(5), BIT(1), BIT(26), BIT(31), false), > + [RK3066_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > + [RK3066_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > + [RK3066_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > + [RK3066_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > + [RK3066_PD_CPU] = DOMAIN("cpu", 0, BIT(5), BIT(1), BIT(26), BIT(31), false), > }; > > static const struct rockchip_domain_info rk3128_pm_domains[] = { > - [RK3128_PD_CORE] = DOMAIN_RK3288(BIT(0), BIT(0), BIT(4), false), > - [RK3128_PD_MSCH] = DOMAIN_RK3288(0, 0, BIT(6), true), > - [RK3128_PD_VIO] = DOMAIN_RK3288(BIT(3), BIT(3), BIT(2), false), > - [RK3128_PD_VIDEO] = DOMAIN_RK3288(BIT(2), BIT(2), BIT(1), false), > - [RK3128_PD_GPU] = DOMAIN_RK3288(BIT(1), BIT(1), BIT(3), false), > + [RK3128_PD_CORE] = DOMAIN_RK3288("core", BIT(0), BIT(0), BIT(4), false), > + [RK3128_PD_MSCH] = DOMAIN_RK3288("msch", 0, 0, BIT(6), true), > + [RK3128_PD_VIO] = DOMAIN_RK3288("vio", BIT(3), BIT(3), BIT(2), false), > + [RK3128_PD_VIDEO] = DOMAIN_RK3288("video", BIT(2), BIT(2), BIT(1), false), > + [RK3128_PD_GPU] = DOMAIN_RK3288("gpu", BIT(1), BIT(1), BIT(3), false), > }; > > static const struct rockchip_domain_info rk3188_pm_domains[] = { > - [RK3188_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > - [RK3188_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > - [RK3188_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > - [RK3188_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > - [RK3188_PD_CPU] = DOMAIN(BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false), > + [RK3188_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > + [RK3188_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > + [RK3188_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > + [RK3188_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > + [RK3188_PD_CPU] = DOMAIN("cpu", BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false), > }; > > static const struct rockchip_domain_info rk3228_pm_domains[] = { > - [RK3228_PD_CORE] = DOMAIN_RK3036(BIT(0), BIT(0), BIT(16), true), > - [RK3228_PD_MSCH] = DOMAIN_RK3036(BIT(1), BIT(1), BIT(17), true), > - [RK3228_PD_BUS] = DOMAIN_RK3036(BIT(2), BIT(2), BIT(18), true), > - [RK3228_PD_SYS] = DOMAIN_RK3036(BIT(3), BIT(3), BIT(19), true), > - [RK3228_PD_VIO] = DOMAIN_RK3036(BIT(4), BIT(4), BIT(20), false), > - [RK3228_PD_VOP] = DOMAIN_RK3036(BIT(5), BIT(5), BIT(21), false), > - [RK3228_PD_VPU] = DOMAIN_RK3036(BIT(6), BIT(6), BIT(22), false), > - [RK3228_PD_RKVDEC] = DOMAIN_RK3036(BIT(7), BIT(7), BIT(23), false), > - [RK3228_PD_GPU] = DOMAIN_RK3036(BIT(8), BIT(8), BIT(24), false), > - [RK3228_PD_PERI] = DOMAIN_RK3036(BIT(9), BIT(9), BIT(25), true), > - [RK3228_PD_GMAC] = DOMAIN_RK3036(BIT(10), BIT(10), BIT(26), false), > + [RK3228_PD_CORE] = DOMAIN_RK3036("core", BIT(0), BIT(0), BIT(16), true), > + [RK3228_PD_MSCH] = DOMAIN_RK3036("msch", BIT(1), BIT(1), BIT(17), true), > + [RK3228_PD_BUS] = DOMAIN_RK3036("bus", BIT(2), BIT(2), BIT(18), true), > + [RK3228_PD_SYS] = DOMAIN_RK3036("sys", BIT(3), BIT(3), BIT(19), true), > + [RK3228_PD_VIO] = DOMAIN_RK3036("vio", BIT(4), BIT(4), BIT(20), false), > + [RK3228_PD_VOP] = DOMAIN_RK3036("vop", BIT(5), BIT(5), BIT(21), false), > + [RK3228_PD_VPU] = DOMAIN_RK3036("vpu", BIT(6), BIT(6), BIT(22), false), > + [RK3228_PD_RKVDEC] = DOMAIN_RK3036("vdec", BIT(7), BIT(7), BIT(23), false), > + [RK3228_PD_GPU] = DOMAIN_RK3036("gpu", BIT(8), BIT(8), BIT(24), false), > + [RK3228_PD_PERI] = DOMAIN_RK3036("peri", BIT(9), BIT(9), BIT(25), true), > + [RK3228_PD_GMAC] = DOMAIN_RK3036("gmac", BIT(10), BIT(10), BIT(26), false), > }; > > static const struct rockchip_domain_info rk3288_pm_domains[] = { > - [RK3288_PD_VIO] = DOMAIN_RK3288(BIT(7), BIT(7), BIT(4), false), > - [RK3288_PD_HEVC] = DOMAIN_RK3288(BIT(14), BIT(10), BIT(9), false), > - [RK3288_PD_VIDEO] = DOMAIN_RK3288(BIT(8), BIT(8), BIT(3), false), > - [RK3288_PD_GPU] = DOMAIN_RK3288(BIT(9), BIT(9), BIT(2), false), > + [RK3288_PD_VIO] = DOMAIN_RK3288("vio", BIT(7), BIT(7), BIT(4), false), > + [RK3288_PD_HEVC] = DOMAIN_RK3288("hevc", BIT(14), BIT(10), BIT(9), false), > + [RK3288_PD_VIDEO] = DOMAIN_RK3288("video", BIT(8), BIT(8), BIT(3), false), > + [RK3288_PD_GPU] = DOMAIN_RK3288("gpu", BIT(9), BIT(9), BIT(2), false), > }; > > static const struct rockchip_domain_info rk3328_pm_domains[] = { > - [RK3328_PD_CORE] = DOMAIN_RK3328(0, BIT(0), BIT(0), false), > - [RK3328_PD_GPU] = DOMAIN_RK3328(0, BIT(1), BIT(1), false), > - [RK3328_PD_BUS] = DOMAIN_RK3328(0, BIT(2), BIT(2), true), > - [RK3328_PD_MSCH] = DOMAIN_RK3328(0, BIT(3), BIT(3), true), > - [RK3328_PD_PERI] = DOMAIN_RK3328(0, BIT(4), BIT(4), true), > - [RK3328_PD_VIDEO] = DOMAIN_RK3328(0, BIT(5), BIT(5), false), > - [RK3328_PD_HEVC] = DOMAIN_RK3328(0, BIT(6), BIT(6), false), > - [RK3328_PD_VIO] = DOMAIN_RK3328(0, BIT(8), BIT(8), false), > - [RK3328_PD_VPU] = DOMAIN_RK3328(0, BIT(9), BIT(9), false), > + [RK3328_PD_CORE] = DOMAIN_RK3328("core", 0, BIT(0), BIT(0), false), > + [RK3328_PD_GPU] = DOMAIN_RK3328("gpu", 0, BIT(1), BIT(1), false), > + [RK3328_PD_BUS] = DOMAIN_RK3328("bus", 0, BIT(2), BIT(2), true), > + [RK3328_PD_MSCH] = DOMAIN_RK3328("msch", 0, BIT(3), BIT(3), true), > + [RK3328_PD_PERI] = DOMAIN_RK3328("peri", 0, BIT(4), BIT(4), true), > + [RK3328_PD_VIDEO] = DOMAIN_RK3328("video", 0, BIT(5), BIT(5), false), > + [RK3328_PD_HEVC] = DOMAIN_RK3328("hevc", 0, BIT(6), BIT(6), false), > + [RK3328_PD_VIO] = DOMAIN_RK3328("vio", 0, BIT(8), BIT(8), false), > + [RK3328_PD_VPU] = DOMAIN_RK3328("vpu", 0, BIT(9), BIT(9), false), > }; > > static const struct rockchip_domain_info rk3366_pm_domains[] = { > - [RK3366_PD_PERI] = DOMAIN_RK3368(BIT(10), BIT(10), BIT(6), true), > - [RK3366_PD_VIO] = DOMAIN_RK3368(BIT(14), BIT(14), BIT(8), false), > - [RK3366_PD_VIDEO] = DOMAIN_RK3368(BIT(13), BIT(13), BIT(7), false), > - [RK3366_PD_RKVDEC] = DOMAIN_RK3368(BIT(11), BIT(11), BIT(7), false), > - [RK3366_PD_WIFIBT] = DOMAIN_RK3368(BIT(8), BIT(8), BIT(9), false), > - [RK3366_PD_VPU] = DOMAIN_RK3368(BIT(12), BIT(12), BIT(7), false), > - [RK3366_PD_GPU] = DOMAIN_RK3368(BIT(15), BIT(15), BIT(2), false), > + [RK3366_PD_PERI] = DOMAIN_RK3368("peri", BIT(10), BIT(10), BIT(6), true), > + [RK3366_PD_VIO] = DOMAIN_RK3368("vio", BIT(14), BIT(14), BIT(8), false), > + [RK3366_PD_VIDEO] = DOMAIN_RK3368("video", BIT(13), BIT(13), BIT(7), false), > + [RK3366_PD_RKVDEC] = DOMAIN_RK3368("vdec", BIT(11), BIT(11), BIT(7), false), > + [RK3366_PD_WIFIBT] = DOMAIN_RK3368("wifibt", BIT(8), BIT(8), BIT(9), false), > + [RK3366_PD_VPU] = DOMAIN_RK3368("vpu", BIT(12), BIT(12), BIT(7), false), > + [RK3366_PD_GPU] = DOMAIN_RK3368("gpu", BIT(15), BIT(15), BIT(2), false), > }; > > static const struct rockchip_domain_info rk3368_pm_domains[] = { > - [RK3368_PD_PERI] = DOMAIN_RK3368(BIT(13), BIT(12), BIT(6), true), > - [RK3368_PD_VIO] = DOMAIN_RK3368(BIT(15), BIT(14), BIT(8), false), > - [RK3368_PD_VIDEO] = DOMAIN_RK3368(BIT(14), BIT(13), BIT(7), false), > - [RK3368_PD_GPU_0] = DOMAIN_RK3368(BIT(16), BIT(15), BIT(2), false), > - [RK3368_PD_GPU_1] = DOMAIN_RK3368(BIT(17), BIT(16), BIT(2), false), > + [RK3368_PD_PERI] = DOMAIN_RK3368("peri", BIT(13), BIT(12), BIT(6), true), > + [RK3368_PD_VIO] = DOMAIN_RK3368("vio", BIT(15), BIT(14), BIT(8), false), > + [RK3368_PD_VIDEO] = DOMAIN_RK3368("video", BIT(14), BIT(13), BIT(7), false), > + [RK3368_PD_GPU_0] = DOMAIN_RK3368("gpu_0", BIT(16), BIT(15), BIT(2), false), > + [RK3368_PD_GPU_1] = DOMAIN_RK3368("gpu_1", BIT(17), BIT(16), BIT(2), false), > }; > > static const struct rockchip_domain_info rk3399_pm_domains[] = { > - [RK3399_PD_TCPD0] = DOMAIN_RK3399(BIT(8), BIT(8), 0, false), > - [RK3399_PD_TCPD1] = DOMAIN_RK3399(BIT(9), BIT(9), 0, false), > - [RK3399_PD_CCI] = DOMAIN_RK3399(BIT(10), BIT(10), 0, true), > - [RK3399_PD_CCI0] = DOMAIN_RK3399(0, 0, BIT(15), true), > - [RK3399_PD_CCI1] = DOMAIN_RK3399(0, 0, BIT(16), true), > - [RK3399_PD_PERILP] = DOMAIN_RK3399(BIT(11), BIT(11), BIT(1), true), > - [RK3399_PD_PERIHP] = DOMAIN_RK3399(BIT(12), BIT(12), BIT(2), true), > - [RK3399_PD_CENTER] = DOMAIN_RK3399(BIT(13), BIT(13), BIT(14), true), > - [RK3399_PD_VIO] = DOMAIN_RK3399(BIT(14), BIT(14), BIT(17), false), > - [RK3399_PD_GPU] = DOMAIN_RK3399(BIT(15), BIT(15), BIT(0), false), > - [RK3399_PD_VCODEC] = DOMAIN_RK3399(BIT(16), BIT(16), BIT(3), false), > - [RK3399_PD_VDU] = DOMAIN_RK3399(BIT(17), BIT(17), BIT(4), false), > - [RK3399_PD_RGA] = DOMAIN_RK3399(BIT(18), BIT(18), BIT(5), false), > - [RK3399_PD_IEP] = DOMAIN_RK3399(BIT(19), BIT(19), BIT(6), false), > - [RK3399_PD_VO] = DOMAIN_RK3399(BIT(20), BIT(20), 0, false), > - [RK3399_PD_VOPB] = DOMAIN_RK3399(0, 0, BIT(7), false), > - [RK3399_PD_VOPL] = DOMAIN_RK3399(0, 0, BIT(8), false), > - [RK3399_PD_ISP0] = DOMAIN_RK3399(BIT(22), BIT(22), BIT(9), false), > - [RK3399_PD_ISP1] = DOMAIN_RK3399(BIT(23), BIT(23), BIT(10), false), > - [RK3399_PD_HDCP] = DOMAIN_RK3399(BIT(24), BIT(24), BIT(11), false), > - [RK3399_PD_GMAC] = DOMAIN_RK3399(BIT(25), BIT(25), BIT(23), true), > - [RK3399_PD_EMMC] = DOMAIN_RK3399(BIT(26), BIT(26), BIT(24), true), > - [RK3399_PD_USB3] = DOMAIN_RK3399(BIT(27), BIT(27), BIT(12), true), > - [RK3399_PD_EDP] = DOMAIN_RK3399(BIT(28), BIT(28), BIT(22), false), > - [RK3399_PD_GIC] = DOMAIN_RK3399(BIT(29), BIT(29), BIT(27), true), > - [RK3399_PD_SD] = DOMAIN_RK3399(BIT(30), BIT(30), BIT(28), true), > - [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399(BIT(31), BIT(31), BIT(29), true), > + [RK3399_PD_TCPD0] = DOMAIN_RK3399("tcpd0", BIT(8), BIT(8), 0, false), > + [RK3399_PD_TCPD1] = DOMAIN_RK3399("tcpd1", BIT(9), BIT(9), 0, false), > + [RK3399_PD_CCI] = DOMAIN_RK3399("cci", BIT(10), BIT(10), 0, true), > + [RK3399_PD_CCI0] = DOMAIN_RK3399("cci0", 0, 0, BIT(15), true), > + [RK3399_PD_CCI1] = DOMAIN_RK3399("cci1", 0, 0, BIT(16), true), > + [RK3399_PD_PERILP] = DOMAIN_RK3399("perilp", BIT(11), BIT(11), BIT(1), true), > + [RK3399_PD_PERIHP] = DOMAIN_RK3399("perihp", BIT(12), BIT(12), BIT(2), true), > + [RK3399_PD_CENTER] = DOMAIN_RK3399("center", BIT(13), BIT(13), BIT(14), true), > + [RK3399_PD_VIO] = DOMAIN_RK3399("vio", BIT(14), BIT(14), BIT(17), false), > + [RK3399_PD_GPU] = DOMAIN_RK3399("gpu", BIT(15), BIT(15), BIT(0), false), > + [RK3399_PD_VCODEC] = DOMAIN_RK3399("vcodec", BIT(16), BIT(16), BIT(3), false), > + [RK3399_PD_VDU] = DOMAIN_RK3399("vdu", BIT(17), BIT(17), BIT(4), false), > + [RK3399_PD_RGA] = DOMAIN_RK3399("rga", BIT(18), BIT(18), BIT(5), false), > + [RK3399_PD_IEP] = DOMAIN_RK3399("iep", BIT(19), BIT(19), BIT(6), false), > + [RK3399_PD_VO] = DOMAIN_RK3399("vo", BIT(20), BIT(20), 0, false), > + [RK3399_PD_VOPB] = DOMAIN_RK3399("vopb", 0, 0, BIT(7), false), > + [RK3399_PD_VOPL] = DOMAIN_RK3399("vopl", 0, 0, BIT(8), false), > + [RK3399_PD_ISP0] = DOMAIN_RK3399("isp0", BIT(22), BIT(22), BIT(9), false), > + [RK3399_PD_ISP1] = DOMAIN_RK3399("isp1", BIT(23), BIT(23), BIT(10), false), > + [RK3399_PD_HDCP] = DOMAIN_RK3399("hdcp", BIT(24), BIT(24), BIT(11), false), > + [RK3399_PD_GMAC] = DOMAIN_RK3399("gmac", BIT(25), BIT(25), BIT(23), true), > + [RK3399_PD_EMMC] = DOMAIN_RK3399("emmc", BIT(26), BIT(26), BIT(24), true), > + [RK3399_PD_USB3] = DOMAIN_RK3399("usb3", BIT(27), BIT(27), BIT(12), true), > + [RK3399_PD_EDP] = DOMAIN_RK3399("edp", BIT(28), BIT(28), BIT(22), false), > + [RK3399_PD_GIC] = DOMAIN_RK3399("gic", BIT(29), BIT(29), BIT(27), true), > + [RK3399_PD_SD] = DOMAIN_RK3399("sd", BIT(30), BIT(30), BIT(28), true), > + [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true), > }; > > static const struct rockchip_pmu_info px30_pmu = { > ^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [RESEND PATCH v5 07/11] soc: rockchip: pm-domains: Add a meaningful power domain name @ 2021-03-26 9:52 ` Heiko Stübner 0 siblings, 0 replies; 75+ messages in thread From: Heiko Stübner @ 2021-03-26 9:52 UTC (permalink / raw) To: robh+dt, Elaine Zhang Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang, enric.balletbo Hi Elaine, [also adding that answer to the resend :-) ] Am Freitag, 26. März 2021, 10:17:39 CET schrieb Elaine Zhang: > Add the power domains names to the power domain info struct so we > have meaningful name for every power domain. > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> I like that approach very much, there is one tiny comment below. > --- > drivers/soc/rockchip/pm_domains.c | 217 +++++++++++++++--------------- > 1 file changed, 112 insertions(+), 105 deletions(-) > > diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c > index 54eb6cfc5d5b..d661d967079f 100644 > --- a/drivers/soc/rockchip/pm_domains.c > +++ b/drivers/soc/rockchip/pm_domains.c > @@ -29,6 +29,7 @@ > #include <dt-bindings/power/rk3399-power.h> > > struct rockchip_domain_info { > + const char *name; > int pwr_mask; > int status_mask; > int req_mask; > @@ -85,8 +86,9 @@ struct rockchip_pmu { > > #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd) > > -#define DOMAIN(pwr, status, req, idle, ack, wakeup) \ > +#define DOMAIN(_name, pwr, status, req, idle, ack, wakeup) \ > { \ > + .name = _name, \ > .pwr_mask = (pwr), \ > .status_mask = (status), \ > .req_mask = (req), \ > @@ -95,8 +97,9 @@ struct rockchip_pmu { > .active_wakeup = (wakeup), \ > } > > -#define DOMAIN_M(pwr, status, req, idle, ack, wakeup) \ > +#define DOMAIN_M(_name, pwr, status, req, idle, ack, wakeup) \ > { \ > + .name = _name, \ > .pwr_w_mask = (pwr) << 16, \ > .pwr_mask = (pwr), \ > .status_mask = (status), \ > @@ -107,8 +110,9 @@ struct rockchip_pmu { > .active_wakeup = wakeup, \ > } > > -#define DOMAIN_RK3036(req, ack, idle, wakeup) \ > +#define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \ > { \ > + .name = _name, \ > .req_mask = (req), \ > .req_w_mask = (req) << 16, \ > .ack_mask = (ack), \ > @@ -119,17 +123,17 @@ struct rockchip_pmu { > #define DOMAIN_PX30(pwr, status, req, wakeup) \ > DOMAIN_M(pwr, status, req, (req) << 16, req, wakeup) > > -#define DOMAIN_RK3288(pwr, status, req, wakeup) \ > - DOMAIN(pwr, status, req, req, (req) << 16, wakeup) > +#define DOMAIN_RK3288(name, pwr, status, req, wakeup) \ > + DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup) > > -#define DOMAIN_RK3328(pwr, status, req, wakeup) \ > - DOMAIN_M(pwr, pwr, req, (req) << 10, req, wakeup) > +#define DOMAIN_RK3328(name, pwr, status, req, wakeup) \ > + DOMAIN_M(name, pwr, pwr, req, (req) << 10, req, wakeup) > > -#define DOMAIN_RK3368(pwr, status, req, wakeup) \ > - DOMAIN(pwr, status, req, (req) << 16, req, wakeup) > +#define DOMAIN_RK3368(name, pwr, status, req, wakeup) \ > + DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup) > > -#define DOMAIN_RK3399(pwr, status, req, wakeup) \ > - DOMAIN(pwr, status, req, req, req, wakeup) > +#define DOMAIN_RK3399(name, pwr, status, req, wakeup) \ > + DOMAIN(name, pwr, status, req, req, req, wakeup) > > static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd) > { > @@ -490,7 +494,10 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, > goto err_unprepare_clocks; > } > > - pd->genpd.name = node->name; > + if (!pd->info->name) > + pd->genpd.name = node->name; I guess we should make that "node->full_name" perhaps? And I guess it might be nicer to swap the cases if (pd->info->name) pd->genpd.name = pd->info->name else pd->genpd.name = node->full_name; for easier readability Heiko > + else > + pd->genpd.name = pd->info->name; > pd->genpd.power_off = rockchip_pd_power_off; > pd->genpd.power_on = rockchip_pd_power_on; > pd->genpd.attach_dev = rockchip_pd_attach_dev; > @@ -716,129 +723,129 @@ static int rockchip_pm_domain_probe(struct platform_device *pdev) > } > > static const struct rockchip_domain_info px30_pm_domains[] = { > - [PX30_PD_USB] = DOMAIN_PX30(BIT(5), BIT(5), BIT(10), false), > - [PX30_PD_SDCARD] = DOMAIN_PX30(BIT(8), BIT(8), BIT(9), false), > - [PX30_PD_GMAC] = DOMAIN_PX30(BIT(10), BIT(10), BIT(6), false), > - [PX30_PD_MMC_NAND] = DOMAIN_PX30(BIT(11), BIT(11), BIT(5), false), > - [PX30_PD_VPU] = DOMAIN_PX30(BIT(12), BIT(12), BIT(14), false), > - [PX30_PD_VO] = DOMAIN_PX30(BIT(13), BIT(13), BIT(7), false), > - [PX30_PD_VI] = DOMAIN_PX30(BIT(14), BIT(14), BIT(8), false), > - [PX30_PD_GPU] = DOMAIN_PX30(BIT(15), BIT(15), BIT(2), false), > + [PX30_PD_USB] = DOMAIN_PX30("usb", BIT(5), BIT(5), BIT(10), false), > + [PX30_PD_SDCARD] = DOMAIN_PX30("sdcard", BIT(8), BIT(8), BIT(9), false), > + [PX30_PD_GMAC] = DOMAIN_PX30("gmac", BIT(10), BIT(10), BIT(6), false), > + [PX30_PD_MMC_NAND] = DOMAIN_PX30("mmc_nand", BIT(11), BIT(11), BIT(5), false), > + [PX30_PD_VPU] = DOMAIN_PX30("vpu", BIT(12), BIT(12), BIT(14), false), > + [PX30_PD_VO] = DOMAIN_PX30("vo", BIT(13), BIT(13), BIT(7), false), > + [PX30_PD_VI] = DOMAIN_PX30("vi", BIT(14), BIT(14), BIT(8), false), > + [PX30_PD_GPU] = DOMAIN_PX30("gpu", BIT(15), BIT(15), BIT(2), false), > }; > > static const struct rockchip_domain_info rk3036_pm_domains[] = { > - [RK3036_PD_MSCH] = DOMAIN_RK3036(BIT(14), BIT(23), BIT(30), true), > - [RK3036_PD_CORE] = DOMAIN_RK3036(BIT(13), BIT(17), BIT(24), false), > - [RK3036_PD_PERI] = DOMAIN_RK3036(BIT(12), BIT(18), BIT(25), false), > - [RK3036_PD_VIO] = DOMAIN_RK3036(BIT(11), BIT(19), BIT(26), false), > - [RK3036_PD_VPU] = DOMAIN_RK3036(BIT(10), BIT(20), BIT(27), false), > - [RK3036_PD_GPU] = DOMAIN_RK3036(BIT(9), BIT(21), BIT(28), false), > - [RK3036_PD_SYS] = DOMAIN_RK3036(BIT(8), BIT(22), BIT(29), false), > + [RK3036_PD_MSCH] = DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true), > + [RK3036_PD_CORE] = DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false), > + [RK3036_PD_PERI] = DOMAIN_RK3036("peri", BIT(12), BIT(18), BIT(25), false), > + [RK3036_PD_VIO] = DOMAIN_RK3036("vio", BIT(11), BIT(19), BIT(26), false), > + [RK3036_PD_VPU] = DOMAIN_RK3036("vpu", BIT(10), BIT(20), BIT(27), false), > + [RK3036_PD_GPU] = DOMAIN_RK3036("gpu", BIT(9), BIT(21), BIT(28), false), > + [RK3036_PD_SYS] = DOMAIN_RK3036("sys", BIT(8), BIT(22), BIT(29), false), > }; > > static const struct rockchip_domain_info rk3066_pm_domains[] = { > - [RK3066_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > - [RK3066_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > - [RK3066_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > - [RK3066_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > - [RK3066_PD_CPU] = DOMAIN(0, BIT(5), BIT(1), BIT(26), BIT(31), false), > + [RK3066_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > + [RK3066_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > + [RK3066_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > + [RK3066_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > + [RK3066_PD_CPU] = DOMAIN("cpu", 0, BIT(5), BIT(1), BIT(26), BIT(31), false), > }; > > static const struct rockchip_domain_info rk3128_pm_domains[] = { > - [RK3128_PD_CORE] = DOMAIN_RK3288(BIT(0), BIT(0), BIT(4), false), > - [RK3128_PD_MSCH] = DOMAIN_RK3288(0, 0, BIT(6), true), > - [RK3128_PD_VIO] = DOMAIN_RK3288(BIT(3), BIT(3), BIT(2), false), > - [RK3128_PD_VIDEO] = DOMAIN_RK3288(BIT(2), BIT(2), BIT(1), false), > - [RK3128_PD_GPU] = DOMAIN_RK3288(BIT(1), BIT(1), BIT(3), false), > + [RK3128_PD_CORE] = DOMAIN_RK3288("core", BIT(0), BIT(0), BIT(4), false), > + [RK3128_PD_MSCH] = DOMAIN_RK3288("msch", 0, 0, BIT(6), true), > + [RK3128_PD_VIO] = DOMAIN_RK3288("vio", BIT(3), BIT(3), BIT(2), false), > + [RK3128_PD_VIDEO] = DOMAIN_RK3288("video", BIT(2), BIT(2), BIT(1), false), > + [RK3128_PD_GPU] = DOMAIN_RK3288("gpu", BIT(1), BIT(1), BIT(3), false), > }; > > static const struct rockchip_domain_info rk3188_pm_domains[] = { > - [RK3188_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > - [RK3188_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > - [RK3188_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > - [RK3188_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > - [RK3188_PD_CPU] = DOMAIN(BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false), > + [RK3188_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > + [RK3188_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > + [RK3188_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > + [RK3188_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > + [RK3188_PD_CPU] = DOMAIN("cpu", BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false), > }; > > static const struct rockchip_domain_info rk3228_pm_domains[] = { > - [RK3228_PD_CORE] = DOMAIN_RK3036(BIT(0), BIT(0), BIT(16), true), > - [RK3228_PD_MSCH] = DOMAIN_RK3036(BIT(1), BIT(1), BIT(17), true), > - [RK3228_PD_BUS] = DOMAIN_RK3036(BIT(2), BIT(2), BIT(18), true), > - [RK3228_PD_SYS] = DOMAIN_RK3036(BIT(3), BIT(3), BIT(19), true), > - [RK3228_PD_VIO] = DOMAIN_RK3036(BIT(4), BIT(4), BIT(20), false), > - [RK3228_PD_VOP] = DOMAIN_RK3036(BIT(5), BIT(5), BIT(21), false), > - [RK3228_PD_VPU] = DOMAIN_RK3036(BIT(6), BIT(6), BIT(22), false), > - [RK3228_PD_RKVDEC] = DOMAIN_RK3036(BIT(7), BIT(7), BIT(23), false), > - [RK3228_PD_GPU] = DOMAIN_RK3036(BIT(8), BIT(8), BIT(24), false), > - [RK3228_PD_PERI] = DOMAIN_RK3036(BIT(9), BIT(9), BIT(25), true), > - [RK3228_PD_GMAC] = DOMAIN_RK3036(BIT(10), BIT(10), BIT(26), false), > + [RK3228_PD_CORE] = DOMAIN_RK3036("core", BIT(0), BIT(0), BIT(16), true), > + [RK3228_PD_MSCH] = DOMAIN_RK3036("msch", BIT(1), BIT(1), BIT(17), true), > + [RK3228_PD_BUS] = DOMAIN_RK3036("bus", BIT(2), BIT(2), BIT(18), true), > + [RK3228_PD_SYS] = DOMAIN_RK3036("sys", BIT(3), BIT(3), BIT(19), true), > + [RK3228_PD_VIO] = DOMAIN_RK3036("vio", BIT(4), BIT(4), BIT(20), false), > + [RK3228_PD_VOP] = DOMAIN_RK3036("vop", BIT(5), BIT(5), BIT(21), false), > + [RK3228_PD_VPU] = DOMAIN_RK3036("vpu", BIT(6), BIT(6), BIT(22), false), > + [RK3228_PD_RKVDEC] = DOMAIN_RK3036("vdec", BIT(7), BIT(7), BIT(23), false), > + [RK3228_PD_GPU] = DOMAIN_RK3036("gpu", BIT(8), BIT(8), BIT(24), false), > + [RK3228_PD_PERI] = DOMAIN_RK3036("peri", BIT(9), BIT(9), BIT(25), true), > + [RK3228_PD_GMAC] = DOMAIN_RK3036("gmac", BIT(10), BIT(10), BIT(26), false), > }; > > static const struct rockchip_domain_info rk3288_pm_domains[] = { > - [RK3288_PD_VIO] = DOMAIN_RK3288(BIT(7), BIT(7), BIT(4), false), > - [RK3288_PD_HEVC] = DOMAIN_RK3288(BIT(14), BIT(10), BIT(9), false), > - [RK3288_PD_VIDEO] = DOMAIN_RK3288(BIT(8), BIT(8), BIT(3), false), > - [RK3288_PD_GPU] = DOMAIN_RK3288(BIT(9), BIT(9), BIT(2), false), > + [RK3288_PD_VIO] = DOMAIN_RK3288("vio", BIT(7), BIT(7), BIT(4), false), > + [RK3288_PD_HEVC] = DOMAIN_RK3288("hevc", BIT(14), BIT(10), BIT(9), false), > + [RK3288_PD_VIDEO] = DOMAIN_RK3288("video", BIT(8), BIT(8), BIT(3), false), > + [RK3288_PD_GPU] = DOMAIN_RK3288("gpu", BIT(9), BIT(9), BIT(2), false), > }; > > static const struct rockchip_domain_info rk3328_pm_domains[] = { > - [RK3328_PD_CORE] = DOMAIN_RK3328(0, BIT(0), BIT(0), false), > - [RK3328_PD_GPU] = DOMAIN_RK3328(0, BIT(1), BIT(1), false), > - [RK3328_PD_BUS] = DOMAIN_RK3328(0, BIT(2), BIT(2), true), > - [RK3328_PD_MSCH] = DOMAIN_RK3328(0, BIT(3), BIT(3), true), > - [RK3328_PD_PERI] = DOMAIN_RK3328(0, BIT(4), BIT(4), true), > - [RK3328_PD_VIDEO] = DOMAIN_RK3328(0, BIT(5), BIT(5), false), > - [RK3328_PD_HEVC] = DOMAIN_RK3328(0, BIT(6), BIT(6), false), > - [RK3328_PD_VIO] = DOMAIN_RK3328(0, BIT(8), BIT(8), false), > - [RK3328_PD_VPU] = DOMAIN_RK3328(0, BIT(9), BIT(9), false), > + [RK3328_PD_CORE] = DOMAIN_RK3328("core", 0, BIT(0), BIT(0), false), > + [RK3328_PD_GPU] = DOMAIN_RK3328("gpu", 0, BIT(1), BIT(1), false), > + [RK3328_PD_BUS] = DOMAIN_RK3328("bus", 0, BIT(2), BIT(2), true), > + [RK3328_PD_MSCH] = DOMAIN_RK3328("msch", 0, BIT(3), BIT(3), true), > + [RK3328_PD_PERI] = DOMAIN_RK3328("peri", 0, BIT(4), BIT(4), true), > + [RK3328_PD_VIDEO] = DOMAIN_RK3328("video", 0, BIT(5), BIT(5), false), > + [RK3328_PD_HEVC] = DOMAIN_RK3328("hevc", 0, BIT(6), BIT(6), false), > + [RK3328_PD_VIO] = DOMAIN_RK3328("vio", 0, BIT(8), BIT(8), false), > + [RK3328_PD_VPU] = DOMAIN_RK3328("vpu", 0, BIT(9), BIT(9), false), > }; > > static const struct rockchip_domain_info rk3366_pm_domains[] = { > - [RK3366_PD_PERI] = DOMAIN_RK3368(BIT(10), BIT(10), BIT(6), true), > - [RK3366_PD_VIO] = DOMAIN_RK3368(BIT(14), BIT(14), BIT(8), false), > - [RK3366_PD_VIDEO] = DOMAIN_RK3368(BIT(13), BIT(13), BIT(7), false), > - [RK3366_PD_RKVDEC] = DOMAIN_RK3368(BIT(11), BIT(11), BIT(7), false), > - [RK3366_PD_WIFIBT] = DOMAIN_RK3368(BIT(8), BIT(8), BIT(9), false), > - [RK3366_PD_VPU] = DOMAIN_RK3368(BIT(12), BIT(12), BIT(7), false), > - [RK3366_PD_GPU] = DOMAIN_RK3368(BIT(15), BIT(15), BIT(2), false), > + [RK3366_PD_PERI] = DOMAIN_RK3368("peri", BIT(10), BIT(10), BIT(6), true), > + [RK3366_PD_VIO] = DOMAIN_RK3368("vio", BIT(14), BIT(14), BIT(8), false), > + [RK3366_PD_VIDEO] = DOMAIN_RK3368("video", BIT(13), BIT(13), BIT(7), false), > + [RK3366_PD_RKVDEC] = DOMAIN_RK3368("vdec", BIT(11), BIT(11), BIT(7), false), > + [RK3366_PD_WIFIBT] = DOMAIN_RK3368("wifibt", BIT(8), BIT(8), BIT(9), false), > + [RK3366_PD_VPU] = DOMAIN_RK3368("vpu", BIT(12), BIT(12), BIT(7), false), > + [RK3366_PD_GPU] = DOMAIN_RK3368("gpu", BIT(15), BIT(15), BIT(2), false), > }; > > static const struct rockchip_domain_info rk3368_pm_domains[] = { > - [RK3368_PD_PERI] = DOMAIN_RK3368(BIT(13), BIT(12), BIT(6), true), > - [RK3368_PD_VIO] = DOMAIN_RK3368(BIT(15), BIT(14), BIT(8), false), > - [RK3368_PD_VIDEO] = DOMAIN_RK3368(BIT(14), BIT(13), BIT(7), false), > - [RK3368_PD_GPU_0] = DOMAIN_RK3368(BIT(16), BIT(15), BIT(2), false), > - [RK3368_PD_GPU_1] = DOMAIN_RK3368(BIT(17), BIT(16), BIT(2), false), > + [RK3368_PD_PERI] = DOMAIN_RK3368("peri", BIT(13), BIT(12), BIT(6), true), > + [RK3368_PD_VIO] = DOMAIN_RK3368("vio", BIT(15), BIT(14), BIT(8), false), > + [RK3368_PD_VIDEO] = DOMAIN_RK3368("video", BIT(14), BIT(13), BIT(7), false), > + [RK3368_PD_GPU_0] = DOMAIN_RK3368("gpu_0", BIT(16), BIT(15), BIT(2), false), > + [RK3368_PD_GPU_1] = DOMAIN_RK3368("gpu_1", BIT(17), BIT(16), BIT(2), false), > }; > > static const struct rockchip_domain_info rk3399_pm_domains[] = { > - [RK3399_PD_TCPD0] = DOMAIN_RK3399(BIT(8), BIT(8), 0, false), > - [RK3399_PD_TCPD1] = DOMAIN_RK3399(BIT(9), BIT(9), 0, false), > - [RK3399_PD_CCI] = DOMAIN_RK3399(BIT(10), BIT(10), 0, true), > - [RK3399_PD_CCI0] = DOMAIN_RK3399(0, 0, BIT(15), true), > - [RK3399_PD_CCI1] = DOMAIN_RK3399(0, 0, BIT(16), true), > - [RK3399_PD_PERILP] = DOMAIN_RK3399(BIT(11), BIT(11), BIT(1), true), > - [RK3399_PD_PERIHP] = DOMAIN_RK3399(BIT(12), BIT(12), BIT(2), true), > - [RK3399_PD_CENTER] = DOMAIN_RK3399(BIT(13), BIT(13), BIT(14), true), > - [RK3399_PD_VIO] = DOMAIN_RK3399(BIT(14), BIT(14), BIT(17), false), > - [RK3399_PD_GPU] = DOMAIN_RK3399(BIT(15), BIT(15), BIT(0), false), > - [RK3399_PD_VCODEC] = DOMAIN_RK3399(BIT(16), BIT(16), BIT(3), false), > - [RK3399_PD_VDU] = DOMAIN_RK3399(BIT(17), BIT(17), BIT(4), false), > - [RK3399_PD_RGA] = DOMAIN_RK3399(BIT(18), BIT(18), BIT(5), false), > - [RK3399_PD_IEP] = DOMAIN_RK3399(BIT(19), BIT(19), BIT(6), false), > - [RK3399_PD_VO] = DOMAIN_RK3399(BIT(20), BIT(20), 0, false), > - [RK3399_PD_VOPB] = DOMAIN_RK3399(0, 0, BIT(7), false), > - [RK3399_PD_VOPL] = DOMAIN_RK3399(0, 0, BIT(8), false), > - [RK3399_PD_ISP0] = DOMAIN_RK3399(BIT(22), BIT(22), BIT(9), false), > - [RK3399_PD_ISP1] = DOMAIN_RK3399(BIT(23), BIT(23), BIT(10), false), > - [RK3399_PD_HDCP] = DOMAIN_RK3399(BIT(24), BIT(24), BIT(11), false), > - [RK3399_PD_GMAC] = DOMAIN_RK3399(BIT(25), BIT(25), BIT(23), true), > - [RK3399_PD_EMMC] = DOMAIN_RK3399(BIT(26), BIT(26), BIT(24), true), > - [RK3399_PD_USB3] = DOMAIN_RK3399(BIT(27), BIT(27), BIT(12), true), > - [RK3399_PD_EDP] = DOMAIN_RK3399(BIT(28), BIT(28), BIT(22), false), > - [RK3399_PD_GIC] = DOMAIN_RK3399(BIT(29), BIT(29), BIT(27), true), > - [RK3399_PD_SD] = DOMAIN_RK3399(BIT(30), BIT(30), BIT(28), true), > - [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399(BIT(31), BIT(31), BIT(29), true), > + [RK3399_PD_TCPD0] = DOMAIN_RK3399("tcpd0", BIT(8), BIT(8), 0, false), > + [RK3399_PD_TCPD1] = DOMAIN_RK3399("tcpd1", BIT(9), BIT(9), 0, false), > + [RK3399_PD_CCI] = DOMAIN_RK3399("cci", BIT(10), BIT(10), 0, true), > + [RK3399_PD_CCI0] = DOMAIN_RK3399("cci0", 0, 0, BIT(15), true), > + [RK3399_PD_CCI1] = DOMAIN_RK3399("cci1", 0, 0, BIT(16), true), > + [RK3399_PD_PERILP] = DOMAIN_RK3399("perilp", BIT(11), BIT(11), BIT(1), true), > + [RK3399_PD_PERIHP] = DOMAIN_RK3399("perihp", BIT(12), BIT(12), BIT(2), true), > + [RK3399_PD_CENTER] = DOMAIN_RK3399("center", BIT(13), BIT(13), BIT(14), true), > + [RK3399_PD_VIO] = DOMAIN_RK3399("vio", BIT(14), BIT(14), BIT(17), false), > + [RK3399_PD_GPU] = DOMAIN_RK3399("gpu", BIT(15), BIT(15), BIT(0), false), > + [RK3399_PD_VCODEC] = DOMAIN_RK3399("vcodec", BIT(16), BIT(16), BIT(3), false), > + [RK3399_PD_VDU] = DOMAIN_RK3399("vdu", BIT(17), BIT(17), BIT(4), false), > + [RK3399_PD_RGA] = DOMAIN_RK3399("rga", BIT(18), BIT(18), BIT(5), false), > + [RK3399_PD_IEP] = DOMAIN_RK3399("iep", BIT(19), BIT(19), BIT(6), false), > + [RK3399_PD_VO] = DOMAIN_RK3399("vo", BIT(20), BIT(20), 0, false), > + [RK3399_PD_VOPB] = DOMAIN_RK3399("vopb", 0, 0, BIT(7), false), > + [RK3399_PD_VOPL] = DOMAIN_RK3399("vopl", 0, 0, BIT(8), false), > + [RK3399_PD_ISP0] = DOMAIN_RK3399("isp0", BIT(22), BIT(22), BIT(9), false), > + [RK3399_PD_ISP1] = DOMAIN_RK3399("isp1", BIT(23), BIT(23), BIT(10), false), > + [RK3399_PD_HDCP] = DOMAIN_RK3399("hdcp", BIT(24), BIT(24), BIT(11), false), > + [RK3399_PD_GMAC] = DOMAIN_RK3399("gmac", BIT(25), BIT(25), BIT(23), true), > + [RK3399_PD_EMMC] = DOMAIN_RK3399("emmc", BIT(26), BIT(26), BIT(24), true), > + [RK3399_PD_USB3] = DOMAIN_RK3399("usb3", BIT(27), BIT(27), BIT(12), true), > + [RK3399_PD_EDP] = DOMAIN_RK3399("edp", BIT(28), BIT(28), BIT(22), false), > + [RK3399_PD_GIC] = DOMAIN_RK3399("gic", BIT(29), BIT(29), BIT(27), true), > + [RK3399_PD_SD] = DOMAIN_RK3399("sd", BIT(30), BIT(30), BIT(28), true), > + [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true), > }; > > static const struct rockchip_pmu_info px30_pmu = { > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [RESEND PATCH v5 07/11] soc: rockchip: pm-domains: Add a meaningful power domain name 2021-03-26 9:52 ` Heiko Stübner (?) @ 2021-03-26 10:02 ` Heiko Stübner -1 siblings, 0 replies; 75+ messages in thread From: Heiko Stübner @ 2021-03-26 10:02 UTC (permalink / raw) To: robh+dt, Elaine Zhang Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang, enric.balletbo Hi Elaine again, Am Freitag, 26. März 2021, 10:52:53 CET schrieb Heiko Stübner: > Hi Elaine, > > [also adding that answer to the resend :-) ] > > Am Freitag, 26. März 2021, 10:17:39 CET schrieb Elaine Zhang: > > Add the power domains names to the power domain info struct so we > > have meaningful name for every power domain. > > > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> > > I like that approach very much, there is one tiny comment below. > > > --- > > drivers/soc/rockchip/pm_domains.c | 217 +++++++++++++++--------------- > > 1 file changed, 112 insertions(+), 105 deletions(-) > > > > diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c > > index 54eb6cfc5d5b..d661d967079f 100644 > > --- a/drivers/soc/rockchip/pm_domains.c > > +++ b/drivers/soc/rockchip/pm_domains.c > > @@ -29,6 +29,7 @@ > > #include <dt-bindings/power/rk3399-power.h> > > > > struct rockchip_domain_info { > > + const char *name; > > int pwr_mask; > > int status_mask; > > int req_mask; > > @@ -85,8 +86,9 @@ struct rockchip_pmu { > > > > #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd) > > > > -#define DOMAIN(pwr, status, req, idle, ack, wakeup) \ > > +#define DOMAIN(_name, pwr, status, req, idle, ack, wakeup) \ > > { \ > > + .name = _name, \ > > .pwr_mask = (pwr), \ > > .status_mask = (status), \ > > .req_mask = (req), \ > > @@ -95,8 +97,9 @@ struct rockchip_pmu { > > .active_wakeup = (wakeup), \ > > } > > > > -#define DOMAIN_M(pwr, status, req, idle, ack, wakeup) \ > > +#define DOMAIN_M(_name, pwr, status, req, idle, ack, wakeup) \ > > { \ > > + .name = _name, \ > > .pwr_w_mask = (pwr) << 16, \ > > .pwr_mask = (pwr), \ > > .status_mask = (status), \ > > @@ -107,8 +110,9 @@ struct rockchip_pmu { > > .active_wakeup = wakeup, \ > > } > > > > -#define DOMAIN_RK3036(req, ack, idle, wakeup) \ > > +#define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \ > > { \ > > + .name = _name, \ > > .req_mask = (req), \ > > .req_w_mask = (req) << 16, \ > > .ack_mask = (ack), \ > > @@ -119,17 +123,17 @@ struct rockchip_pmu { > > #define DOMAIN_PX30(pwr, status, req, wakeup) \ > > DOMAIN_M(pwr, status, req, (req) << 16, req, wakeup) > > > > -#define DOMAIN_RK3288(pwr, status, req, wakeup) \ > > - DOMAIN(pwr, status, req, req, (req) << 16, wakeup) > > +#define DOMAIN_RK3288(name, pwr, status, req, wakeup) \ > > + DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup) > > > > -#define DOMAIN_RK3328(pwr, status, req, wakeup) \ > > - DOMAIN_M(pwr, pwr, req, (req) << 10, req, wakeup) > > +#define DOMAIN_RK3328(name, pwr, status, req, wakeup) \ > > + DOMAIN_M(name, pwr, pwr, req, (req) << 10, req, wakeup) > > > > -#define DOMAIN_RK3368(pwr, status, req, wakeup) \ > > - DOMAIN(pwr, status, req, (req) << 16, req, wakeup) > > +#define DOMAIN_RK3368(name, pwr, status, req, wakeup) \ > > + DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup) > > > > -#define DOMAIN_RK3399(pwr, status, req, wakeup) \ > > - DOMAIN(pwr, status, req, req, req, wakeup) > > +#define DOMAIN_RK3399(name, pwr, status, req, wakeup) \ > > + DOMAIN(name, pwr, status, req, req, req, wakeup) > > > > static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd) > > { > > @@ -490,7 +494,10 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, > > goto err_unprepare_clocks; > > } > > > > - pd->genpd.name = node->name; > > + if (!pd->info->name) > > + pd->genpd.name = node->name; > > I guess we should make that "node->full_name" perhaps? > And I guess it might be nicer to swap the cases > > if (pd->info->name) > pd->genpd.name = pd->info->name > else > pd->genpd.name = node->full_name; > > for easier readability looking a bit through kernel-sources, maybe if (pd->info->name) pd->genpd.name = pd->info->name else pd->genpd.name = kbasename(node->full_name) might be even nicer? :-) Heiko > > + else > > + pd->genpd.name = pd->info->name; > > pd->genpd.power_off = rockchip_pd_power_off; > > pd->genpd.power_on = rockchip_pd_power_on; > > pd->genpd.attach_dev = rockchip_pd_attach_dev; > > @@ -716,129 +723,129 @@ static int rockchip_pm_domain_probe(struct platform_device *pdev) > > } > > > > static const struct rockchip_domain_info px30_pm_domains[] = { > > - [PX30_PD_USB] = DOMAIN_PX30(BIT(5), BIT(5), BIT(10), false), > > - [PX30_PD_SDCARD] = DOMAIN_PX30(BIT(8), BIT(8), BIT(9), false), > > - [PX30_PD_GMAC] = DOMAIN_PX30(BIT(10), BIT(10), BIT(6), false), > > - [PX30_PD_MMC_NAND] = DOMAIN_PX30(BIT(11), BIT(11), BIT(5), false), > > - [PX30_PD_VPU] = DOMAIN_PX30(BIT(12), BIT(12), BIT(14), false), > > - [PX30_PD_VO] = DOMAIN_PX30(BIT(13), BIT(13), BIT(7), false), > > - [PX30_PD_VI] = DOMAIN_PX30(BIT(14), BIT(14), BIT(8), false), > > - [PX30_PD_GPU] = DOMAIN_PX30(BIT(15), BIT(15), BIT(2), false), > > + [PX30_PD_USB] = DOMAIN_PX30("usb", BIT(5), BIT(5), BIT(10), false), > > + [PX30_PD_SDCARD] = DOMAIN_PX30("sdcard", BIT(8), BIT(8), BIT(9), false), > > + [PX30_PD_GMAC] = DOMAIN_PX30("gmac", BIT(10), BIT(10), BIT(6), false), > > + [PX30_PD_MMC_NAND] = DOMAIN_PX30("mmc_nand", BIT(11), BIT(11), BIT(5), false), > > + [PX30_PD_VPU] = DOMAIN_PX30("vpu", BIT(12), BIT(12), BIT(14), false), > > + [PX30_PD_VO] = DOMAIN_PX30("vo", BIT(13), BIT(13), BIT(7), false), > > + [PX30_PD_VI] = DOMAIN_PX30("vi", BIT(14), BIT(14), BIT(8), false), > > + [PX30_PD_GPU] = DOMAIN_PX30("gpu", BIT(15), BIT(15), BIT(2), false), > > }; > > > > static const struct rockchip_domain_info rk3036_pm_domains[] = { > > - [RK3036_PD_MSCH] = DOMAIN_RK3036(BIT(14), BIT(23), BIT(30), true), > > - [RK3036_PD_CORE] = DOMAIN_RK3036(BIT(13), BIT(17), BIT(24), false), > > - [RK3036_PD_PERI] = DOMAIN_RK3036(BIT(12), BIT(18), BIT(25), false), > > - [RK3036_PD_VIO] = DOMAIN_RK3036(BIT(11), BIT(19), BIT(26), false), > > - [RK3036_PD_VPU] = DOMAIN_RK3036(BIT(10), BIT(20), BIT(27), false), > > - [RK3036_PD_GPU] = DOMAIN_RK3036(BIT(9), BIT(21), BIT(28), false), > > - [RK3036_PD_SYS] = DOMAIN_RK3036(BIT(8), BIT(22), BIT(29), false), > > + [RK3036_PD_MSCH] = DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true), > > + [RK3036_PD_CORE] = DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false), > > + [RK3036_PD_PERI] = DOMAIN_RK3036("peri", BIT(12), BIT(18), BIT(25), false), > > + [RK3036_PD_VIO] = DOMAIN_RK3036("vio", BIT(11), BIT(19), BIT(26), false), > > + [RK3036_PD_VPU] = DOMAIN_RK3036("vpu", BIT(10), BIT(20), BIT(27), false), > > + [RK3036_PD_GPU] = DOMAIN_RK3036("gpu", BIT(9), BIT(21), BIT(28), false), > > + [RK3036_PD_SYS] = DOMAIN_RK3036("sys", BIT(8), BIT(22), BIT(29), false), > > }; > > > > static const struct rockchip_domain_info rk3066_pm_domains[] = { > > - [RK3066_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > > - [RK3066_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > > - [RK3066_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > > - [RK3066_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > > - [RK3066_PD_CPU] = DOMAIN(0, BIT(5), BIT(1), BIT(26), BIT(31), false), > > + [RK3066_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > > + [RK3066_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > > + [RK3066_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > > + [RK3066_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > > + [RK3066_PD_CPU] = DOMAIN("cpu", 0, BIT(5), BIT(1), BIT(26), BIT(31), false), > > }; > > > > static const struct rockchip_domain_info rk3128_pm_domains[] = { > > - [RK3128_PD_CORE] = DOMAIN_RK3288(BIT(0), BIT(0), BIT(4), false), > > - [RK3128_PD_MSCH] = DOMAIN_RK3288(0, 0, BIT(6), true), > > - [RK3128_PD_VIO] = DOMAIN_RK3288(BIT(3), BIT(3), BIT(2), false), > > - [RK3128_PD_VIDEO] = DOMAIN_RK3288(BIT(2), BIT(2), BIT(1), false), > > - [RK3128_PD_GPU] = DOMAIN_RK3288(BIT(1), BIT(1), BIT(3), false), > > + [RK3128_PD_CORE] = DOMAIN_RK3288("core", BIT(0), BIT(0), BIT(4), false), > > + [RK3128_PD_MSCH] = DOMAIN_RK3288("msch", 0, 0, BIT(6), true), > > + [RK3128_PD_VIO] = DOMAIN_RK3288("vio", BIT(3), BIT(3), BIT(2), false), > > + [RK3128_PD_VIDEO] = DOMAIN_RK3288("video", BIT(2), BIT(2), BIT(1), false), > > + [RK3128_PD_GPU] = DOMAIN_RK3288("gpu", BIT(1), BIT(1), BIT(3), false), > > }; > > > > static const struct rockchip_domain_info rk3188_pm_domains[] = { > > - [RK3188_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > > - [RK3188_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > > - [RK3188_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > > - [RK3188_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > > - [RK3188_PD_CPU] = DOMAIN(BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false), > > + [RK3188_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > > + [RK3188_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > > + [RK3188_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > > + [RK3188_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > > + [RK3188_PD_CPU] = DOMAIN("cpu", BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false), > > }; > > > > static const struct rockchip_domain_info rk3228_pm_domains[] = { > > - [RK3228_PD_CORE] = DOMAIN_RK3036(BIT(0), BIT(0), BIT(16), true), > > - [RK3228_PD_MSCH] = DOMAIN_RK3036(BIT(1), BIT(1), BIT(17), true), > > - [RK3228_PD_BUS] = DOMAIN_RK3036(BIT(2), BIT(2), BIT(18), true), > > - [RK3228_PD_SYS] = DOMAIN_RK3036(BIT(3), BIT(3), BIT(19), true), > > - [RK3228_PD_VIO] = DOMAIN_RK3036(BIT(4), BIT(4), BIT(20), false), > > - [RK3228_PD_VOP] = DOMAIN_RK3036(BIT(5), BIT(5), BIT(21), false), > > - [RK3228_PD_VPU] = DOMAIN_RK3036(BIT(6), BIT(6), BIT(22), false), > > - [RK3228_PD_RKVDEC] = DOMAIN_RK3036(BIT(7), BIT(7), BIT(23), false), > > - [RK3228_PD_GPU] = DOMAIN_RK3036(BIT(8), BIT(8), BIT(24), false), > > - [RK3228_PD_PERI] = DOMAIN_RK3036(BIT(9), BIT(9), BIT(25), true), > > - [RK3228_PD_GMAC] = DOMAIN_RK3036(BIT(10), BIT(10), BIT(26), false), > > + [RK3228_PD_CORE] = DOMAIN_RK3036("core", BIT(0), BIT(0), BIT(16), true), > > + [RK3228_PD_MSCH] = DOMAIN_RK3036("msch", BIT(1), BIT(1), BIT(17), true), > > + [RK3228_PD_BUS] = DOMAIN_RK3036("bus", BIT(2), BIT(2), BIT(18), true), > > + [RK3228_PD_SYS] = DOMAIN_RK3036("sys", BIT(3), BIT(3), BIT(19), true), > > + [RK3228_PD_VIO] = DOMAIN_RK3036("vio", BIT(4), BIT(4), BIT(20), false), > > + [RK3228_PD_VOP] = DOMAIN_RK3036("vop", BIT(5), BIT(5), BIT(21), false), > > + [RK3228_PD_VPU] = DOMAIN_RK3036("vpu", BIT(6), BIT(6), BIT(22), false), > > + [RK3228_PD_RKVDEC] = DOMAIN_RK3036("vdec", BIT(7), BIT(7), BIT(23), false), > > + [RK3228_PD_GPU] = DOMAIN_RK3036("gpu", BIT(8), BIT(8), BIT(24), false), > > + [RK3228_PD_PERI] = DOMAIN_RK3036("peri", BIT(9), BIT(9), BIT(25), true), > > + [RK3228_PD_GMAC] = DOMAIN_RK3036("gmac", BIT(10), BIT(10), BIT(26), false), > > }; > > > > static const struct rockchip_domain_info rk3288_pm_domains[] = { > > - [RK3288_PD_VIO] = DOMAIN_RK3288(BIT(7), BIT(7), BIT(4), false), > > - [RK3288_PD_HEVC] = DOMAIN_RK3288(BIT(14), BIT(10), BIT(9), false), > > - [RK3288_PD_VIDEO] = DOMAIN_RK3288(BIT(8), BIT(8), BIT(3), false), > > - [RK3288_PD_GPU] = DOMAIN_RK3288(BIT(9), BIT(9), BIT(2), false), > > + [RK3288_PD_VIO] = DOMAIN_RK3288("vio", BIT(7), BIT(7), BIT(4), false), > > + [RK3288_PD_HEVC] = DOMAIN_RK3288("hevc", BIT(14), BIT(10), BIT(9), false), > > + [RK3288_PD_VIDEO] = DOMAIN_RK3288("video", BIT(8), BIT(8), BIT(3), false), > > + [RK3288_PD_GPU] = DOMAIN_RK3288("gpu", BIT(9), BIT(9), BIT(2), false), > > }; > > > > static const struct rockchip_domain_info rk3328_pm_domains[] = { > > - [RK3328_PD_CORE] = DOMAIN_RK3328(0, BIT(0), BIT(0), false), > > - [RK3328_PD_GPU] = DOMAIN_RK3328(0, BIT(1), BIT(1), false), > > - [RK3328_PD_BUS] = DOMAIN_RK3328(0, BIT(2), BIT(2), true), > > - [RK3328_PD_MSCH] = DOMAIN_RK3328(0, BIT(3), BIT(3), true), > > - [RK3328_PD_PERI] = DOMAIN_RK3328(0, BIT(4), BIT(4), true), > > - [RK3328_PD_VIDEO] = DOMAIN_RK3328(0, BIT(5), BIT(5), false), > > - [RK3328_PD_HEVC] = DOMAIN_RK3328(0, BIT(6), BIT(6), false), > > - [RK3328_PD_VIO] = DOMAIN_RK3328(0, BIT(8), BIT(8), false), > > - [RK3328_PD_VPU] = DOMAIN_RK3328(0, BIT(9), BIT(9), false), > > + [RK3328_PD_CORE] = DOMAIN_RK3328("core", 0, BIT(0), BIT(0), false), > > + [RK3328_PD_GPU] = DOMAIN_RK3328("gpu", 0, BIT(1), BIT(1), false), > > + [RK3328_PD_BUS] = DOMAIN_RK3328("bus", 0, BIT(2), BIT(2), true), > > + [RK3328_PD_MSCH] = DOMAIN_RK3328("msch", 0, BIT(3), BIT(3), true), > > + [RK3328_PD_PERI] = DOMAIN_RK3328("peri", 0, BIT(4), BIT(4), true), > > + [RK3328_PD_VIDEO] = DOMAIN_RK3328("video", 0, BIT(5), BIT(5), false), > > + [RK3328_PD_HEVC] = DOMAIN_RK3328("hevc", 0, BIT(6), BIT(6), false), > > + [RK3328_PD_VIO] = DOMAIN_RK3328("vio", 0, BIT(8), BIT(8), false), > > + [RK3328_PD_VPU] = DOMAIN_RK3328("vpu", 0, BIT(9), BIT(9), false), > > }; > > > > static const struct rockchip_domain_info rk3366_pm_domains[] = { > > - [RK3366_PD_PERI] = DOMAIN_RK3368(BIT(10), BIT(10), BIT(6), true), > > - [RK3366_PD_VIO] = DOMAIN_RK3368(BIT(14), BIT(14), BIT(8), false), > > - [RK3366_PD_VIDEO] = DOMAIN_RK3368(BIT(13), BIT(13), BIT(7), false), > > - [RK3366_PD_RKVDEC] = DOMAIN_RK3368(BIT(11), BIT(11), BIT(7), false), > > - [RK3366_PD_WIFIBT] = DOMAIN_RK3368(BIT(8), BIT(8), BIT(9), false), > > - [RK3366_PD_VPU] = DOMAIN_RK3368(BIT(12), BIT(12), BIT(7), false), > > - [RK3366_PD_GPU] = DOMAIN_RK3368(BIT(15), BIT(15), BIT(2), false), > > + [RK3366_PD_PERI] = DOMAIN_RK3368("peri", BIT(10), BIT(10), BIT(6), true), > > + [RK3366_PD_VIO] = DOMAIN_RK3368("vio", BIT(14), BIT(14), BIT(8), false), > > + [RK3366_PD_VIDEO] = DOMAIN_RK3368("video", BIT(13), BIT(13), BIT(7), false), > > + [RK3366_PD_RKVDEC] = DOMAIN_RK3368("vdec", BIT(11), BIT(11), BIT(7), false), > > + [RK3366_PD_WIFIBT] = DOMAIN_RK3368("wifibt", BIT(8), BIT(8), BIT(9), false), > > + [RK3366_PD_VPU] = DOMAIN_RK3368("vpu", BIT(12), BIT(12), BIT(7), false), > > + [RK3366_PD_GPU] = DOMAIN_RK3368("gpu", BIT(15), BIT(15), BIT(2), false), > > }; > > > > static const struct rockchip_domain_info rk3368_pm_domains[] = { > > - [RK3368_PD_PERI] = DOMAIN_RK3368(BIT(13), BIT(12), BIT(6), true), > > - [RK3368_PD_VIO] = DOMAIN_RK3368(BIT(15), BIT(14), BIT(8), false), > > - [RK3368_PD_VIDEO] = DOMAIN_RK3368(BIT(14), BIT(13), BIT(7), false), > > - [RK3368_PD_GPU_0] = DOMAIN_RK3368(BIT(16), BIT(15), BIT(2), false), > > - [RK3368_PD_GPU_1] = DOMAIN_RK3368(BIT(17), BIT(16), BIT(2), false), > > + [RK3368_PD_PERI] = DOMAIN_RK3368("peri", BIT(13), BIT(12), BIT(6), true), > > + [RK3368_PD_VIO] = DOMAIN_RK3368("vio", BIT(15), BIT(14), BIT(8), false), > > + [RK3368_PD_VIDEO] = DOMAIN_RK3368("video", BIT(14), BIT(13), BIT(7), false), > > + [RK3368_PD_GPU_0] = DOMAIN_RK3368("gpu_0", BIT(16), BIT(15), BIT(2), false), > > + [RK3368_PD_GPU_1] = DOMAIN_RK3368("gpu_1", BIT(17), BIT(16), BIT(2), false), > > }; > > > > static const struct rockchip_domain_info rk3399_pm_domains[] = { > > - [RK3399_PD_TCPD0] = DOMAIN_RK3399(BIT(8), BIT(8), 0, false), > > - [RK3399_PD_TCPD1] = DOMAIN_RK3399(BIT(9), BIT(9), 0, false), > > - [RK3399_PD_CCI] = DOMAIN_RK3399(BIT(10), BIT(10), 0, true), > > - [RK3399_PD_CCI0] = DOMAIN_RK3399(0, 0, BIT(15), true), > > - [RK3399_PD_CCI1] = DOMAIN_RK3399(0, 0, BIT(16), true), > > - [RK3399_PD_PERILP] = DOMAIN_RK3399(BIT(11), BIT(11), BIT(1), true), > > - [RK3399_PD_PERIHP] = DOMAIN_RK3399(BIT(12), BIT(12), BIT(2), true), > > - [RK3399_PD_CENTER] = DOMAIN_RK3399(BIT(13), BIT(13), BIT(14), true), > > - [RK3399_PD_VIO] = DOMAIN_RK3399(BIT(14), BIT(14), BIT(17), false), > > - [RK3399_PD_GPU] = DOMAIN_RK3399(BIT(15), BIT(15), BIT(0), false), > > - [RK3399_PD_VCODEC] = DOMAIN_RK3399(BIT(16), BIT(16), BIT(3), false), > > - [RK3399_PD_VDU] = DOMAIN_RK3399(BIT(17), BIT(17), BIT(4), false), > > - [RK3399_PD_RGA] = DOMAIN_RK3399(BIT(18), BIT(18), BIT(5), false), > > - [RK3399_PD_IEP] = DOMAIN_RK3399(BIT(19), BIT(19), BIT(6), false), > > - [RK3399_PD_VO] = DOMAIN_RK3399(BIT(20), BIT(20), 0, false), > > - [RK3399_PD_VOPB] = DOMAIN_RK3399(0, 0, BIT(7), false), > > - [RK3399_PD_VOPL] = DOMAIN_RK3399(0, 0, BIT(8), false), > > - [RK3399_PD_ISP0] = DOMAIN_RK3399(BIT(22), BIT(22), BIT(9), false), > > - [RK3399_PD_ISP1] = DOMAIN_RK3399(BIT(23), BIT(23), BIT(10), false), > > - [RK3399_PD_HDCP] = DOMAIN_RK3399(BIT(24), BIT(24), BIT(11), false), > > - [RK3399_PD_GMAC] = DOMAIN_RK3399(BIT(25), BIT(25), BIT(23), true), > > - [RK3399_PD_EMMC] = DOMAIN_RK3399(BIT(26), BIT(26), BIT(24), true), > > - [RK3399_PD_USB3] = DOMAIN_RK3399(BIT(27), BIT(27), BIT(12), true), > > - [RK3399_PD_EDP] = DOMAIN_RK3399(BIT(28), BIT(28), BIT(22), false), > > - [RK3399_PD_GIC] = DOMAIN_RK3399(BIT(29), BIT(29), BIT(27), true), > > - [RK3399_PD_SD] = DOMAIN_RK3399(BIT(30), BIT(30), BIT(28), true), > > - [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399(BIT(31), BIT(31), BIT(29), true), > > + [RK3399_PD_TCPD0] = DOMAIN_RK3399("tcpd0", BIT(8), BIT(8), 0, false), > > + [RK3399_PD_TCPD1] = DOMAIN_RK3399("tcpd1", BIT(9), BIT(9), 0, false), > > + [RK3399_PD_CCI] = DOMAIN_RK3399("cci", BIT(10), BIT(10), 0, true), > > + [RK3399_PD_CCI0] = DOMAIN_RK3399("cci0", 0, 0, BIT(15), true), > > + [RK3399_PD_CCI1] = DOMAIN_RK3399("cci1", 0, 0, BIT(16), true), > > + [RK3399_PD_PERILP] = DOMAIN_RK3399("perilp", BIT(11), BIT(11), BIT(1), true), > > + [RK3399_PD_PERIHP] = DOMAIN_RK3399("perihp", BIT(12), BIT(12), BIT(2), true), > > + [RK3399_PD_CENTER] = DOMAIN_RK3399("center", BIT(13), BIT(13), BIT(14), true), > > + [RK3399_PD_VIO] = DOMAIN_RK3399("vio", BIT(14), BIT(14), BIT(17), false), > > + [RK3399_PD_GPU] = DOMAIN_RK3399("gpu", BIT(15), BIT(15), BIT(0), false), > > + [RK3399_PD_VCODEC] = DOMAIN_RK3399("vcodec", BIT(16), BIT(16), BIT(3), false), > > + [RK3399_PD_VDU] = DOMAIN_RK3399("vdu", BIT(17), BIT(17), BIT(4), false), > > + [RK3399_PD_RGA] = DOMAIN_RK3399("rga", BIT(18), BIT(18), BIT(5), false), > > + [RK3399_PD_IEP] = DOMAIN_RK3399("iep", BIT(19), BIT(19), BIT(6), false), > > + [RK3399_PD_VO] = DOMAIN_RK3399("vo", BIT(20), BIT(20), 0, false), > > + [RK3399_PD_VOPB] = DOMAIN_RK3399("vopb", 0, 0, BIT(7), false), > > + [RK3399_PD_VOPL] = DOMAIN_RK3399("vopl", 0, 0, BIT(8), false), > > + [RK3399_PD_ISP0] = DOMAIN_RK3399("isp0", BIT(22), BIT(22), BIT(9), false), > > + [RK3399_PD_ISP1] = DOMAIN_RK3399("isp1", BIT(23), BIT(23), BIT(10), false), > > + [RK3399_PD_HDCP] = DOMAIN_RK3399("hdcp", BIT(24), BIT(24), BIT(11), false), > > + [RK3399_PD_GMAC] = DOMAIN_RK3399("gmac", BIT(25), BIT(25), BIT(23), true), > > + [RK3399_PD_EMMC] = DOMAIN_RK3399("emmc", BIT(26), BIT(26), BIT(24), true), > > + [RK3399_PD_USB3] = DOMAIN_RK3399("usb3", BIT(27), BIT(27), BIT(12), true), > > + [RK3399_PD_EDP] = DOMAIN_RK3399("edp", BIT(28), BIT(28), BIT(22), false), > > + [RK3399_PD_GIC] = DOMAIN_RK3399("gic", BIT(29), BIT(29), BIT(27), true), > > + [RK3399_PD_SD] = DOMAIN_RK3399("sd", BIT(30), BIT(30), BIT(28), true), > > + [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true), > > }; > > > > static const struct rockchip_pmu_info px30_pmu = { > > > _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [RESEND PATCH v5 07/11] soc: rockchip: pm-domains: Add a meaningful power domain name @ 2021-03-26 10:02 ` Heiko Stübner 0 siblings, 0 replies; 75+ messages in thread From: Heiko Stübner @ 2021-03-26 10:02 UTC (permalink / raw) To: robh+dt, Elaine Zhang Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang, enric.balletbo Hi Elaine again, Am Freitag, 26. März 2021, 10:52:53 CET schrieb Heiko Stübner: > Hi Elaine, > > [also adding that answer to the resend :-) ] > > Am Freitag, 26. März 2021, 10:17:39 CET schrieb Elaine Zhang: > > Add the power domains names to the power domain info struct so we > > have meaningful name for every power domain. > > > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> > > I like that approach very much, there is one tiny comment below. > > > --- > > drivers/soc/rockchip/pm_domains.c | 217 +++++++++++++++--------------- > > 1 file changed, 112 insertions(+), 105 deletions(-) > > > > diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c > > index 54eb6cfc5d5b..d661d967079f 100644 > > --- a/drivers/soc/rockchip/pm_domains.c > > +++ b/drivers/soc/rockchip/pm_domains.c > > @@ -29,6 +29,7 @@ > > #include <dt-bindings/power/rk3399-power.h> > > > > struct rockchip_domain_info { > > + const char *name; > > int pwr_mask; > > int status_mask; > > int req_mask; > > @@ -85,8 +86,9 @@ struct rockchip_pmu { > > > > #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd) > > > > -#define DOMAIN(pwr, status, req, idle, ack, wakeup) \ > > +#define DOMAIN(_name, pwr, status, req, idle, ack, wakeup) \ > > { \ > > + .name = _name, \ > > .pwr_mask = (pwr), \ > > .status_mask = (status), \ > > .req_mask = (req), \ > > @@ -95,8 +97,9 @@ struct rockchip_pmu { > > .active_wakeup = (wakeup), \ > > } > > > > -#define DOMAIN_M(pwr, status, req, idle, ack, wakeup) \ > > +#define DOMAIN_M(_name, pwr, status, req, idle, ack, wakeup) \ > > { \ > > + .name = _name, \ > > .pwr_w_mask = (pwr) << 16, \ > > .pwr_mask = (pwr), \ > > .status_mask = (status), \ > > @@ -107,8 +110,9 @@ struct rockchip_pmu { > > .active_wakeup = wakeup, \ > > } > > > > -#define DOMAIN_RK3036(req, ack, idle, wakeup) \ > > +#define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \ > > { \ > > + .name = _name, \ > > .req_mask = (req), \ > > .req_w_mask = (req) << 16, \ > > .ack_mask = (ack), \ > > @@ -119,17 +123,17 @@ struct rockchip_pmu { > > #define DOMAIN_PX30(pwr, status, req, wakeup) \ > > DOMAIN_M(pwr, status, req, (req) << 16, req, wakeup) > > > > -#define DOMAIN_RK3288(pwr, status, req, wakeup) \ > > - DOMAIN(pwr, status, req, req, (req) << 16, wakeup) > > +#define DOMAIN_RK3288(name, pwr, status, req, wakeup) \ > > + DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup) > > > > -#define DOMAIN_RK3328(pwr, status, req, wakeup) \ > > - DOMAIN_M(pwr, pwr, req, (req) << 10, req, wakeup) > > +#define DOMAIN_RK3328(name, pwr, status, req, wakeup) \ > > + DOMAIN_M(name, pwr, pwr, req, (req) << 10, req, wakeup) > > > > -#define DOMAIN_RK3368(pwr, status, req, wakeup) \ > > - DOMAIN(pwr, status, req, (req) << 16, req, wakeup) > > +#define DOMAIN_RK3368(name, pwr, status, req, wakeup) \ > > + DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup) > > > > -#define DOMAIN_RK3399(pwr, status, req, wakeup) \ > > - DOMAIN(pwr, status, req, req, req, wakeup) > > +#define DOMAIN_RK3399(name, pwr, status, req, wakeup) \ > > + DOMAIN(name, pwr, status, req, req, req, wakeup) > > > > static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd) > > { > > @@ -490,7 +494,10 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, > > goto err_unprepare_clocks; > > } > > > > - pd->genpd.name = node->name; > > + if (!pd->info->name) > > + pd->genpd.name = node->name; > > I guess we should make that "node->full_name" perhaps? > And I guess it might be nicer to swap the cases > > if (pd->info->name) > pd->genpd.name = pd->info->name > else > pd->genpd.name = node->full_name; > > for easier readability looking a bit through kernel-sources, maybe if (pd->info->name) pd->genpd.name = pd->info->name else pd->genpd.name = kbasename(node->full_name) might be even nicer? :-) Heiko > > + else > > + pd->genpd.name = pd->info->name; > > pd->genpd.power_off = rockchip_pd_power_off; > > pd->genpd.power_on = rockchip_pd_power_on; > > pd->genpd.attach_dev = rockchip_pd_attach_dev; > > @@ -716,129 +723,129 @@ static int rockchip_pm_domain_probe(struct platform_device *pdev) > > } > > > > static const struct rockchip_domain_info px30_pm_domains[] = { > > - [PX30_PD_USB] = DOMAIN_PX30(BIT(5), BIT(5), BIT(10), false), > > - [PX30_PD_SDCARD] = DOMAIN_PX30(BIT(8), BIT(8), BIT(9), false), > > - [PX30_PD_GMAC] = DOMAIN_PX30(BIT(10), BIT(10), BIT(6), false), > > - [PX30_PD_MMC_NAND] = DOMAIN_PX30(BIT(11), BIT(11), BIT(5), false), > > - [PX30_PD_VPU] = DOMAIN_PX30(BIT(12), BIT(12), BIT(14), false), > > - [PX30_PD_VO] = DOMAIN_PX30(BIT(13), BIT(13), BIT(7), false), > > - [PX30_PD_VI] = DOMAIN_PX30(BIT(14), BIT(14), BIT(8), false), > > - [PX30_PD_GPU] = DOMAIN_PX30(BIT(15), BIT(15), BIT(2), false), > > + [PX30_PD_USB] = DOMAIN_PX30("usb", BIT(5), BIT(5), BIT(10), false), > > + [PX30_PD_SDCARD] = DOMAIN_PX30("sdcard", BIT(8), BIT(8), BIT(9), false), > > + [PX30_PD_GMAC] = DOMAIN_PX30("gmac", BIT(10), BIT(10), BIT(6), false), > > + [PX30_PD_MMC_NAND] = DOMAIN_PX30("mmc_nand", BIT(11), BIT(11), BIT(5), false), > > + [PX30_PD_VPU] = DOMAIN_PX30("vpu", BIT(12), BIT(12), BIT(14), false), > > + [PX30_PD_VO] = DOMAIN_PX30("vo", BIT(13), BIT(13), BIT(7), false), > > + [PX30_PD_VI] = DOMAIN_PX30("vi", BIT(14), BIT(14), BIT(8), false), > > + [PX30_PD_GPU] = DOMAIN_PX30("gpu", BIT(15), BIT(15), BIT(2), false), > > }; > > > > static const struct rockchip_domain_info rk3036_pm_domains[] = { > > - [RK3036_PD_MSCH] = DOMAIN_RK3036(BIT(14), BIT(23), BIT(30), true), > > - [RK3036_PD_CORE] = DOMAIN_RK3036(BIT(13), BIT(17), BIT(24), false), > > - [RK3036_PD_PERI] = DOMAIN_RK3036(BIT(12), BIT(18), BIT(25), false), > > - [RK3036_PD_VIO] = DOMAIN_RK3036(BIT(11), BIT(19), BIT(26), false), > > - [RK3036_PD_VPU] = DOMAIN_RK3036(BIT(10), BIT(20), BIT(27), false), > > - [RK3036_PD_GPU] = DOMAIN_RK3036(BIT(9), BIT(21), BIT(28), false), > > - [RK3036_PD_SYS] = DOMAIN_RK3036(BIT(8), BIT(22), BIT(29), false), > > + [RK3036_PD_MSCH] = DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true), > > + [RK3036_PD_CORE] = DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false), > > + [RK3036_PD_PERI] = DOMAIN_RK3036("peri", BIT(12), BIT(18), BIT(25), false), > > + [RK3036_PD_VIO] = DOMAIN_RK3036("vio", BIT(11), BIT(19), BIT(26), false), > > + [RK3036_PD_VPU] = DOMAIN_RK3036("vpu", BIT(10), BIT(20), BIT(27), false), > > + [RK3036_PD_GPU] = DOMAIN_RK3036("gpu", BIT(9), BIT(21), BIT(28), false), > > + [RK3036_PD_SYS] = DOMAIN_RK3036("sys", BIT(8), BIT(22), BIT(29), false), > > }; > > > > static const struct rockchip_domain_info rk3066_pm_domains[] = { > > - [RK3066_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > > - [RK3066_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > > - [RK3066_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > > - [RK3066_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > > - [RK3066_PD_CPU] = DOMAIN(0, BIT(5), BIT(1), BIT(26), BIT(31), false), > > + [RK3066_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > > + [RK3066_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > > + [RK3066_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > > + [RK3066_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > > + [RK3066_PD_CPU] = DOMAIN("cpu", 0, BIT(5), BIT(1), BIT(26), BIT(31), false), > > }; > > > > static const struct rockchip_domain_info rk3128_pm_domains[] = { > > - [RK3128_PD_CORE] = DOMAIN_RK3288(BIT(0), BIT(0), BIT(4), false), > > - [RK3128_PD_MSCH] = DOMAIN_RK3288(0, 0, BIT(6), true), > > - [RK3128_PD_VIO] = DOMAIN_RK3288(BIT(3), BIT(3), BIT(2), false), > > - [RK3128_PD_VIDEO] = DOMAIN_RK3288(BIT(2), BIT(2), BIT(1), false), > > - [RK3128_PD_GPU] = DOMAIN_RK3288(BIT(1), BIT(1), BIT(3), false), > > + [RK3128_PD_CORE] = DOMAIN_RK3288("core", BIT(0), BIT(0), BIT(4), false), > > + [RK3128_PD_MSCH] = DOMAIN_RK3288("msch", 0, 0, BIT(6), true), > > + [RK3128_PD_VIO] = DOMAIN_RK3288("vio", BIT(3), BIT(3), BIT(2), false), > > + [RK3128_PD_VIDEO] = DOMAIN_RK3288("video", BIT(2), BIT(2), BIT(1), false), > > + [RK3128_PD_GPU] = DOMAIN_RK3288("gpu", BIT(1), BIT(1), BIT(3), false), > > }; > > > > static const struct rockchip_domain_info rk3188_pm_domains[] = { > > - [RK3188_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > > - [RK3188_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > > - [RK3188_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > > - [RK3188_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > > - [RK3188_PD_CPU] = DOMAIN(BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false), > > + [RK3188_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > > + [RK3188_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > > + [RK3188_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > > + [RK3188_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > > + [RK3188_PD_CPU] = DOMAIN("cpu", BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false), > > }; > > > > static const struct rockchip_domain_info rk3228_pm_domains[] = { > > - [RK3228_PD_CORE] = DOMAIN_RK3036(BIT(0), BIT(0), BIT(16), true), > > - [RK3228_PD_MSCH] = DOMAIN_RK3036(BIT(1), BIT(1), BIT(17), true), > > - [RK3228_PD_BUS] = DOMAIN_RK3036(BIT(2), BIT(2), BIT(18), true), > > - [RK3228_PD_SYS] = DOMAIN_RK3036(BIT(3), BIT(3), BIT(19), true), > > - [RK3228_PD_VIO] = DOMAIN_RK3036(BIT(4), BIT(4), BIT(20), false), > > - [RK3228_PD_VOP] = DOMAIN_RK3036(BIT(5), BIT(5), BIT(21), false), > > - [RK3228_PD_VPU] = DOMAIN_RK3036(BIT(6), BIT(6), BIT(22), false), > > - [RK3228_PD_RKVDEC] = DOMAIN_RK3036(BIT(7), BIT(7), BIT(23), false), > > - [RK3228_PD_GPU] = DOMAIN_RK3036(BIT(8), BIT(8), BIT(24), false), > > - [RK3228_PD_PERI] = DOMAIN_RK3036(BIT(9), BIT(9), BIT(25), true), > > - [RK3228_PD_GMAC] = DOMAIN_RK3036(BIT(10), BIT(10), BIT(26), false), > > + [RK3228_PD_CORE] = DOMAIN_RK3036("core", BIT(0), BIT(0), BIT(16), true), > > + [RK3228_PD_MSCH] = DOMAIN_RK3036("msch", BIT(1), BIT(1), BIT(17), true), > > + [RK3228_PD_BUS] = DOMAIN_RK3036("bus", BIT(2), BIT(2), BIT(18), true), > > + [RK3228_PD_SYS] = DOMAIN_RK3036("sys", BIT(3), BIT(3), BIT(19), true), > > + [RK3228_PD_VIO] = DOMAIN_RK3036("vio", BIT(4), BIT(4), BIT(20), false), > > + [RK3228_PD_VOP] = DOMAIN_RK3036("vop", BIT(5), BIT(5), BIT(21), false), > > + [RK3228_PD_VPU] = DOMAIN_RK3036("vpu", BIT(6), BIT(6), BIT(22), false), > > + [RK3228_PD_RKVDEC] = DOMAIN_RK3036("vdec", BIT(7), BIT(7), BIT(23), false), > > + [RK3228_PD_GPU] = DOMAIN_RK3036("gpu", BIT(8), BIT(8), BIT(24), false), > > + [RK3228_PD_PERI] = DOMAIN_RK3036("peri", BIT(9), BIT(9), BIT(25), true), > > + [RK3228_PD_GMAC] = DOMAIN_RK3036("gmac", BIT(10), BIT(10), BIT(26), false), > > }; > > > > static const struct rockchip_domain_info rk3288_pm_domains[] = { > > - [RK3288_PD_VIO] = DOMAIN_RK3288(BIT(7), BIT(7), BIT(4), false), > > - [RK3288_PD_HEVC] = DOMAIN_RK3288(BIT(14), BIT(10), BIT(9), false), > > - [RK3288_PD_VIDEO] = DOMAIN_RK3288(BIT(8), BIT(8), BIT(3), false), > > - [RK3288_PD_GPU] = DOMAIN_RK3288(BIT(9), BIT(9), BIT(2), false), > > + [RK3288_PD_VIO] = DOMAIN_RK3288("vio", BIT(7), BIT(7), BIT(4), false), > > + [RK3288_PD_HEVC] = DOMAIN_RK3288("hevc", BIT(14), BIT(10), BIT(9), false), > > + [RK3288_PD_VIDEO] = DOMAIN_RK3288("video", BIT(8), BIT(8), BIT(3), false), > > + [RK3288_PD_GPU] = DOMAIN_RK3288("gpu", BIT(9), BIT(9), BIT(2), false), > > }; > > > > static const struct rockchip_domain_info rk3328_pm_domains[] = { > > - [RK3328_PD_CORE] = DOMAIN_RK3328(0, BIT(0), BIT(0), false), > > - [RK3328_PD_GPU] = DOMAIN_RK3328(0, BIT(1), BIT(1), false), > > - [RK3328_PD_BUS] = DOMAIN_RK3328(0, BIT(2), BIT(2), true), > > - [RK3328_PD_MSCH] = DOMAIN_RK3328(0, BIT(3), BIT(3), true), > > - [RK3328_PD_PERI] = DOMAIN_RK3328(0, BIT(4), BIT(4), true), > > - [RK3328_PD_VIDEO] = DOMAIN_RK3328(0, BIT(5), BIT(5), false), > > - [RK3328_PD_HEVC] = DOMAIN_RK3328(0, BIT(6), BIT(6), false), > > - [RK3328_PD_VIO] = DOMAIN_RK3328(0, BIT(8), BIT(8), false), > > - [RK3328_PD_VPU] = DOMAIN_RK3328(0, BIT(9), BIT(9), false), > > + [RK3328_PD_CORE] = DOMAIN_RK3328("core", 0, BIT(0), BIT(0), false), > > + [RK3328_PD_GPU] = DOMAIN_RK3328("gpu", 0, BIT(1), BIT(1), false), > > + [RK3328_PD_BUS] = DOMAIN_RK3328("bus", 0, BIT(2), BIT(2), true), > > + [RK3328_PD_MSCH] = DOMAIN_RK3328("msch", 0, BIT(3), BIT(3), true), > > + [RK3328_PD_PERI] = DOMAIN_RK3328("peri", 0, BIT(4), BIT(4), true), > > + [RK3328_PD_VIDEO] = DOMAIN_RK3328("video", 0, BIT(5), BIT(5), false), > > + [RK3328_PD_HEVC] = DOMAIN_RK3328("hevc", 0, BIT(6), BIT(6), false), > > + [RK3328_PD_VIO] = DOMAIN_RK3328("vio", 0, BIT(8), BIT(8), false), > > + [RK3328_PD_VPU] = DOMAIN_RK3328("vpu", 0, BIT(9), BIT(9), false), > > }; > > > > static const struct rockchip_domain_info rk3366_pm_domains[] = { > > - [RK3366_PD_PERI] = DOMAIN_RK3368(BIT(10), BIT(10), BIT(6), true), > > - [RK3366_PD_VIO] = DOMAIN_RK3368(BIT(14), BIT(14), BIT(8), false), > > - [RK3366_PD_VIDEO] = DOMAIN_RK3368(BIT(13), BIT(13), BIT(7), false), > > - [RK3366_PD_RKVDEC] = DOMAIN_RK3368(BIT(11), BIT(11), BIT(7), false), > > - [RK3366_PD_WIFIBT] = DOMAIN_RK3368(BIT(8), BIT(8), BIT(9), false), > > - [RK3366_PD_VPU] = DOMAIN_RK3368(BIT(12), BIT(12), BIT(7), false), > > - [RK3366_PD_GPU] = DOMAIN_RK3368(BIT(15), BIT(15), BIT(2), false), > > + [RK3366_PD_PERI] = DOMAIN_RK3368("peri", BIT(10), BIT(10), BIT(6), true), > > + [RK3366_PD_VIO] = DOMAIN_RK3368("vio", BIT(14), BIT(14), BIT(8), false), > > + [RK3366_PD_VIDEO] = DOMAIN_RK3368("video", BIT(13), BIT(13), BIT(7), false), > > + [RK3366_PD_RKVDEC] = DOMAIN_RK3368("vdec", BIT(11), BIT(11), BIT(7), false), > > + [RK3366_PD_WIFIBT] = DOMAIN_RK3368("wifibt", BIT(8), BIT(8), BIT(9), false), > > + [RK3366_PD_VPU] = DOMAIN_RK3368("vpu", BIT(12), BIT(12), BIT(7), false), > > + [RK3366_PD_GPU] = DOMAIN_RK3368("gpu", BIT(15), BIT(15), BIT(2), false), > > }; > > > > static const struct rockchip_domain_info rk3368_pm_domains[] = { > > - [RK3368_PD_PERI] = DOMAIN_RK3368(BIT(13), BIT(12), BIT(6), true), > > - [RK3368_PD_VIO] = DOMAIN_RK3368(BIT(15), BIT(14), BIT(8), false), > > - [RK3368_PD_VIDEO] = DOMAIN_RK3368(BIT(14), BIT(13), BIT(7), false), > > - [RK3368_PD_GPU_0] = DOMAIN_RK3368(BIT(16), BIT(15), BIT(2), false), > > - [RK3368_PD_GPU_1] = DOMAIN_RK3368(BIT(17), BIT(16), BIT(2), false), > > + [RK3368_PD_PERI] = DOMAIN_RK3368("peri", BIT(13), BIT(12), BIT(6), true), > > + [RK3368_PD_VIO] = DOMAIN_RK3368("vio", BIT(15), BIT(14), BIT(8), false), > > + [RK3368_PD_VIDEO] = DOMAIN_RK3368("video", BIT(14), BIT(13), BIT(7), false), > > + [RK3368_PD_GPU_0] = DOMAIN_RK3368("gpu_0", BIT(16), BIT(15), BIT(2), false), > > + [RK3368_PD_GPU_1] = DOMAIN_RK3368("gpu_1", BIT(17), BIT(16), BIT(2), false), > > }; > > > > static const struct rockchip_domain_info rk3399_pm_domains[] = { > > - [RK3399_PD_TCPD0] = DOMAIN_RK3399(BIT(8), BIT(8), 0, false), > > - [RK3399_PD_TCPD1] = DOMAIN_RK3399(BIT(9), BIT(9), 0, false), > > - [RK3399_PD_CCI] = DOMAIN_RK3399(BIT(10), BIT(10), 0, true), > > - [RK3399_PD_CCI0] = DOMAIN_RK3399(0, 0, BIT(15), true), > > - [RK3399_PD_CCI1] = DOMAIN_RK3399(0, 0, BIT(16), true), > > - [RK3399_PD_PERILP] = DOMAIN_RK3399(BIT(11), BIT(11), BIT(1), true), > > - [RK3399_PD_PERIHP] = DOMAIN_RK3399(BIT(12), BIT(12), BIT(2), true), > > - [RK3399_PD_CENTER] = DOMAIN_RK3399(BIT(13), BIT(13), BIT(14), true), > > - [RK3399_PD_VIO] = DOMAIN_RK3399(BIT(14), BIT(14), BIT(17), false), > > - [RK3399_PD_GPU] = DOMAIN_RK3399(BIT(15), BIT(15), BIT(0), false), > > - [RK3399_PD_VCODEC] = DOMAIN_RK3399(BIT(16), BIT(16), BIT(3), false), > > - [RK3399_PD_VDU] = DOMAIN_RK3399(BIT(17), BIT(17), BIT(4), false), > > - [RK3399_PD_RGA] = DOMAIN_RK3399(BIT(18), BIT(18), BIT(5), false), > > - [RK3399_PD_IEP] = DOMAIN_RK3399(BIT(19), BIT(19), BIT(6), false), > > - [RK3399_PD_VO] = DOMAIN_RK3399(BIT(20), BIT(20), 0, false), > > - [RK3399_PD_VOPB] = DOMAIN_RK3399(0, 0, BIT(7), false), > > - [RK3399_PD_VOPL] = DOMAIN_RK3399(0, 0, BIT(8), false), > > - [RK3399_PD_ISP0] = DOMAIN_RK3399(BIT(22), BIT(22), BIT(9), false), > > - [RK3399_PD_ISP1] = DOMAIN_RK3399(BIT(23), BIT(23), BIT(10), false), > > - [RK3399_PD_HDCP] = DOMAIN_RK3399(BIT(24), BIT(24), BIT(11), false), > > - [RK3399_PD_GMAC] = DOMAIN_RK3399(BIT(25), BIT(25), BIT(23), true), > > - [RK3399_PD_EMMC] = DOMAIN_RK3399(BIT(26), BIT(26), BIT(24), true), > > - [RK3399_PD_USB3] = DOMAIN_RK3399(BIT(27), BIT(27), BIT(12), true), > > - [RK3399_PD_EDP] = DOMAIN_RK3399(BIT(28), BIT(28), BIT(22), false), > > - [RK3399_PD_GIC] = DOMAIN_RK3399(BIT(29), BIT(29), BIT(27), true), > > - [RK3399_PD_SD] = DOMAIN_RK3399(BIT(30), BIT(30), BIT(28), true), > > - [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399(BIT(31), BIT(31), BIT(29), true), > > + [RK3399_PD_TCPD0] = DOMAIN_RK3399("tcpd0", BIT(8), BIT(8), 0, false), > > + [RK3399_PD_TCPD1] = DOMAIN_RK3399("tcpd1", BIT(9), BIT(9), 0, false), > > + [RK3399_PD_CCI] = DOMAIN_RK3399("cci", BIT(10), BIT(10), 0, true), > > + [RK3399_PD_CCI0] = DOMAIN_RK3399("cci0", 0, 0, BIT(15), true), > > + [RK3399_PD_CCI1] = DOMAIN_RK3399("cci1", 0, 0, BIT(16), true), > > + [RK3399_PD_PERILP] = DOMAIN_RK3399("perilp", BIT(11), BIT(11), BIT(1), true), > > + [RK3399_PD_PERIHP] = DOMAIN_RK3399("perihp", BIT(12), BIT(12), BIT(2), true), > > + [RK3399_PD_CENTER] = DOMAIN_RK3399("center", BIT(13), BIT(13), BIT(14), true), > > + [RK3399_PD_VIO] = DOMAIN_RK3399("vio", BIT(14), BIT(14), BIT(17), false), > > + [RK3399_PD_GPU] = DOMAIN_RK3399("gpu", BIT(15), BIT(15), BIT(0), false), > > + [RK3399_PD_VCODEC] = DOMAIN_RK3399("vcodec", BIT(16), BIT(16), BIT(3), false), > > + [RK3399_PD_VDU] = DOMAIN_RK3399("vdu", BIT(17), BIT(17), BIT(4), false), > > + [RK3399_PD_RGA] = DOMAIN_RK3399("rga", BIT(18), BIT(18), BIT(5), false), > > + [RK3399_PD_IEP] = DOMAIN_RK3399("iep", BIT(19), BIT(19), BIT(6), false), > > + [RK3399_PD_VO] = DOMAIN_RK3399("vo", BIT(20), BIT(20), 0, false), > > + [RK3399_PD_VOPB] = DOMAIN_RK3399("vopb", 0, 0, BIT(7), false), > > + [RK3399_PD_VOPL] = DOMAIN_RK3399("vopl", 0, 0, BIT(8), false), > > + [RK3399_PD_ISP0] = DOMAIN_RK3399("isp0", BIT(22), BIT(22), BIT(9), false), > > + [RK3399_PD_ISP1] = DOMAIN_RK3399("isp1", BIT(23), BIT(23), BIT(10), false), > > + [RK3399_PD_HDCP] = DOMAIN_RK3399("hdcp", BIT(24), BIT(24), BIT(11), false), > > + [RK3399_PD_GMAC] = DOMAIN_RK3399("gmac", BIT(25), BIT(25), BIT(23), true), > > + [RK3399_PD_EMMC] = DOMAIN_RK3399("emmc", BIT(26), BIT(26), BIT(24), true), > > + [RK3399_PD_USB3] = DOMAIN_RK3399("usb3", BIT(27), BIT(27), BIT(12), true), > > + [RK3399_PD_EDP] = DOMAIN_RK3399("edp", BIT(28), BIT(28), BIT(22), false), > > + [RK3399_PD_GIC] = DOMAIN_RK3399("gic", BIT(29), BIT(29), BIT(27), true), > > + [RK3399_PD_SD] = DOMAIN_RK3399("sd", BIT(30), BIT(30), BIT(28), true), > > + [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true), > > }; > > > > static const struct rockchip_pmu_info px30_pmu = { > > > ^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [RESEND PATCH v5 07/11] soc: rockchip: pm-domains: Add a meaningful power domain name @ 2021-03-26 10:02 ` Heiko Stübner 0 siblings, 0 replies; 75+ messages in thread From: Heiko Stübner @ 2021-03-26 10:02 UTC (permalink / raw) To: robh+dt, Elaine Zhang Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, cl, huangtao, kever.yang, tony.xie, finley.xiao, Elaine Zhang, enric.balletbo Hi Elaine again, Am Freitag, 26. März 2021, 10:52:53 CET schrieb Heiko Stübner: > Hi Elaine, > > [also adding that answer to the resend :-) ] > > Am Freitag, 26. März 2021, 10:17:39 CET schrieb Elaine Zhang: > > Add the power domains names to the power domain info struct so we > > have meaningful name for every power domain. > > > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> > > I like that approach very much, there is one tiny comment below. > > > --- > > drivers/soc/rockchip/pm_domains.c | 217 +++++++++++++++--------------- > > 1 file changed, 112 insertions(+), 105 deletions(-) > > > > diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c > > index 54eb6cfc5d5b..d661d967079f 100644 > > --- a/drivers/soc/rockchip/pm_domains.c > > +++ b/drivers/soc/rockchip/pm_domains.c > > @@ -29,6 +29,7 @@ > > #include <dt-bindings/power/rk3399-power.h> > > > > struct rockchip_domain_info { > > + const char *name; > > int pwr_mask; > > int status_mask; > > int req_mask; > > @@ -85,8 +86,9 @@ struct rockchip_pmu { > > > > #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd) > > > > -#define DOMAIN(pwr, status, req, idle, ack, wakeup) \ > > +#define DOMAIN(_name, pwr, status, req, idle, ack, wakeup) \ > > { \ > > + .name = _name, \ > > .pwr_mask = (pwr), \ > > .status_mask = (status), \ > > .req_mask = (req), \ > > @@ -95,8 +97,9 @@ struct rockchip_pmu { > > .active_wakeup = (wakeup), \ > > } > > > > -#define DOMAIN_M(pwr, status, req, idle, ack, wakeup) \ > > +#define DOMAIN_M(_name, pwr, status, req, idle, ack, wakeup) \ > > { \ > > + .name = _name, \ > > .pwr_w_mask = (pwr) << 16, \ > > .pwr_mask = (pwr), \ > > .status_mask = (status), \ > > @@ -107,8 +110,9 @@ struct rockchip_pmu { > > .active_wakeup = wakeup, \ > > } > > > > -#define DOMAIN_RK3036(req, ack, idle, wakeup) \ > > +#define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \ > > { \ > > + .name = _name, \ > > .req_mask = (req), \ > > .req_w_mask = (req) << 16, \ > > .ack_mask = (ack), \ > > @@ -119,17 +123,17 @@ struct rockchip_pmu { > > #define DOMAIN_PX30(pwr, status, req, wakeup) \ > > DOMAIN_M(pwr, status, req, (req) << 16, req, wakeup) > > > > -#define DOMAIN_RK3288(pwr, status, req, wakeup) \ > > - DOMAIN(pwr, status, req, req, (req) << 16, wakeup) > > +#define DOMAIN_RK3288(name, pwr, status, req, wakeup) \ > > + DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup) > > > > -#define DOMAIN_RK3328(pwr, status, req, wakeup) \ > > - DOMAIN_M(pwr, pwr, req, (req) << 10, req, wakeup) > > +#define DOMAIN_RK3328(name, pwr, status, req, wakeup) \ > > + DOMAIN_M(name, pwr, pwr, req, (req) << 10, req, wakeup) > > > > -#define DOMAIN_RK3368(pwr, status, req, wakeup) \ > > - DOMAIN(pwr, status, req, (req) << 16, req, wakeup) > > +#define DOMAIN_RK3368(name, pwr, status, req, wakeup) \ > > + DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup) > > > > -#define DOMAIN_RK3399(pwr, status, req, wakeup) \ > > - DOMAIN(pwr, status, req, req, req, wakeup) > > +#define DOMAIN_RK3399(name, pwr, status, req, wakeup) \ > > + DOMAIN(name, pwr, status, req, req, req, wakeup) > > > > static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd) > > { > > @@ -490,7 +494,10 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, > > goto err_unprepare_clocks; > > } > > > > - pd->genpd.name = node->name; > > + if (!pd->info->name) > > + pd->genpd.name = node->name; > > I guess we should make that "node->full_name" perhaps? > And I guess it might be nicer to swap the cases > > if (pd->info->name) > pd->genpd.name = pd->info->name > else > pd->genpd.name = node->full_name; > > for easier readability looking a bit through kernel-sources, maybe if (pd->info->name) pd->genpd.name = pd->info->name else pd->genpd.name = kbasename(node->full_name) might be even nicer? :-) Heiko > > + else > > + pd->genpd.name = pd->info->name; > > pd->genpd.power_off = rockchip_pd_power_off; > > pd->genpd.power_on = rockchip_pd_power_on; > > pd->genpd.attach_dev = rockchip_pd_attach_dev; > > @@ -716,129 +723,129 @@ static int rockchip_pm_domain_probe(struct platform_device *pdev) > > } > > > > static const struct rockchip_domain_info px30_pm_domains[] = { > > - [PX30_PD_USB] = DOMAIN_PX30(BIT(5), BIT(5), BIT(10), false), > > - [PX30_PD_SDCARD] = DOMAIN_PX30(BIT(8), BIT(8), BIT(9), false), > > - [PX30_PD_GMAC] = DOMAIN_PX30(BIT(10), BIT(10), BIT(6), false), > > - [PX30_PD_MMC_NAND] = DOMAIN_PX30(BIT(11), BIT(11), BIT(5), false), > > - [PX30_PD_VPU] = DOMAIN_PX30(BIT(12), BIT(12), BIT(14), false), > > - [PX30_PD_VO] = DOMAIN_PX30(BIT(13), BIT(13), BIT(7), false), > > - [PX30_PD_VI] = DOMAIN_PX30(BIT(14), BIT(14), BIT(8), false), > > - [PX30_PD_GPU] = DOMAIN_PX30(BIT(15), BIT(15), BIT(2), false), > > + [PX30_PD_USB] = DOMAIN_PX30("usb", BIT(5), BIT(5), BIT(10), false), > > + [PX30_PD_SDCARD] = DOMAIN_PX30("sdcard", BIT(8), BIT(8), BIT(9), false), > > + [PX30_PD_GMAC] = DOMAIN_PX30("gmac", BIT(10), BIT(10), BIT(6), false), > > + [PX30_PD_MMC_NAND] = DOMAIN_PX30("mmc_nand", BIT(11), BIT(11), BIT(5), false), > > + [PX30_PD_VPU] = DOMAIN_PX30("vpu", BIT(12), BIT(12), BIT(14), false), > > + [PX30_PD_VO] = DOMAIN_PX30("vo", BIT(13), BIT(13), BIT(7), false), > > + [PX30_PD_VI] = DOMAIN_PX30("vi", BIT(14), BIT(14), BIT(8), false), > > + [PX30_PD_GPU] = DOMAIN_PX30("gpu", BIT(15), BIT(15), BIT(2), false), > > }; > > > > static const struct rockchip_domain_info rk3036_pm_domains[] = { > > - [RK3036_PD_MSCH] = DOMAIN_RK3036(BIT(14), BIT(23), BIT(30), true), > > - [RK3036_PD_CORE] = DOMAIN_RK3036(BIT(13), BIT(17), BIT(24), false), > > - [RK3036_PD_PERI] = DOMAIN_RK3036(BIT(12), BIT(18), BIT(25), false), > > - [RK3036_PD_VIO] = DOMAIN_RK3036(BIT(11), BIT(19), BIT(26), false), > > - [RK3036_PD_VPU] = DOMAIN_RK3036(BIT(10), BIT(20), BIT(27), false), > > - [RK3036_PD_GPU] = DOMAIN_RK3036(BIT(9), BIT(21), BIT(28), false), > > - [RK3036_PD_SYS] = DOMAIN_RK3036(BIT(8), BIT(22), BIT(29), false), > > + [RK3036_PD_MSCH] = DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true), > > + [RK3036_PD_CORE] = DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false), > > + [RK3036_PD_PERI] = DOMAIN_RK3036("peri", BIT(12), BIT(18), BIT(25), false), > > + [RK3036_PD_VIO] = DOMAIN_RK3036("vio", BIT(11), BIT(19), BIT(26), false), > > + [RK3036_PD_VPU] = DOMAIN_RK3036("vpu", BIT(10), BIT(20), BIT(27), false), > > + [RK3036_PD_GPU] = DOMAIN_RK3036("gpu", BIT(9), BIT(21), BIT(28), false), > > + [RK3036_PD_SYS] = DOMAIN_RK3036("sys", BIT(8), BIT(22), BIT(29), false), > > }; > > > > static const struct rockchip_domain_info rk3066_pm_domains[] = { > > - [RK3066_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > > - [RK3066_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > > - [RK3066_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > > - [RK3066_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > > - [RK3066_PD_CPU] = DOMAIN(0, BIT(5), BIT(1), BIT(26), BIT(31), false), > > + [RK3066_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > > + [RK3066_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > > + [RK3066_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > > + [RK3066_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > > + [RK3066_PD_CPU] = DOMAIN("cpu", 0, BIT(5), BIT(1), BIT(26), BIT(31), false), > > }; > > > > static const struct rockchip_domain_info rk3128_pm_domains[] = { > > - [RK3128_PD_CORE] = DOMAIN_RK3288(BIT(0), BIT(0), BIT(4), false), > > - [RK3128_PD_MSCH] = DOMAIN_RK3288(0, 0, BIT(6), true), > > - [RK3128_PD_VIO] = DOMAIN_RK3288(BIT(3), BIT(3), BIT(2), false), > > - [RK3128_PD_VIDEO] = DOMAIN_RK3288(BIT(2), BIT(2), BIT(1), false), > > - [RK3128_PD_GPU] = DOMAIN_RK3288(BIT(1), BIT(1), BIT(3), false), > > + [RK3128_PD_CORE] = DOMAIN_RK3288("core", BIT(0), BIT(0), BIT(4), false), > > + [RK3128_PD_MSCH] = DOMAIN_RK3288("msch", 0, 0, BIT(6), true), > > + [RK3128_PD_VIO] = DOMAIN_RK3288("vio", BIT(3), BIT(3), BIT(2), false), > > + [RK3128_PD_VIDEO] = DOMAIN_RK3288("video", BIT(2), BIT(2), BIT(1), false), > > + [RK3128_PD_GPU] = DOMAIN_RK3288("gpu", BIT(1), BIT(1), BIT(3), false), > > }; > > > > static const struct rockchip_domain_info rk3188_pm_domains[] = { > > - [RK3188_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > > - [RK3188_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > > - [RK3188_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > > - [RK3188_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > > - [RK3188_PD_CPU] = DOMAIN(BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false), > > + [RK3188_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), > > + [RK3188_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), > > + [RK3188_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), > > + [RK3188_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), > > + [RK3188_PD_CPU] = DOMAIN("cpu", BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false), > > }; > > > > static const struct rockchip_domain_info rk3228_pm_domains[] = { > > - [RK3228_PD_CORE] = DOMAIN_RK3036(BIT(0), BIT(0), BIT(16), true), > > - [RK3228_PD_MSCH] = DOMAIN_RK3036(BIT(1), BIT(1), BIT(17), true), > > - [RK3228_PD_BUS] = DOMAIN_RK3036(BIT(2), BIT(2), BIT(18), true), > > - [RK3228_PD_SYS] = DOMAIN_RK3036(BIT(3), BIT(3), BIT(19), true), > > - [RK3228_PD_VIO] = DOMAIN_RK3036(BIT(4), BIT(4), BIT(20), false), > > - [RK3228_PD_VOP] = DOMAIN_RK3036(BIT(5), BIT(5), BIT(21), false), > > - [RK3228_PD_VPU] = DOMAIN_RK3036(BIT(6), BIT(6), BIT(22), false), > > - [RK3228_PD_RKVDEC] = DOMAIN_RK3036(BIT(7), BIT(7), BIT(23), false), > > - [RK3228_PD_GPU] = DOMAIN_RK3036(BIT(8), BIT(8), BIT(24), false), > > - [RK3228_PD_PERI] = DOMAIN_RK3036(BIT(9), BIT(9), BIT(25), true), > > - [RK3228_PD_GMAC] = DOMAIN_RK3036(BIT(10), BIT(10), BIT(26), false), > > + [RK3228_PD_CORE] = DOMAIN_RK3036("core", BIT(0), BIT(0), BIT(16), true), > > + [RK3228_PD_MSCH] = DOMAIN_RK3036("msch", BIT(1), BIT(1), BIT(17), true), > > + [RK3228_PD_BUS] = DOMAIN_RK3036("bus", BIT(2), BIT(2), BIT(18), true), > > + [RK3228_PD_SYS] = DOMAIN_RK3036("sys", BIT(3), BIT(3), BIT(19), true), > > + [RK3228_PD_VIO] = DOMAIN_RK3036("vio", BIT(4), BIT(4), BIT(20), false), > > + [RK3228_PD_VOP] = DOMAIN_RK3036("vop", BIT(5), BIT(5), BIT(21), false), > > + [RK3228_PD_VPU] = DOMAIN_RK3036("vpu", BIT(6), BIT(6), BIT(22), false), > > + [RK3228_PD_RKVDEC] = DOMAIN_RK3036("vdec", BIT(7), BIT(7), BIT(23), false), > > + [RK3228_PD_GPU] = DOMAIN_RK3036("gpu", BIT(8), BIT(8), BIT(24), false), > > + [RK3228_PD_PERI] = DOMAIN_RK3036("peri", BIT(9), BIT(9), BIT(25), true), > > + [RK3228_PD_GMAC] = DOMAIN_RK3036("gmac", BIT(10), BIT(10), BIT(26), false), > > }; > > > > static const struct rockchip_domain_info rk3288_pm_domains[] = { > > - [RK3288_PD_VIO] = DOMAIN_RK3288(BIT(7), BIT(7), BIT(4), false), > > - [RK3288_PD_HEVC] = DOMAIN_RK3288(BIT(14), BIT(10), BIT(9), false), > > - [RK3288_PD_VIDEO] = DOMAIN_RK3288(BIT(8), BIT(8), BIT(3), false), > > - [RK3288_PD_GPU] = DOMAIN_RK3288(BIT(9), BIT(9), BIT(2), false), > > + [RK3288_PD_VIO] = DOMAIN_RK3288("vio", BIT(7), BIT(7), BIT(4), false), > > + [RK3288_PD_HEVC] = DOMAIN_RK3288("hevc", BIT(14), BIT(10), BIT(9), false), > > + [RK3288_PD_VIDEO] = DOMAIN_RK3288("video", BIT(8), BIT(8), BIT(3), false), > > + [RK3288_PD_GPU] = DOMAIN_RK3288("gpu", BIT(9), BIT(9), BIT(2), false), > > }; > > > > static const struct rockchip_domain_info rk3328_pm_domains[] = { > > - [RK3328_PD_CORE] = DOMAIN_RK3328(0, BIT(0), BIT(0), false), > > - [RK3328_PD_GPU] = DOMAIN_RK3328(0, BIT(1), BIT(1), false), > > - [RK3328_PD_BUS] = DOMAIN_RK3328(0, BIT(2), BIT(2), true), > > - [RK3328_PD_MSCH] = DOMAIN_RK3328(0, BIT(3), BIT(3), true), > > - [RK3328_PD_PERI] = DOMAIN_RK3328(0, BIT(4), BIT(4), true), > > - [RK3328_PD_VIDEO] = DOMAIN_RK3328(0, BIT(5), BIT(5), false), > > - [RK3328_PD_HEVC] = DOMAIN_RK3328(0, BIT(6), BIT(6), false), > > - [RK3328_PD_VIO] = DOMAIN_RK3328(0, BIT(8), BIT(8), false), > > - [RK3328_PD_VPU] = DOMAIN_RK3328(0, BIT(9), BIT(9), false), > > + [RK3328_PD_CORE] = DOMAIN_RK3328("core", 0, BIT(0), BIT(0), false), > > + [RK3328_PD_GPU] = DOMAIN_RK3328("gpu", 0, BIT(1), BIT(1), false), > > + [RK3328_PD_BUS] = DOMAIN_RK3328("bus", 0, BIT(2), BIT(2), true), > > + [RK3328_PD_MSCH] = DOMAIN_RK3328("msch", 0, BIT(3), BIT(3), true), > > + [RK3328_PD_PERI] = DOMAIN_RK3328("peri", 0, BIT(4), BIT(4), true), > > + [RK3328_PD_VIDEO] = DOMAIN_RK3328("video", 0, BIT(5), BIT(5), false), > > + [RK3328_PD_HEVC] = DOMAIN_RK3328("hevc", 0, BIT(6), BIT(6), false), > > + [RK3328_PD_VIO] = DOMAIN_RK3328("vio", 0, BIT(8), BIT(8), false), > > + [RK3328_PD_VPU] = DOMAIN_RK3328("vpu", 0, BIT(9), BIT(9), false), > > }; > > > > static const struct rockchip_domain_info rk3366_pm_domains[] = { > > - [RK3366_PD_PERI] = DOMAIN_RK3368(BIT(10), BIT(10), BIT(6), true), > > - [RK3366_PD_VIO] = DOMAIN_RK3368(BIT(14), BIT(14), BIT(8), false), > > - [RK3366_PD_VIDEO] = DOMAIN_RK3368(BIT(13), BIT(13), BIT(7), false), > > - [RK3366_PD_RKVDEC] = DOMAIN_RK3368(BIT(11), BIT(11), BIT(7), false), > > - [RK3366_PD_WIFIBT] = DOMAIN_RK3368(BIT(8), BIT(8), BIT(9), false), > > - [RK3366_PD_VPU] = DOMAIN_RK3368(BIT(12), BIT(12), BIT(7), false), > > - [RK3366_PD_GPU] = DOMAIN_RK3368(BIT(15), BIT(15), BIT(2), false), > > + [RK3366_PD_PERI] = DOMAIN_RK3368("peri", BIT(10), BIT(10), BIT(6), true), > > + [RK3366_PD_VIO] = DOMAIN_RK3368("vio", BIT(14), BIT(14), BIT(8), false), > > + [RK3366_PD_VIDEO] = DOMAIN_RK3368("video", BIT(13), BIT(13), BIT(7), false), > > + [RK3366_PD_RKVDEC] = DOMAIN_RK3368("vdec", BIT(11), BIT(11), BIT(7), false), > > + [RK3366_PD_WIFIBT] = DOMAIN_RK3368("wifibt", BIT(8), BIT(8), BIT(9), false), > > + [RK3366_PD_VPU] = DOMAIN_RK3368("vpu", BIT(12), BIT(12), BIT(7), false), > > + [RK3366_PD_GPU] = DOMAIN_RK3368("gpu", BIT(15), BIT(15), BIT(2), false), > > }; > > > > static const struct rockchip_domain_info rk3368_pm_domains[] = { > > - [RK3368_PD_PERI] = DOMAIN_RK3368(BIT(13), BIT(12), BIT(6), true), > > - [RK3368_PD_VIO] = DOMAIN_RK3368(BIT(15), BIT(14), BIT(8), false), > > - [RK3368_PD_VIDEO] = DOMAIN_RK3368(BIT(14), BIT(13), BIT(7), false), > > - [RK3368_PD_GPU_0] = DOMAIN_RK3368(BIT(16), BIT(15), BIT(2), false), > > - [RK3368_PD_GPU_1] = DOMAIN_RK3368(BIT(17), BIT(16), BIT(2), false), > > + [RK3368_PD_PERI] = DOMAIN_RK3368("peri", BIT(13), BIT(12), BIT(6), true), > > + [RK3368_PD_VIO] = DOMAIN_RK3368("vio", BIT(15), BIT(14), BIT(8), false), > > + [RK3368_PD_VIDEO] = DOMAIN_RK3368("video", BIT(14), BIT(13), BIT(7), false), > > + [RK3368_PD_GPU_0] = DOMAIN_RK3368("gpu_0", BIT(16), BIT(15), BIT(2), false), > > + [RK3368_PD_GPU_1] = DOMAIN_RK3368("gpu_1", BIT(17), BIT(16), BIT(2), false), > > }; > > > > static const struct rockchip_domain_info rk3399_pm_domains[] = { > > - [RK3399_PD_TCPD0] = DOMAIN_RK3399(BIT(8), BIT(8), 0, false), > > - [RK3399_PD_TCPD1] = DOMAIN_RK3399(BIT(9), BIT(9), 0, false), > > - [RK3399_PD_CCI] = DOMAIN_RK3399(BIT(10), BIT(10), 0, true), > > - [RK3399_PD_CCI0] = DOMAIN_RK3399(0, 0, BIT(15), true), > > - [RK3399_PD_CCI1] = DOMAIN_RK3399(0, 0, BIT(16), true), > > - [RK3399_PD_PERILP] = DOMAIN_RK3399(BIT(11), BIT(11), BIT(1), true), > > - [RK3399_PD_PERIHP] = DOMAIN_RK3399(BIT(12), BIT(12), BIT(2), true), > > - [RK3399_PD_CENTER] = DOMAIN_RK3399(BIT(13), BIT(13), BIT(14), true), > > - [RK3399_PD_VIO] = DOMAIN_RK3399(BIT(14), BIT(14), BIT(17), false), > > - [RK3399_PD_GPU] = DOMAIN_RK3399(BIT(15), BIT(15), BIT(0), false), > > - [RK3399_PD_VCODEC] = DOMAIN_RK3399(BIT(16), BIT(16), BIT(3), false), > > - [RK3399_PD_VDU] = DOMAIN_RK3399(BIT(17), BIT(17), BIT(4), false), > > - [RK3399_PD_RGA] = DOMAIN_RK3399(BIT(18), BIT(18), BIT(5), false), > > - [RK3399_PD_IEP] = DOMAIN_RK3399(BIT(19), BIT(19), BIT(6), false), > > - [RK3399_PD_VO] = DOMAIN_RK3399(BIT(20), BIT(20), 0, false), > > - [RK3399_PD_VOPB] = DOMAIN_RK3399(0, 0, BIT(7), false), > > - [RK3399_PD_VOPL] = DOMAIN_RK3399(0, 0, BIT(8), false), > > - [RK3399_PD_ISP0] = DOMAIN_RK3399(BIT(22), BIT(22), BIT(9), false), > > - [RK3399_PD_ISP1] = DOMAIN_RK3399(BIT(23), BIT(23), BIT(10), false), > > - [RK3399_PD_HDCP] = DOMAIN_RK3399(BIT(24), BIT(24), BIT(11), false), > > - [RK3399_PD_GMAC] = DOMAIN_RK3399(BIT(25), BIT(25), BIT(23), true), > > - [RK3399_PD_EMMC] = DOMAIN_RK3399(BIT(26), BIT(26), BIT(24), true), > > - [RK3399_PD_USB3] = DOMAIN_RK3399(BIT(27), BIT(27), BIT(12), true), > > - [RK3399_PD_EDP] = DOMAIN_RK3399(BIT(28), BIT(28), BIT(22), false), > > - [RK3399_PD_GIC] = DOMAIN_RK3399(BIT(29), BIT(29), BIT(27), true), > > - [RK3399_PD_SD] = DOMAIN_RK3399(BIT(30), BIT(30), BIT(28), true), > > - [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399(BIT(31), BIT(31), BIT(29), true), > > + [RK3399_PD_TCPD0] = DOMAIN_RK3399("tcpd0", BIT(8), BIT(8), 0, false), > > + [RK3399_PD_TCPD1] = DOMAIN_RK3399("tcpd1", BIT(9), BIT(9), 0, false), > > + [RK3399_PD_CCI] = DOMAIN_RK3399("cci", BIT(10), BIT(10), 0, true), > > + [RK3399_PD_CCI0] = DOMAIN_RK3399("cci0", 0, 0, BIT(15), true), > > + [RK3399_PD_CCI1] = DOMAIN_RK3399("cci1", 0, 0, BIT(16), true), > > + [RK3399_PD_PERILP] = DOMAIN_RK3399("perilp", BIT(11), BIT(11), BIT(1), true), > > + [RK3399_PD_PERIHP] = DOMAIN_RK3399("perihp", BIT(12), BIT(12), BIT(2), true), > > + [RK3399_PD_CENTER] = DOMAIN_RK3399("center", BIT(13), BIT(13), BIT(14), true), > > + [RK3399_PD_VIO] = DOMAIN_RK3399("vio", BIT(14), BIT(14), BIT(17), false), > > + [RK3399_PD_GPU] = DOMAIN_RK3399("gpu", BIT(15), BIT(15), BIT(0), false), > > + [RK3399_PD_VCODEC] = DOMAIN_RK3399("vcodec", BIT(16), BIT(16), BIT(3), false), > > + [RK3399_PD_VDU] = DOMAIN_RK3399("vdu", BIT(17), BIT(17), BIT(4), false), > > + [RK3399_PD_RGA] = DOMAIN_RK3399("rga", BIT(18), BIT(18), BIT(5), false), > > + [RK3399_PD_IEP] = DOMAIN_RK3399("iep", BIT(19), BIT(19), BIT(6), false), > > + [RK3399_PD_VO] = DOMAIN_RK3399("vo", BIT(20), BIT(20), 0, false), > > + [RK3399_PD_VOPB] = DOMAIN_RK3399("vopb", 0, 0, BIT(7), false), > > + [RK3399_PD_VOPL] = DOMAIN_RK3399("vopl", 0, 0, BIT(8), false), > > + [RK3399_PD_ISP0] = DOMAIN_RK3399("isp0", BIT(22), BIT(22), BIT(9), false), > > + [RK3399_PD_ISP1] = DOMAIN_RK3399("isp1", BIT(23), BIT(23), BIT(10), false), > > + [RK3399_PD_HDCP] = DOMAIN_RK3399("hdcp", BIT(24), BIT(24), BIT(11), false), > > + [RK3399_PD_GMAC] = DOMAIN_RK3399("gmac", BIT(25), BIT(25), BIT(23), true), > > + [RK3399_PD_EMMC] = DOMAIN_RK3399("emmc", BIT(26), BIT(26), BIT(24), true), > > + [RK3399_PD_USB3] = DOMAIN_RK3399("usb3", BIT(27), BIT(27), BIT(12), true), > > + [RK3399_PD_EDP] = DOMAIN_RK3399("edp", BIT(28), BIT(28), BIT(22), false), > > + [RK3399_PD_GIC] = DOMAIN_RK3399("gic", BIT(29), BIT(29), BIT(27), true), > > + [RK3399_PD_SD] = DOMAIN_RK3399("sd", BIT(30), BIT(30), BIT(28), true), > > + [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true), > > }; > > > > static const struct rockchip_pmu_info px30_pmu = { > > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 75+ messages in thread
end of thread, other threads:[~2021-03-26 10:04 UTC | newest] Thread overview: 75+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2021-03-26 9:15 [PATCH v5 00/11] soc: rockchip: power-domain: add rk3568 powerdomains Elaine Zhang 2021-03-26 9:15 ` Elaine Zhang 2021-03-26 9:15 ` Elaine Zhang 2021-03-26 9:15 ` [PATCH v5 01/11] arm: dts: rockchip: Fix power-controller node names for rk3066a Elaine Zhang 2021-03-26 9:15 ` Elaine Zhang 2021-03-26 9:15 ` Elaine Zhang 2021-03-26 9:40 ` Enric Balletbo Serra 2021-03-26 9:40 ` Enric Balletbo Serra 2021-03-26 9:40 ` Enric Balletbo Serra 2021-03-26 9:15 ` [PATCH v5 02/11] arm: dts: rockchip: Fix power-controller node names for rk3188 Elaine Zhang 2021-03-26 9:15 ` Elaine Zhang 2021-03-26 9:15 ` Elaine Zhang 2021-03-26 9:40 ` Enric Balletbo Serra 2021-03-26 9:40 ` Enric Balletbo Serra 2021-03-26 9:40 ` Enric Balletbo Serra 2021-03-26 9:15 ` [PATCH v5 03/11] arm: dts: rockchip: Fix power-controller node names for rk3288 Elaine Zhang 2021-03-26 9:15 ` Elaine Zhang 2021-03-26 9:15 ` Elaine Zhang 2021-03-26 9:40 ` Enric Balletbo Serra 2021-03-26 9:40 ` Enric Balletbo Serra 2021-03-26 9:40 ` Enric Balletbo Serra 2021-03-26 9:15 ` [PATCH v5 04/11] arm64: dts: rockchip: Fix power-controller node names for px30 Elaine Zhang 2021-03-26 9:15 ` Elaine Zhang 2021-03-26 9:15 ` Elaine Zhang 2021-03-26 9:41 ` Enric Balletbo Serra 2021-03-26 9:41 ` Enric Balletbo Serra 2021-03-26 9:41 ` Enric Balletbo Serra 2021-03-26 9:17 ` [PATCH v5 05/11] arm64: dts: rockchip: Fix power-controller node names for rk3328 Elaine Zhang 2021-03-26 9:17 ` Elaine Zhang 2021-03-26 9:17 ` Elaine Zhang 2021-03-26 9:41 ` Enric Balletbo Serra 2021-03-26 9:41 ` Enric Balletbo Serra 2021-03-26 9:41 ` Enric Balletbo Serra 2021-03-26 9:17 ` [PATCH v5 06/11] arm64: dts: rockchip: Fix power-controller node names for rk3399 Elaine Zhang 2021-03-26 9:17 ` Elaine Zhang 2021-03-26 9:17 ` Elaine Zhang 2021-03-26 9:42 ` Enric Balletbo Serra 2021-03-26 9:42 ` Enric Balletbo Serra 2021-03-26 9:42 ` Enric Balletbo Serra 2021-03-26 9:17 ` [PATCH v5 07/11] soc: rockchip: pm-domains: Add a meaningful power domain name Elaine Zhang 2021-03-26 9:17 ` Elaine Zhang 2021-03-26 9:17 ` Elaine Zhang 2021-03-26 9:49 ` Heiko Stübner 2021-03-26 9:49 ` Heiko Stübner 2021-03-26 9:49 ` Heiko Stübner 2021-03-26 9:17 ` [PATCH v5 08/11] dt-bindings: add power-domain header for RK3568 SoCs Elaine Zhang 2021-03-26 9:17 ` Elaine Zhang 2021-03-26 9:17 ` Elaine Zhang 2021-03-26 9:52 ` Enric Balletbo Serra 2021-03-26 9:52 ` Enric Balletbo Serra 2021-03-26 9:52 ` Enric Balletbo Serra 2021-03-26 9:18 ` [PATCH v5 09/11] dt-bindings: power: rockchip: Convert to json-schema Elaine Zhang 2021-03-26 9:18 ` Elaine Zhang 2021-03-26 9:18 ` Elaine Zhang 2021-03-26 9:51 ` Heiko Stübner 2021-03-26 9:51 ` Heiko Stübner 2021-03-26 9:51 ` Heiko Stübner 2021-03-26 9:18 ` [PATCH v5 10/11] dt-bindings: power: rockchip: Add bindings for RK3568 Soc Elaine Zhang 2021-03-26 9:18 ` Elaine Zhang 2021-03-26 9:18 ` Elaine Zhang 2021-03-26 9:51 ` Enric Balletbo Serra 2021-03-26 9:51 ` Enric Balletbo Serra 2021-03-26 9:51 ` Enric Balletbo Serra 2021-03-26 9:18 ` [PATCH v5 11/11] soc: rockchip: power-domain: add rk3568 powerdomains Elaine Zhang 2021-03-26 9:18 ` Elaine Zhang 2021-03-26 9:18 ` Elaine Zhang 2021-03-26 9:37 ` [RESEND PATCH v5 07/11] soc: rockchip: pm-domains: Add a meaningful power domain name Elaine Zhang 2021-03-26 9:37 ` Elaine Zhang 2021-03-26 9:37 ` Elaine Zhang 2021-03-26 9:52 ` Heiko Stübner 2021-03-26 9:52 ` Heiko Stübner 2021-03-26 9:52 ` Heiko Stübner 2021-03-26 10:02 ` Heiko Stübner 2021-03-26 10:02 ` Heiko Stübner 2021-03-26 10:02 ` Heiko Stübner
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