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From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Simon Horman <horms@verge.net.au>,
	Magnus Damm <magnus.damm@gmail.com>,
	Yoshinori Sato <ysato@users.sourceforge.jp>,
	linux-serial@vger.kernel.org, linux-sh@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 14/25] serial: sh-sci: Add BRG register definitions
Date: Thu, 19 Nov 2015 20:45:31 +0000	[thread overview]
Message-ID: <1866546.6tqcoO3C0e@avalon> (raw)
In-Reply-To: <1447958344-836-15-git-send-email-geert+renesas@glider.be>

Hi Geert,

Thank you for the patch.

On Thursday 19 November 2015 19:38:53 Geert Uytterhoeven wrote:
> Add register definitions for the Baud Rate Generator for External Clock
> (BRG), as found in some SCIF and in HSCIF, including a new regtype for
> the "SH-4(A)"-derived SCIF variant with BRG.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
>  drivers/tty/serial/sh-sci.c | 46 ++++++++++++++++++++++++++++++++++++++++++
>  drivers/tty/serial/sh-sci.h |  5 +++++
>  include/linux/serial_sci.h  |  1 +
>  3 files changed, 52 insertions(+)
> 
> diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
> index d82735dd62ae38d8..76738c9918885764 100644
> --- a/drivers/tty/serial/sh-sci.c
> +++ b/drivers/tty/serial/sh-sci.c
> @@ -161,6 +161,8 @@ static const struct plat_sci_reg
> sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { [HSSRR]		= 
sci_reg_invalid,
>  		[SCPCR]		= sci_reg_invalid,
>  		[SCPDR]		= sci_reg_invalid,
> +		[SCDL]		= sci_reg_invalid,
> +		[SCCKS]		= sci_reg_invalid,
>  	},
> 
>  	/*
> @@ -183,6 +185,8 @@ static const struct plat_sci_reg
> sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { [HSSRR]		= 
sci_reg_invalid,
>  		[SCPCR]		= sci_reg_invalid,
>  		[SCPDR]		= sci_reg_invalid,
> +		[SCDL]		= sci_reg_invalid,
> +		[SCCKS]		= sci_reg_invalid,
>  	},
> 
>  	/*
> @@ -204,6 +208,8 @@ static const struct plat_sci_reg
> sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { [HSSRR]		= 
sci_reg_invalid,
>  		[SCPCR]		= { 0x30, 16 },
>  		[SCPDR]		= { 0x34, 16 },
> +		[SCDL]		= sci_reg_invalid,
> +		[SCCKS]		= sci_reg_invalid,
>  	},
> 
>  	/*
> @@ -225,6 +231,8 @@ static const struct plat_sci_reg
> sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { [HSSRR]		= 
sci_reg_invalid,
>  		[SCPCR]		= { 0x30, 16 },
>  		[SCPDR]		= { 0x34, 16 },
> +		[SCDL]		= sci_reg_invalid,
> +		[SCCKS]		= sci_reg_invalid,
>  	},
> 
>  	/*
> @@ -247,6 +255,8 @@ static const struct plat_sci_reg
> sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { [HSSRR]		= 
sci_reg_invalid,
>  		[SCPCR]		= sci_reg_invalid,
>  		[SCPDR]		= sci_reg_invalid,
> +		[SCDL]		= sci_reg_invalid,
> +		[SCCKS]		= sci_reg_invalid,
>  	},
> 
>  	/*
> @@ -268,6 +278,8 @@ static const struct plat_sci_reg
> sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { [HSSRR]		= 
sci_reg_invalid,
>  		[SCPCR]		= sci_reg_invalid,
>  		[SCPDR]		= sci_reg_invalid,
> +		[SCDL]		= sci_reg_invalid,
> +		[SCCKS]		= sci_reg_invalid,
>  	},
> 
>  	/*
> @@ -289,6 +301,32 @@ static const struct plat_sci_reg
> sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { [HSSRR]		= 
sci_reg_invalid,
>  		[SCPCR]		= sci_reg_invalid,
>  		[SCPDR]		= sci_reg_invalid,
> +		[SCDL]		= sci_reg_invalid,
> +		[SCCKS]		= sci_reg_invalid,
> +	},
> +
> +	/*
> +	 * Common SCIF definitions for ports with a Baud Rate Generator for
> +	 * External Clock (BRG).
> +	 */
> +	[SCIx_SH4_SCIF_BRG_REGTYPE] = {
> +		[SCSMR]		= { 0x00, 16 },
> +		[SCBRR]		= { 0x04,  8 },
> +		[SCSCR]		= { 0x08, 16 },
> +		[SCxTDR]	= { 0x0c,  8 },
> +		[SCxSR]		= { 0x10, 16 },
> +		[SCxRDR]	= { 0x14,  8 },
> +		[SCFCR]		= { 0x18, 16 },
> +		[SCFDR]		= { 0x1c, 16 },
> +		[SCTFDR]	= sci_reg_invalid,
> +		[SCRFDR]	= sci_reg_invalid,
> +		[SCSPTR]	= { 0x20, 16 },
> +		[SCLSR]		= { 0x24, 16 },
> +		[HSSRR]		= sci_reg_invalid,
> +		[SCPCR]		= sci_reg_invalid,
> +		[SCPDR]		= sci_reg_invalid,
> +		[SCDL]		= { 0x30, 16 },
> +		[SCCKS]		= { 0x34, 16 },
>  	},
> 
>  	/*
> @@ -310,6 +348,8 @@ static const struct plat_sci_reg
> sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { [HSSRR]		= { 0x40, 16 },
>  		[SCPCR]		= sci_reg_invalid,
>  		[SCPDR]		= sci_reg_invalid,
> +		[SCDL]		= { 0x30, 16 },
> +		[SCCKS]		= { 0x34, 16 },
>  	},
> 
>  	/*
> @@ -332,6 +372,8 @@ static const struct plat_sci_reg
> sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { [HSSRR]		= 
sci_reg_invalid,
>  		[SCPCR]		= sci_reg_invalid,
>  		[SCPDR]		= sci_reg_invalid,
> +		[SCDL]		= sci_reg_invalid,
> +		[SCCKS]		= sci_reg_invalid,
>  	},
> 
>  	/*
> @@ -354,6 +396,8 @@ static const struct plat_sci_reg
> sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { [HSSRR]		= 
sci_reg_invalid,
>  		[SCPCR]		= sci_reg_invalid,
>  		[SCPDR]		= sci_reg_invalid,
> +		[SCDL]		= sci_reg_invalid,
> +		[SCCKS]		= sci_reg_invalid,
>  	},
> 
>  	/*
> @@ -376,6 +420,8 @@ static const struct plat_sci_reg
> sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { [HSSRR]		= 
sci_reg_invalid,
>  		[SCPCR]		= sci_reg_invalid,
>  		[SCPDR]		= sci_reg_invalid,
> +		[SCDL]		= sci_reg_invalid,
> +		[SCCKS]		= sci_reg_invalid,
>  	},
>  };
> 
> diff --git a/drivers/tty/serial/sh-sci.h b/drivers/tty/serial/sh-sci.h
> index bf69bbdcc1f9aa39..54994f0bfafdbe12 100644
> --- a/drivers/tty/serial/sh-sci.h
> +++ b/drivers/tty/serial/sh-sci.h
> @@ -27,6 +27,8 @@ enum {
>  	HSSRR,				/* Sampling Rate Register */
>  	SCPCR,				/* Serial Port Control Register */
>  	SCPDR,				/* Serial Port Data Register */
> +	SCDL,				/* BRG Frequency Division Register */
> +	SCCKS,				/* BRG Clock Select Register */
> 
>  	SCIx_NR_REGS,
>  };
> @@ -109,6 +111,9 @@ enum {
>  #define SCPDR_RTSD	BIT(4)	/* Serial Port RTS Output Pin Data */
>  #define SCPDR_CTSD	BIT(3)	/* Serial Port CTS Input Pin Data */
> 
> +/* BRG Clock Select Register (Some SCIF and HSCIF) */
> +#define SCCKS_CKS	BIT(15)	/* Select SCK (1) or SC_CLK (0) */

This is slightly confusing. SC_CLK is defined as the external clock selectable 
between the bus clock and SCIF_CLK. The CKS bit selects the output of the baud 
rate generator for external clock as being the divided SC_CLK or the undivided 
(H)SCK. The comment, and I know it comes from the datasheet, seems to imply 
that the bit selects the input of the BRG-EC. Speaking of which it would be 
good to have a comment somewhere in the code to explain that we have two 
chained BRGs.

> +#define SCCKS_XIN	BIT(14)	/* SC_CLK uses bus clock (1) or SCIF_CLK (0) 
*/
> 
>  #define SCxSR_TEND(port)	(((port)->type = PORT_SCI) ? SCI_TEND   :
> SCIF_TEND) #define SCxSR_RDxF(port)	(((port)->type = PORT_SCI) ? 
SCI_RDRF 
>  : SCIF_RDF) diff --git a/include/linux/serial_sci.h
> b/include/linux/serial_sci.h index 7c536ac5be05d3aa..9f2bfd0557429ac3
> 100644
> --- a/include/linux/serial_sci.h
> +++ b/include/linux/serial_sci.h
> @@ -32,6 +32,7 @@ enum {
>  	SCIx_SH2_SCIF_FIFODATA_REGTYPE,
>  	SCIx_SH3_SCIF_REGTYPE,
>  	SCIx_SH4_SCIF_REGTYPE,
> +	SCIx_SH4_SCIF_BRG_REGTYPE,
>  	SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
>  	SCIx_SH4_SCIF_FIFODATA_REGTYPE,
>  	SCIx_SH7705_SCIF_REGTYPE,

-- 
Regards,

Laurent Pinchart


WARNING: multiple messages have this Message-ID (diff)
From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Simon Horman <horms@verge.net.au>,
	Magnus Damm <magnus.damm@gmail.com>,
	Yoshinori Sato <ysato@users.sourceforge.jp>,
	linux-serial@vger.kernel.org, linux-sh@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 14/25] serial: sh-sci: Add BRG register definitions
Date: Thu, 19 Nov 2015 22:45:31 +0200	[thread overview]
Message-ID: <1866546.6tqcoO3C0e@avalon> (raw)
In-Reply-To: <1447958344-836-15-git-send-email-geert+renesas@glider.be>

Hi Geert,

Thank you for the patch.

On Thursday 19 November 2015 19:38:53 Geert Uytterhoeven wrote:
> Add register definitions for the Baud Rate Generator for External Clock
> (BRG), as found in some SCIF and in HSCIF, including a new regtype for
> the "SH-4(A)"-derived SCIF variant with BRG.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
>  drivers/tty/serial/sh-sci.c | 46 ++++++++++++++++++++++++++++++++++++++++++
>  drivers/tty/serial/sh-sci.h |  5 +++++
>  include/linux/serial_sci.h  |  1 +
>  3 files changed, 52 insertions(+)
> 
> diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
> index d82735dd62ae38d8..76738c9918885764 100644
> --- a/drivers/tty/serial/sh-sci.c
> +++ b/drivers/tty/serial/sh-sci.c
> @@ -161,6 +161,8 @@ static const struct plat_sci_reg
> sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { [HSSRR]		= 
sci_reg_invalid,
>  		[SCPCR]		= sci_reg_invalid,
>  		[SCPDR]		= sci_reg_invalid,
> +		[SCDL]		= sci_reg_invalid,
> +		[SCCKS]		= sci_reg_invalid,
>  	},
> 
>  	/*
> @@ -183,6 +185,8 @@ static const struct plat_sci_reg
> sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { [HSSRR]		= 
sci_reg_invalid,
>  		[SCPCR]		= sci_reg_invalid,
>  		[SCPDR]		= sci_reg_invalid,
> +		[SCDL]		= sci_reg_invalid,
> +		[SCCKS]		= sci_reg_invalid,
>  	},
> 
>  	/*
> @@ -204,6 +208,8 @@ static const struct plat_sci_reg
> sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { [HSSRR]		= 
sci_reg_invalid,
>  		[SCPCR]		= { 0x30, 16 },
>  		[SCPDR]		= { 0x34, 16 },
> +		[SCDL]		= sci_reg_invalid,
> +		[SCCKS]		= sci_reg_invalid,
>  	},
> 
>  	/*
> @@ -225,6 +231,8 @@ static const struct plat_sci_reg
> sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { [HSSRR]		= 
sci_reg_invalid,
>  		[SCPCR]		= { 0x30, 16 },
>  		[SCPDR]		= { 0x34, 16 },
> +		[SCDL]		= sci_reg_invalid,
> +		[SCCKS]		= sci_reg_invalid,
>  	},
> 
>  	/*
> @@ -247,6 +255,8 @@ static const struct plat_sci_reg
> sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { [HSSRR]		= 
sci_reg_invalid,
>  		[SCPCR]		= sci_reg_invalid,
>  		[SCPDR]		= sci_reg_invalid,
> +		[SCDL]		= sci_reg_invalid,
> +		[SCCKS]		= sci_reg_invalid,
>  	},
> 
>  	/*
> @@ -268,6 +278,8 @@ static const struct plat_sci_reg
> sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { [HSSRR]		= 
sci_reg_invalid,
>  		[SCPCR]		= sci_reg_invalid,
>  		[SCPDR]		= sci_reg_invalid,
> +		[SCDL]		= sci_reg_invalid,
> +		[SCCKS]		= sci_reg_invalid,
>  	},
> 
>  	/*
> @@ -289,6 +301,32 @@ static const struct plat_sci_reg
> sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { [HSSRR]		= 
sci_reg_invalid,
>  		[SCPCR]		= sci_reg_invalid,
>  		[SCPDR]		= sci_reg_invalid,
> +		[SCDL]		= sci_reg_invalid,
> +		[SCCKS]		= sci_reg_invalid,
> +	},
> +
> +	/*
> +	 * Common SCIF definitions for ports with a Baud Rate Generator for
> +	 * External Clock (BRG).
> +	 */
> +	[SCIx_SH4_SCIF_BRG_REGTYPE] = {
> +		[SCSMR]		= { 0x00, 16 },
> +		[SCBRR]		= { 0x04,  8 },
> +		[SCSCR]		= { 0x08, 16 },
> +		[SCxTDR]	= { 0x0c,  8 },
> +		[SCxSR]		= { 0x10, 16 },
> +		[SCxRDR]	= { 0x14,  8 },
> +		[SCFCR]		= { 0x18, 16 },
> +		[SCFDR]		= { 0x1c, 16 },
> +		[SCTFDR]	= sci_reg_invalid,
> +		[SCRFDR]	= sci_reg_invalid,
> +		[SCSPTR]	= { 0x20, 16 },
> +		[SCLSR]		= { 0x24, 16 },
> +		[HSSRR]		= sci_reg_invalid,
> +		[SCPCR]		= sci_reg_invalid,
> +		[SCPDR]		= sci_reg_invalid,
> +		[SCDL]		= { 0x30, 16 },
> +		[SCCKS]		= { 0x34, 16 },
>  	},
> 
>  	/*
> @@ -310,6 +348,8 @@ static const struct plat_sci_reg
> sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { [HSSRR]		= { 0x40, 16 },
>  		[SCPCR]		= sci_reg_invalid,
>  		[SCPDR]		= sci_reg_invalid,
> +		[SCDL]		= { 0x30, 16 },
> +		[SCCKS]		= { 0x34, 16 },
>  	},
> 
>  	/*
> @@ -332,6 +372,8 @@ static const struct plat_sci_reg
> sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { [HSSRR]		= 
sci_reg_invalid,
>  		[SCPCR]		= sci_reg_invalid,
>  		[SCPDR]		= sci_reg_invalid,
> +		[SCDL]		= sci_reg_invalid,
> +		[SCCKS]		= sci_reg_invalid,
>  	},
> 
>  	/*
> @@ -354,6 +396,8 @@ static const struct plat_sci_reg
> sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { [HSSRR]		= 
sci_reg_invalid,
>  		[SCPCR]		= sci_reg_invalid,
>  		[SCPDR]		= sci_reg_invalid,
> +		[SCDL]		= sci_reg_invalid,
> +		[SCCKS]		= sci_reg_invalid,
>  	},
> 
>  	/*
> @@ -376,6 +420,8 @@ static const struct plat_sci_reg
> sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { [HSSRR]		= 
sci_reg_invalid,
>  		[SCPCR]		= sci_reg_invalid,
>  		[SCPDR]		= sci_reg_invalid,
> +		[SCDL]		= sci_reg_invalid,
> +		[SCCKS]		= sci_reg_invalid,
>  	},
>  };
> 
> diff --git a/drivers/tty/serial/sh-sci.h b/drivers/tty/serial/sh-sci.h
> index bf69bbdcc1f9aa39..54994f0bfafdbe12 100644
> --- a/drivers/tty/serial/sh-sci.h
> +++ b/drivers/tty/serial/sh-sci.h
> @@ -27,6 +27,8 @@ enum {
>  	HSSRR,				/* Sampling Rate Register */
>  	SCPCR,				/* Serial Port Control Register */
>  	SCPDR,				/* Serial Port Data Register */
> +	SCDL,				/* BRG Frequency Division Register */
> +	SCCKS,				/* BRG Clock Select Register */
> 
>  	SCIx_NR_REGS,
>  };
> @@ -109,6 +111,9 @@ enum {
>  #define SCPDR_RTSD	BIT(4)	/* Serial Port RTS Output Pin Data */
>  #define SCPDR_CTSD	BIT(3)	/* Serial Port CTS Input Pin Data */
> 
> +/* BRG Clock Select Register (Some SCIF and HSCIF) */
> +#define SCCKS_CKS	BIT(15)	/* Select SCK (1) or SC_CLK (0) */

This is slightly confusing. SC_CLK is defined as the external clock selectable 
between the bus clock and SCIF_CLK. The CKS bit selects the output of the baud 
rate generator for external clock as being the divided SC_CLK or the undivided 
(H)SCK. The comment, and I know it comes from the datasheet, seems to imply 
that the bit selects the input of the BRG-EC. Speaking of which it would be 
good to have a comment somewhere in the code to explain that we have two 
chained BRGs.

> +#define SCCKS_XIN	BIT(14)	/* SC_CLK uses bus clock (1) or SCIF_CLK (0) 
*/
> 
>  #define SCxSR_TEND(port)	(((port)->type == PORT_SCI) ? SCI_TEND   :
> SCIF_TEND) #define SCxSR_RDxF(port)	(((port)->type == PORT_SCI) ? 
SCI_RDRF 
>  : SCIF_RDF) diff --git a/include/linux/serial_sci.h
> b/include/linux/serial_sci.h index 7c536ac5be05d3aa..9f2bfd0557429ac3
> 100644
> --- a/include/linux/serial_sci.h
> +++ b/include/linux/serial_sci.h
> @@ -32,6 +32,7 @@ enum {
>  	SCIx_SH2_SCIF_FIFODATA_REGTYPE,
>  	SCIx_SH3_SCIF_REGTYPE,
>  	SCIx_SH4_SCIF_REGTYPE,
> +	SCIx_SH4_SCIF_BRG_REGTYPE,
>  	SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
>  	SCIx_SH4_SCIF_FIFODATA_REGTYPE,
>  	SCIx_SH7705_SCIF_REGTYPE,

-- 
Regards,

Laurent Pinchart

  reply	other threads:[~2015-11-19 20:45 UTC|newest]

Thread overview: 151+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-11-19 18:38 [PATCH 00/25] serial: sh-sci: Add external clock and BRG Support Geert Uytterhoeven
2015-11-19 18:38 ` Geert Uytterhoeven
     [not found] ` <1447958344-836-1-git-send-email-geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
2015-11-19 18:38   ` [PATCH 01/25] serial: sh-sci: Update DT binding documentation for external clock input Geert Uytterhoeven
2015-11-19 18:38     ` Geert Uytterhoeven
2015-11-19 18:38     ` Geert Uytterhoeven
     [not found]     ` <1447958344-836-2-git-send-email-geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
2015-11-19 20:19       ` Laurent Pinchart
2015-11-19 20:19         ` Laurent Pinchart
2015-11-19 20:19         ` Laurent Pinchart
2015-11-19 20:27         ` Laurent Pinchart
2015-11-19 20:27           ` Laurent Pinchart
2015-11-19 20:39           ` Geert Uytterhoeven
2015-11-19 20:39             ` Geert Uytterhoeven
2015-11-19 20:39             ` Geert Uytterhoeven
     [not found]             ` <CAMuHMdUnT2zCnj9QBVgxJaHV2fk5iuc7cxq=fh+fVTv3toOVaQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-11-19 21:17               ` Laurent Pinchart
2015-11-19 21:17                 ` Laurent Pinchart
2015-11-19 21:17                 ` Laurent Pinchart
2015-11-20  8:00                 ` Geert Uytterhoeven
2015-11-20  8:00                   ` Geert Uytterhoeven
2015-11-19 20:33         ` Geert Uytterhoeven
2015-11-19 20:33           ` Geert Uytterhoeven
     [not found]           ` <CAMuHMdX4ToefbBLR6o2AMuzCMoKcYo9XRZOzHJzgtQn552vmNg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-12-21 14:20             ` Geert Uytterhoeven
2015-12-21 14:20               ` Geert Uytterhoeven
2015-12-21 14:20               ` Geert Uytterhoeven
2015-11-19 18:38   ` [PATCH 02/25] serial: sh-sci: Update DT binding documentation for BRG support Geert Uytterhoeven
2015-11-19 18:38     ` Geert Uytterhoeven
2015-11-19 18:38     ` Geert Uytterhoeven
2015-11-19 20:26     ` Laurent Pinchart
2015-11-19 20:26       ` Laurent Pinchart
2015-11-19 20:44       ` Geert Uytterhoeven
2015-11-19 20:44         ` Geert Uytterhoeven
     [not found]         ` <CAMuHMdWHbc1kK7MipyZ_M_C6gPyPqvC4H35eZLXQezjbQNK2Jw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-11-19 21:13           ` Laurent Pinchart
2015-11-19 21:13             ` Laurent Pinchart
2015-11-19 21:13             ` Laurent Pinchart
2015-11-20  7:58             ` Geert Uytterhoeven
2015-11-20  7:58               ` Geert Uytterhoeven
2015-11-19 18:38 ` [PATCH 03/25] serial: sh-sci: Drop useless check for zero sampling_rate Geert Uytterhoeven
2015-11-19 18:38   ` Geert Uytterhoeven
2015-11-19 18:38 ` [PATCH 04/25] serial: sh-sci: Grammar s/Get ... for/Get ... from/ Geert Uytterhoeven
2015-11-19 18:38   ` Geert Uytterhoeven
2015-11-19 18:38 ` [PATCH 05/25] serial: sh-sci: Drop unused frame_len parameter for sci_baud_calc_hscif() Geert Uytterhoeven
2015-11-19 18:38   ` Geert Uytterhoeven
2015-11-19 18:38 ` [PATCH 06/25] serial: sh-sci: Don't overwrite clock selection in serial_console_write() Geert Uytterhoeven
2015-11-19 18:38   ` Geert Uytterhoeven
2015-11-19 18:38 ` [PATCH 07/25] serial: sh-sci: Convert from clk_get() to devm_clk_get() Geert Uytterhoeven
2015-11-19 18:38   ` Geert Uytterhoeven
2015-11-19 20:38   ` Laurent Pinchart
2015-11-19 20:38     ` Laurent Pinchart
2015-12-10 12:30     ` Geert Uytterhoeven
2015-12-10 12:30       ` Geert Uytterhoeven
2015-12-13 19:39       ` Laurent Pinchart
2015-12-13 19:39         ` Laurent Pinchart
2015-12-14 10:34         ` Geert Uytterhoeven
2015-12-14 10:34           ` Geert Uytterhoeven
2015-12-14 15:47           ` Laurent Pinchart
2015-12-14 15:47             ` Laurent Pinchart
2015-11-19 18:38 ` [PATCH 08/25] serial: sh-sci: Make unsigned values in sci_baud_calc_hscif() unsigned Geert Uytterhoeven
2015-11-19 18:38   ` Geert Uytterhoeven
2015-11-19 20:36   ` Laurent Pinchart
2015-11-19 20:36     ` Laurent Pinchart
2015-11-19 20:49     ` Geert Uytterhoeven
2015-11-19 20:49       ` Geert Uytterhoeven
2015-11-19 18:38 ` [PATCH 09/25] serial: sh-sci: Avoid overflow in sci_baud_calc_hscif() Geert Uytterhoeven
2015-11-19 18:38   ` Geert Uytterhoeven
2015-11-19 20:37   ` Laurent Pinchart
2015-11-19 20:37     ` Laurent Pinchart
2015-11-19 20:50     ` Geert Uytterhoeven
2015-11-19 20:50       ` Geert Uytterhoeven
2015-11-19 18:38 ` [PATCH 10/25] serial: sh-sci: Improve bit rate error calculation for HSCIF Geert Uytterhoeven
2015-11-19 18:38   ` Geert Uytterhoeven
2015-11-19 18:38 ` [PATCH 11/25] serial: sh-sci: Avoid calculating the receive margin " Geert Uytterhoeven
2015-11-19 18:38   ` Geert Uytterhoeven
2015-11-19 18:38 ` [PATCH 12/25] serial: sh-sci: Merge sci_scbrr_calc() and sci_baud_calc_hscif() Geert Uytterhoeven
2015-11-19 18:38   ` Geert Uytterhoeven
2015-11-19 18:38 ` [PATCH 13/25] serial: sh-sci: Take into account sampling rate for max baud rate Geert Uytterhoeven
2015-11-19 18:38   ` Geert Uytterhoeven
2015-11-19 18:38 ` [PATCH 14/25] serial: sh-sci: Add BRG register definitions Geert Uytterhoeven
2015-11-19 18:38   ` Geert Uytterhoeven
2015-11-19 20:45   ` Laurent Pinchart [this message]
2015-11-19 20:45     ` Laurent Pinchart
2015-11-19 18:38 ` [PATCH 15/25] serial: sh-sci: Replace struct sci_port_info by type/regtype encoding Geert Uytterhoeven
2015-11-19 18:38   ` Geert Uytterhoeven
2015-11-19 18:38 ` [PATCH 16/25] serial: sh-sci: Correct SCIF type on RZ/A1H Geert Uytterhoeven
2015-11-19 18:38   ` Geert Uytterhoeven
2015-11-19 18:38 ` [PATCH 17/25] serial: sh-sci: Correct SCIF type on R-Car for BRG Geert Uytterhoeven
2015-11-19 18:38   ` Geert Uytterhoeven
2015-11-19 20:55   ` Laurent Pinchart
2015-11-19 20:55     ` Laurent Pinchart
2015-11-20  7:46     ` Geert Uytterhoeven
2015-11-20  7:46       ` Geert Uytterhoeven
2015-11-20 14:52       ` Laurent Pinchart
2015-11-20 14:52         ` Laurent Pinchart
2015-11-20 15:30         ` Geert Uytterhoeven
2015-11-20 15:30           ` Geert Uytterhoeven
2015-11-20 15:33           ` Laurent Pinchart
2015-11-20 15:33             ` Laurent Pinchart
2015-12-10  9:21             ` Geert Uytterhoeven
2015-12-10  9:21               ` Geert Uytterhoeven
2015-12-11  1:12               ` Simon Horman
2015-12-11  1:12                 ` Simon Horman
2015-12-13 19:18               ` Laurent Pinchart
2015-12-13 19:18                 ` Laurent Pinchart
2015-11-19 18:38 ` [PATCH 18/25] serial: sh-sci: Prepare for multiple clocks and baud rate generators Geert Uytterhoeven
2015-11-19 18:38   ` Geert Uytterhoeven
2015-11-19 21:04   ` Laurent Pinchart
2015-11-19 21:04     ` Laurent Pinchart
2015-11-20  7:52     ` Geert Uytterhoeven
2015-11-20  7:52       ` Geert Uytterhoeven
2015-11-20 14:47       ` Laurent Pinchart
2015-11-20 14:47         ` Laurent Pinchart
2015-11-20 15:17         ` Geert Uytterhoeven
2015-11-20 15:17           ` Geert Uytterhoeven
2015-11-20 15:31           ` Laurent Pinchart
2015-11-20 15:31             ` Laurent Pinchart
2015-11-19 18:38 ` [PATCH 19/25] serial: sh-sci: Add support for optional external (H)SCK input Geert Uytterhoeven
2015-11-19 18:38   ` Geert Uytterhoeven
2015-11-19 18:38 ` [PATCH 20/25] serial: sh-sci: Add support for optional BRG on (H)SCIF Geert Uytterhoeven
2015-11-19 18:38   ` Geert Uytterhoeven
2015-11-19 18:39 ` [PATCH 21/25] ARM: shmobile: r8a7791 dtsi: Add BRG support for (H)SCIF Geert Uytterhoeven
2015-11-19 18:39   ` Geert Uytterhoeven
2015-11-19 18:39 ` [PATCH 22/25] ARM: shmobile: koelsch dts: Enable SCIF_CLK frequency and pins Geert Uytterhoeven
2015-11-19 18:39   ` Geert Uytterhoeven
2015-11-19 18:39 ` [PATCH 23/25] arm64: renesas: r8a7795 dtsi: Add BRG support for (H)SCIF Geert Uytterhoeven
2015-11-19 18:39   ` Geert Uytterhoeven
2015-11-19 21:07   ` Laurent Pinchart
2015-11-19 21:07     ` Laurent Pinchart
2015-11-20  8:17     ` Geert Uytterhoeven
2015-11-20  8:17       ` Geert Uytterhoeven
2015-11-19 18:39 ` [PATCH 24/25] arm64: renesas: salvator-x dts: Enable SCIF_CLK frequency and pins Geert Uytterhoeven
2015-11-19 18:39   ` Geert Uytterhoeven
2015-11-19 18:39 ` [PATCH 25/25] sh: sh7734: Correct SCIF type for BRG Geert Uytterhoeven
2015-11-19 18:39   ` Geert Uytterhoeven
2015-11-19 21:08 ` [PATCH 00/25] serial: sh-sci: Add external clock and BRG Support Laurent Pinchart
2015-11-19 21:08   ` Laurent Pinchart
2015-11-20  8:22   ` Geert Uytterhoeven
2015-11-20  8:22     ` Geert Uytterhoeven
2015-11-20  8:58     ` Laurent Pinchart
2015-11-20  8:58       ` Laurent Pinchart
2015-11-20  9:07       ` Geert Uytterhoeven
2015-11-20  9:07         ` Geert Uytterhoeven
2015-11-20 14:50         ` Laurent Pinchart
2015-11-20 14:50           ` Laurent Pinchart
2015-11-20 15:31           ` Geert Uytterhoeven
2015-11-20 15:31             ` Geert Uytterhoeven
2015-11-20  9:09 ` Geert Uytterhoeven
2015-11-20  9:09   ` Geert Uytterhoeven
2015-12-13  6:43   ` Greg Kroah-Hartman
2015-12-13  6:43     ` Greg Kroah-Hartman
2015-12-13  9:09     ` Geert Uytterhoeven
2015-12-13  9:09       ` Geert Uytterhoeven
2015-11-24  2:43 ` Simon Horman
2015-11-24  2:43   ` Simon Horman

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