From: Tomasz Figa <t.figa@samsung.com>
To: Thomas Abraham <thomas.abraham@linaro.org>
Cc: chander.kashyap@linaro.org, linux-arm-kernel@lists.infradead.org,
linux-samsung-soc@vger.kernel.org, kgene.kim@samsung.com,
mturquette@linaro.org, mturquette@ti.com,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] ARM: Exynos4: Register clocks via common clock framework
Date: Mon, 08 Oct 2012 09:31:16 +0200 [thread overview]
Message-ID: <1888016.dshEnlClG6@amdc1227> (raw)
In-Reply-To: <CAJuYYwQCPOFMnQrA-n42hQFtK3TXQtJSjkQZmVgh_4pqnMi8iw@mail.gmail.com>
On Monday 08 of October 2012 12:04:18 Thomas Abraham wrote:
> Hi Tomasz,
>
> On 3 October 2012 19:40, Tomasz Figa <t.figa@samsung.com> wrote:
> > Hi Chander, Thomas,
> >
> > I can see one more problem here.
> >
> > Based on the fact that sdhci-s3c driver receives only the endpoint gate
> > clock (hsmmc), doesn't the following setup make the driver unable to
> > change the frequency of this clock?
>
> The driver never changes the clock frequency of the core system clocks
> nor of the endpoint. There are internal dividers inside the sdhci
> controller which are divide to acheive required clock speed.
What is the use of sdhci_cmu_set_clock (which calls clk_set_rate) in sdhci-
s3c, then?
I think you are missing CLK_SET_RATE_PARENT flags in clocks of which rate
can be changed by the driver.
Best regards,
--
Tomasz Figa
Samsung Poland R&D Center
WARNING: multiple messages have this Message-ID (diff)
From: t.figa@samsung.com (Tomasz Figa)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/2] ARM: Exynos4: Register clocks via common clock framework
Date: Mon, 08 Oct 2012 09:31:16 +0200 [thread overview]
Message-ID: <1888016.dshEnlClG6@amdc1227> (raw)
In-Reply-To: <CAJuYYwQCPOFMnQrA-n42hQFtK3TXQtJSjkQZmVgh_4pqnMi8iw@mail.gmail.com>
On Monday 08 of October 2012 12:04:18 Thomas Abraham wrote:
> Hi Tomasz,
>
> On 3 October 2012 19:40, Tomasz Figa <t.figa@samsung.com> wrote:
> > Hi Chander, Thomas,
> >
> > I can see one more problem here.
> >
> > Based on the fact that sdhci-s3c driver receives only the endpoint gate
> > clock (hsmmc), doesn't the following setup make the driver unable to
> > change the frequency of this clock?
>
> The driver never changes the clock frequency of the core system clocks
> nor of the endpoint. There are internal dividers inside the sdhci
> controller which are divide to acheive required clock speed.
What is the use of sdhci_cmu_set_clock (which calls clk_set_rate) in sdhci-
s3c, then?
I think you are missing CLK_SET_RATE_PARENT flags in clocks of which rate
can be changed by the driver.
Best regards,
--
Tomasz Figa
Samsung Poland R&D Center
next prev parent reply other threads:[~2012-10-08 7:31 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-01 12:09 [PATCH 0/2] ARM: Exynos4: Migrate to common clock framework chander.kashyap
2012-10-01 12:09 ` chander.kashyap at linaro.org
2012-10-01 12:09 ` [PATCH 1/2] ARM: Exynos4: Remove Samsung clock type support chander.kashyap
2012-10-01 12:09 ` chander.kashyap at linaro.org
2012-10-01 12:09 ` [PATCH 2/2] ARM: Exynos4: Register clocks via common clock framework chander.kashyap
2012-10-01 12:09 ` chander.kashyap at linaro.org
2012-10-03 8:25 ` Tomasz Figa
2012-10-03 8:25 ` Tomasz Figa
2012-10-08 6:34 ` Thomas Abraham
2012-10-08 6:34 ` Thomas Abraham
2012-10-03 10:40 ` Tomasz Figa
2012-10-03 10:40 ` Tomasz Figa
2012-10-08 6:34 ` Thomas Abraham
2012-10-08 6:34 ` Thomas Abraham
2012-10-08 7:31 ` Tomasz Figa [this message]
2012-10-08 7:31 ` Tomasz Figa
2012-10-05 15:21 ` Sylwester Nawrocki
2012-10-05 15:21 ` Sylwester Nawrocki
2012-10-08 6:34 ` Thomas Abraham
2012-10-08 6:34 ` Thomas Abraham
2012-10-03 7:26 ` [PATCH 0/2] ARM: Exynos4: Migrate to " Tomasz Figa
2012-10-03 7:26 ` Tomasz Figa
2012-10-08 6:32 ` Thomas Abraham
2012-10-08 6:32 ` Thomas Abraham
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