* RE: LL_TEMAC+LL_DMA configuration on Xilinx ML507
2008-09-09 18:03 LL_TEMAC+LL_DMA configuration on Xilinx ML507 Stuart Bershtein
@ 2008-09-09 18:07 ` John Linn
0 siblings, 0 replies; 2+ messages in thread
From: John Linn @ 2008-09-09 18:07 UTC (permalink / raw)
To: Stuart Bershtein, linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 1811 bytes --]
Hi Stu,
I have attached the MHS file for the v2 bitstream.
I just pushed out changes yesterday to our git tree that move us to a
new bit stream that is based on the V5FXT development kit that Xilinx
released on xilinx.com. If interested, you can find more info on
http://xilinx.wikidot.com.
Thanks,
John
> -----Original Message-----
> From: linuxppc-embedded-bounces+john.linn=xilinx.com@ozlabs.org
[mailto:linuxppc-embedded-
> bounces+john.linn=xilinx.com@ozlabs.org] On Behalf Of Stuart Bershtein
> Sent: Tuesday, September 09, 2008 12:03 PM
> To: linuxppc-embedded@ozlabs.org
> Subject: LL_TEMAC+LL_DMA configuration on Xilinx ML507
>
>
> I am hoping someone can give me some general suggestions for
generating a
> proper bitstream that is compatible with linux 2.6 on the ml507 board.
We
> are using Xilinx XPS, 10.1.2. We haven't had much luck so far. If
someone
> has the MHS file that was generated with ml507_rtos_dma_v2.bit that
would be
> very helpful! Thanks in advance for your help.
>
> Stu
> --
> View this message in context:
http://www.nabble.com/LL_TEMAC%2BLL_DMA-configuration-on-Xilinx-ML507-
> tp19397898p19397898.html
> Sent from the linuxppc-embedded mailing list archive at Nabble.com.
>
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[-- Attachment #2: system.mhs --]
[-- Type: application/octet-stream, Size: 18442 bytes --]
# ########################################################################
# Copyright(C) 2008 by Xilinx, Inc. All rights reserved. ##
# ##
# You may copy and modify these files for your own internal use solely ##
# with Xilinx programmable logic devices and Xilinx EDK system or ##
# create IP modules solely for Xilinx programmable logic devices and ##
# Xilinx EDK system. No rights are granted to distribute any files ##
# unless they are distributed in Xilinx programmable logic devices. ##
# ##
# Source code is provided as-is , with no obligation on the part of ##
# Xilinx to provide support. ##
# ##
# ########################################################################
# ########################################################################
# ##
# ML507 PowerPC 440 Embedded Reference System for Xilinx EDK 10.1.02 ##
# ##
# Target Board: Xilinx Virtex 5 ML507 Evaluation Platform Rev A ##
# Family: virtex5 ##
# Device: xc5vfx70t ##
# Package: ff1136 ##
# Speed Grade: -1 ##
# Processor: ppc440_0 ##
# Processor clock frequency: 400.00 MHz ##
# Bus clock frequency: 100.00 MHz ##
# On Chip Memory : 64 KB ##
# Total Off Chip Memory : 32 MB ##
# - FLASH = 32 MB ##
# ########################################################################
PARAMETER VERSION = 2.1.0
PORT fpga_0_Hard_Ethernet_MAC_PHY_MII_INT = fpga_0_Hard_Ethernet_MAC_PHY_MII_INT, DIR = I, SENSITIVITY = LEVEL_LOW, SIGIS = INTERRUPT
PORT fpga_0_RS232_Uart_1_sin_pin = fpga_0_RS232_Uart_1_sin, DIR = I
PORT fpga_0_RS232_Uart_1_sout_pin = fpga_0_RS232_Uart_1_sout, DIR = O
PORT fpga_0_LEDs_8Bit_GPIO_IO_pin = fpga_0_LEDs_8Bit_GPIO_IO, DIR = IO, VEC = [0:7]
PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO, DIR = IO, VEC = [0:4]
PORT fpga_0_Push_Buttons_5Bit_GPIO_IO_pin = fpga_0_Push_Buttons_5Bit_GPIO_IO, DIR = IO, VEC = [0:4]
PORT fpga_0_DIP_Switches_8Bit_GPIO_IO_pin = fpga_0_DIP_Switches_8Bit_GPIO_IO, DIR = IO, VEC = [0:7]
PORT fpga_0_FLASH_Mem_A_pin = fpga_0_FLASH_Mem_A, DIR = O, VEC = [7:30]
PORT fpga_0_FLASH_Mem_DQ_pin = fpga_0_FLASH_Mem_DQ, DIR = IO, VEC = [0:15]
PORT fpga_0_FLASH_Mem_ADV_LDN_pin = fpga_0_FLASH_Mem_ADV_LDN, DIR = O
PORT fpga_0_FLASH_Mem_WEN_pin = fpga_0_FLASH_Mem_WEN, DIR = O
PORT fpga_0_FLASH_Mem_OEN_pin = fpga_0_FLASH_Mem_OEN, DIR = O
PORT fpga_0_FLASH_Mem_CEN_pin = fpga_0_FLASH_Mem_CEN, DIR = O
PORT fpga_0_DDR2_SDRAM_DDR2_ODT_pin = fpga_0_DDR2_SDRAM_DDR2_ODT, DIR = O, VEC = [1:0]
PORT fpga_0_DDR2_SDRAM_DDR2_A_pin = fpga_0_DDR2_SDRAM_DDR2_A, DIR = O, VEC = [12:0]
PORT fpga_0_DDR2_SDRAM_DDR2_BA_pin = fpga_0_DDR2_SDRAM_DDR2_BA, DIR = O, VEC = [1:0]
PORT fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin = fpga_0_DDR2_SDRAM_DDR2_CAS_N, DIR = O
PORT fpga_0_DDR2_SDRAM_DDR2_CKE_pin = fpga_0_DDR2_SDRAM_DDR2_CKE, DIR = O, VEC = [0:0]
PORT fpga_0_DDR2_SDRAM_DDR2_CS_N_pin = fpga_0_DDR2_SDRAM_DDR2_CS_N, DIR = O, VEC = [0:0]
PORT fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin = fpga_0_DDR2_SDRAM_DDR2_RAS_N, DIR = O
PORT fpga_0_DDR2_SDRAM_DDR2_WE_N_pin = fpga_0_DDR2_SDRAM_DDR2_WE_N, DIR = O
PORT fpga_0_DDR2_SDRAM_DDR2_CK_pin = fpga_0_DDR2_SDRAM_DDR2_CK, DIR = O, VEC = [1:0]
PORT fpga_0_DDR2_SDRAM_DDR2_CK_N_pin = fpga_0_DDR2_SDRAM_DDR2_CK_N, DIR = O, VEC = [1:0]
PORT fpga_0_DDR2_SDRAM_DDR2_DM_pin = fpga_0_DDR2_SDRAM_DDR2_DM, DIR = O, VEC = [7:0]
PORT fpga_0_DDR2_SDRAM_DDR2_DQS = fpga_0_DDR2_SDRAM_DDR2_DQS, DIR = IO, VEC = [7:0]
PORT fpga_0_DDR2_SDRAM_DDR2_DQS_N = fpga_0_DDR2_SDRAM_DDR2_DQS_N, DIR = IO, VEC = [7:0]
PORT fpga_0_DDR2_SDRAM_DDR2_DQ = fpga_0_DDR2_SDRAM_DDR2_DQ, DIR = IO, VEC = [63:0]
PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = I
PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, DIR = O, VEC = [6:0]
PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, DIR = IO, VEC = [15:0]
PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = O
PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = O
PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = O
PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = I
PORT fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin = fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n, DIR = O
PORT fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_TXD_0, DIR = O, VEC = [7:0]
PORT fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0, DIR = O
PORT fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0, DIR = O
PORT fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0, DIR = O
PORT fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0, DIR = I
PORT fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0, DIR = I
PORT fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0, DIR = I
PORT fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin = fpga_0_Hard_Ethernet_MAC_GMII_RXD_0, DIR = I, VEC = [7:0]
PORT fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin = fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0, DIR = I
PORT fpga_0_Hard_Ethernet_MAC_MDC_0_pin = fpga_0_Hard_Ethernet_MAC_MDC_0, DIR = O
PORT fpga_0_Hard_Ethernet_MAC_MDIO_0_pin = fpga_0_Hard_Ethernet_MAC_MDIO_0, DIR = IO
PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
BEGIN ppc440_virtex5
PARAMETER INSTANCE = ppc440_0
PARAMETER HW_VER = 1.01.a
PARAMETER C_PPC440MC_ROW_CONFLICT_MASK = 0x003FFE00
PARAMETER C_PPC440MC_BANK_CONFLICT_MASK = 0x00C00000
PARAMETER C_PPC440MC_CONTROL = 0xf810008f
PARAMETER C_NUM_DMA = 1
PARAMETER C_APU_CONTROL = 0b00000000000000001
PARAMETER C_IDCR_BASEADDR = 0b0000000000
PARAMETER C_IDCR_HIGHADDR = 0b0011111111
BUS_INTERFACE MPLB = plb_v46_0
BUS_INTERFACE PPC440MC = ppc440_0_PPC440MC
BUS_INTERFACE LLDMA0 = Hard_Ethernet_MAC_LLINK0
BUS_INTERFACE MFCB = fcb_v20_0
BUS_INTERFACE JTAGPPC = jtagppc_cntlr_0_0
BUS_INTERFACE RESETPPC = ppc_reset_bus
PORT CPMC440CLK = proc_clk_s
PORT CPMPPCMPLBCLK = sys_clk_s
PORT CPMPPCS0PLBCLK = sys_clk_s
PORT CPMINTERCONNECTCLKNTO1 = net_vcc
PORT CPMDMA0LLCLK = sys_clk_s
PORT CPMMCCLK = clk_200mhz_s
PORT CPMINTERCONNECTCLK = ppc440_0_CPMINTERCONNECTCLK
PORT DMA0TXIRQ = ppc440_0_DMA0TXIRQ
PORT DMA0RXIRQ = ppc440_0_DMA0RXIRQ
PORT EICC440EXTIRQ = EICC440EXTIRQ
END
BEGIN plb_v46
PARAMETER INSTANCE = plb_v46_0
PARAMETER C_DCR_INTFCE = 0
PARAMETER HW_VER = 1.03.a
PORT PLB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
END
BEGIN ppc440mc_ddr2
PARAMETER INSTANCE = DDR2_SDRAM
PARAMETER C_INCLUDE_ECC_SUPPORT = 0
PARAMETER C_DDR_BURST_LENGTH = 4
PARAMETER C_MIB_MC_CLOCK_RATIO = 1
PARAMETER C_IDEL_HIGH_PERF = TRUE
PARAMETER HW_VER = 2.00.a
PARAMETER C_NUM_IDELAYCTRL = 3
PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y6-IDELAYCTRL_X0Y2-IDELAYCTRL_X0Y1
PARAMETER C_DQS_IO_COL = 0b000000000000000000
PARAMETER C_DQ_IO_MS = 0b000000000111010100111101000011110001111000101110110000111100000110111100
PARAMETER C_NUM_CLK_PAIRS = 2
PARAMETER C_DDR2_ODT_SETTING = 1
PARAMETER C_DDR_BAWIDTH = 2
PARAMETER C_DDR_DWIDTH = 64
PARAMETER C_DDR_CAWIDTH = 10
PARAMETER C_NUM_RANKS_MEM = 1
PARAMETER C_CS_BITS = 0
PARAMETER C_DDR_DM_WIDTH = 8
PARAMETER C_DQ_BITS = 8
PARAMETER C_DDR2_ODT_WIDTH = 2
PARAMETER C_DDR2_ADDT_LAT = 0
PARAMETER C_DQS_BITS = 3
PARAMETER C_DDR_DQS_WIDTH = 8
PARAMETER C_REG_DIMM = 0
PARAMETER C_DDR_RAWIDTH = 13
PARAMETER C_DDR_CAS_LAT = 4
PARAMETER C_DDR_TREFI = 3900
PARAMETER C_DDR_TRAS = 40000
PARAMETER C_DDR_TRCD = 15000
PARAMETER C_DDR_TRFC = 75000
PARAMETER C_DDR_TRP = 15000
PARAMETER C_DDR_TRTP = 7500
PARAMETER C_DDR_TWR = 15000
PARAMETER C_DDR_TWTR = 7500
PARAMETER C_MC_MIBCLK_PERIOD_PS = 5000
PARAMETER C_MEM_BASEADDR = 0x00000000
PARAMETER C_MEM_HIGHADDR = 0x0fffffff
BUS_INTERFACE PPC440MC = ppc440_0_PPC440MC
PORT DDR2_ODT = fpga_0_DDR2_SDRAM_DDR2_ODT
PORT DDR2_A = fpga_0_DDR2_SDRAM_DDR2_A
PORT DDR2_BA = fpga_0_DDR2_SDRAM_DDR2_BA
PORT DDR2_CAS_N = fpga_0_DDR2_SDRAM_DDR2_CAS_N
PORT DDR2_CKE = fpga_0_DDR2_SDRAM_DDR2_CKE
PORT DDR2_CS_N = fpga_0_DDR2_SDRAM_DDR2_CS_N
PORT DDR2_RAS_N = fpga_0_DDR2_SDRAM_DDR2_RAS_N
PORT DDR2_WE_N = fpga_0_DDR2_SDRAM_DDR2_WE_N
PORT DDR2_CK = fpga_0_DDR2_SDRAM_DDR2_CK
PORT DDR2_CK_N = fpga_0_DDR2_SDRAM_DDR2_CK_N
PORT DDR2_DM = fpga_0_DDR2_SDRAM_DDR2_DM
PORT DDR2_DQS = fpga_0_DDR2_SDRAM_DDR2_DQS
PORT DDR2_DQS_N = fpga_0_DDR2_SDRAM_DDR2_DQS_N
PORT DDR2_DQ = fpga_0_DDR2_SDRAM_DDR2_DQ
PORT mc_mibclk = clk_200mhz_s
PORT mi_mcclk90 = clk_200mhz_s90
PORT mi_mcclk_200 = clk_200mhz_s
PORT mi_mcclkdiv2 = sys_clk_s
PORT mi_mcreset = sys_bus_reset
END
BEGIN xps_bram_if_cntlr
PARAMETER INSTANCE = xps_bram_if_cntlr_1
PARAMETER C_SPLB_NATIVE_DWIDTH = 64
PARAMETER C_SPLB_P2P = 0
PARAMETER C_SPLB_SUPPORT_BURSTS = 1
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0xffff0000
PARAMETER C_HIGHADDR = 0xffffffff
BUS_INTERFACE SPLB = plb_v46_0
BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END
BEGIN bram_block
PARAMETER INSTANCE = xps_bram_if_cntlr_1_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END
BEGIN xps_uart16550
PARAMETER INSTANCE = RS232_Uart_1
PARAMETER HW_VER = 2.00.a
PARAMETER C_IS_A_16550 = 1
PARAMETER C_BASEADDR = 0x83e00000
PARAMETER C_HIGHADDR = 0x83e0ffff
BUS_INTERFACE SPLB = plb_v46_0
PORT sin = fpga_0_RS232_Uart_1_sin
PORT sout = fpga_0_RS232_Uart_1_sout
PORT IP2INTC_Irpt = RS232_Uart_1_IP2INTC_Irpt
END
BEGIN xps_gpio
PARAMETER INSTANCE = LEDs_8Bit
PARAMETER HW_VER = 1.00.a
PARAMETER C_GPIO_WIDTH = 8
PARAMETER C_IS_DUAL = 0
PARAMETER C_IS_BIDIR = 1
PARAMETER C_ALL_INPUTS = 0
PARAMETER C_BASEADDR = 0x81400000
PARAMETER C_HIGHADDR = 0x8140ffff
BUS_INTERFACE SPLB = plb_v46_0
PORT GPIO_IO = fpga_0_LEDs_8Bit_GPIO_IO
END
BEGIN xps_gpio
PARAMETER INSTANCE = LEDs_Positions
PARAMETER HW_VER = 1.00.a
PARAMETER C_GPIO_WIDTH = 5
PARAMETER C_IS_DUAL = 0
PARAMETER C_IS_BIDIR = 1
PARAMETER C_ALL_INPUTS = 0
PARAMETER C_BASEADDR = 0x81420000
PARAMETER C_HIGHADDR = 0x8142ffff
BUS_INTERFACE SPLB = plb_v46_0
PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO
END
BEGIN xps_gpio
PARAMETER INSTANCE = Push_Buttons_5Bit
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERRUPT_PRESENT = 1
PARAMETER C_GPIO_WIDTH = 5
PARAMETER C_IS_DUAL = 0
PARAMETER C_IS_BIDIR = 1
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_BASEADDR = 0x81440000
PARAMETER C_HIGHADDR = 0x8144ffff
BUS_INTERFACE SPLB = plb_v46_0
PORT GPIO_IO = fpga_0_Push_Buttons_5Bit_GPIO_IO
PORT IP2INTC_Irpt = Push_Buttons_5Bit_IP2INTC_Irpt
END
BEGIN xps_gpio
PARAMETER INSTANCE = DIP_Switches_8Bit
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERRUPT_PRESENT = 1
PARAMETER C_GPIO_WIDTH = 8
PARAMETER C_IS_DUAL = 0
PARAMETER C_IS_BIDIR = 1
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_BASEADDR = 0x81460000
PARAMETER C_HIGHADDR = 0x8146ffff
BUS_INTERFACE SPLB = plb_v46_0
PORT GPIO_IO = fpga_0_DIP_Switches_8Bit_GPIO_IO
PORT IP2INTC_Irpt = DIP_Switches_8Bit_IP2INTC_Irpt
END
BEGIN xps_mch_emc
PARAMETER INSTANCE = FLASH
PARAMETER HW_VER = 2.00.a
PARAMETER C_MCH_PLB_CLK_PERIOD_PS = 10000
PARAMETER C_NUM_BANKS_MEM = 1
PARAMETER C_MAX_MEM_WIDTH = 16
PARAMETER C_MEM0_WIDTH = 16
PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
PARAMETER C_SYNCH_MEM_0 = 0
PARAMETER C_TCEDV_PS_MEM_0 = 110000
PARAMETER C_TWC_PS_MEM_0 = 11000
PARAMETER C_TAVDV_PS_MEM_0 = 110000
PARAMETER C_TWP_PS_MEM_0 = 70000
PARAMETER C_THZCE_PS_MEM_0 = 35000
PARAMETER C_TLZWE_PS_MEM_0 = 35000
PARAMETER C_MEM0_BASEADDR = 0xfc000000
PARAMETER C_MEM0_HIGHADDR = 0xfdffffff
BUS_INTERFACE SPLB = plb_v46_0
PORT Mem_A = fpga_0_FLASH_Mem_A_split
PORT Mem_WEN = fpga_0_FLASH_Mem_WEN
PORT Mem_DQ = fpga_0_FLASH_Mem_DQ
PORT Mem_OEN = fpga_0_FLASH_Mem_OEN
PORT Mem_CEN = fpga_0_FLASH_Mem_CEN
PORT Mem_ADV_LDN = fpga_0_FLASH_Mem_ADV_LDN
PORT RdClk = sys_clk_s
END
BEGIN xps_ll_temac
PARAMETER INSTANCE = Hard_Ethernet_MAC
PARAMETER HW_VER = 1.01.b
PARAMETER C_NUM_IDELAYCTRL = 2
PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y4-IDELAYCTRL_X1Y5
PARAMETER C_TEMAC_TYPE = 0
PARAMETER C_BUS2CORE_CLK_RATIO = 1
PARAMETER C_BASEADDR = 0x81c00000
PARAMETER C_HIGHADDR = 0x81c0ffff
PARAMETER C_TEMAC0_TXCSUM = 1
PARAMETER C_TEMAC0_RXCSUM = 1
BUS_INTERFACE SPLB = plb_v46_0
BUS_INTERFACE LLINK0 = Hard_Ethernet_MAC_LLINK0
PORT TemacPhy_RST_n = fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n
PORT GMII_TXD_0 = fpga_0_Hard_Ethernet_MAC_GMII_TXD_0
PORT GMII_TX_EN_0 = fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0
PORT GMII_TX_ER_0 = fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0
PORT GMII_TX_CLK_0 = fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0
PORT GMII_RXD_0 = fpga_0_Hard_Ethernet_MAC_GMII_RXD_0
PORT GMII_RX_DV_0 = fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0
PORT GMII_RX_ER_0 = fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0
PORT GMII_RX_CLK_0 = fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0
PORT MII_TX_CLK_0 = fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0
PORT MDC_0 = fpga_0_Hard_Ethernet_MAC_MDC_0
PORT MDIO_0 = fpga_0_Hard_Ethernet_MAC_MDIO_0
PORT GTX_CLK_0 = temac_clk_s
PORT REFCLK = clk_200mhz_s
PORT LlinkTemac0_CLK = sys_clk_s
PORT TemacIntc0_Irpt = Hard_Ethernet_MAC_TemacIntc0_Irpt
END
BEGIN xps_sysace
PARAMETER INSTANCE = SysACE_CompactFlash
PARAMETER HW_VER = 1.00.a
PARAMETER C_MEM_WIDTH = 16
PARAMETER C_BASEADDR = 0x83600000
PARAMETER C_HIGHADDR = 0x8360ffff
BUS_INTERFACE SPLB = plb_v46_0
PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK
PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA
PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD
PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN
PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN
PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN
PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
PORT SysACE_IRQ = SysACE_CompactFlash_SysACE_IRQ
END
BEGIN xps_timer
PARAMETER INSTANCE = xps_timer_1
PARAMETER HW_VER = 1.00.a
PARAMETER C_COUNT_WIDTH = 32
PARAMETER C_ONE_TIMER_ONLY = 1
PARAMETER C_BASEADDR = 0x83c00000
PARAMETER C_HIGHADDR = 0x83c0ffff
BUS_INTERFACE SPLB = plb_v46_0
PORT Interrupt = xps_timer_1_Interrupt
END
BEGIN xps_timebase_wdt
PARAMETER INSTANCE = xps_timebase_wdt_1
PARAMETER HW_VER = 1.00.b
PARAMETER C_WDT_ENABLE_ONCE = 0
PARAMETER C_WDT_INTERVAL = 30
PARAMETER C_BASEADDR = 0x83a00000
PARAMETER C_HIGHADDR = 0x83a0ffff
BUS_INTERFACE SPLB = plb_v46_0
PORT Timebase_Interrupt = xps_timebase_wdt_1_Timebase_Interrupt
PORT WDT_Interrupt = xps_timebase_wdt_1_WDT_Interrupt
END
BEGIN util_bus_split
PARAMETER INSTANCE = FLASH_util_bus_split_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE_IN = 32
PARAMETER C_LEFT_POS = 7
PARAMETER C_SPLIT = 31
PORT Sig = fpga_0_FLASH_Mem_A_split
PORT Out1 = fpga_0_FLASH_Mem_A
END
BEGIN fcb_v20
PARAMETER INSTANCE = fcb_v20_0
PARAMETER HW_VER = 1.00.a
PORT SYS_RST = sys_bus_reset
PORT FCB_CLK = fcm_clk_s
END
BEGIN apu_fpu_virtex5
PARAMETER INSTANCE = apu_fpu_virtex5_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_DOUBLE_PRECISION = 1
PARAMETER C_USE_RLOCS = 0
PARAMETER C_LATENCY_CONF = 1
BUS_INTERFACE SFCB2 = fcb_v20_0
END
BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER HW_VER = 2.01.a
PARAMETER C_EXT_RESET_HIGH = 1
PARAMETER C_CLKIN_FREQ = 100000000
PARAMETER C_CLKOUT0_FREQ = 400000000
PARAMETER C_CLKOUT0_BUF = TRUE
PARAMETER C_CLKOUT0_PHASE = 0
PARAMETER C_CLKOUT0_GROUP = PLL0
PARAMETER C_CLKOUT1_FREQ = 200000000
PARAMETER C_CLKOUT1_BUF = TRUE
PARAMETER C_CLKOUT1_PHASE = 0
PARAMETER C_CLKOUT1_GROUP = PLL0
PARAMETER C_CLKOUT2_FREQ = 100000000
PARAMETER C_CLKOUT2_BUF = TRUE
PARAMETER C_CLKOUT2_PHASE = 0
PARAMETER C_CLKOUT2_GROUP = PLL0_ADJUST
PARAMETER C_CLKOUT3_FREQ = 200000000
PARAMETER C_CLKOUT3_BUF = TRUE
PARAMETER C_CLKOUT3_PHASE = 0
PARAMETER C_CLKOUT3_GROUP = PLL0_ADJUST
PARAMETER C_CLKOUT4_FREQ = 200000000
PARAMETER C_CLKOUT4_BUF = TRUE
PARAMETER C_CLKOUT4_PHASE = 90
PARAMETER C_CLKOUT4_GROUP = PLL0_ADJUST
PARAMETER C_CLKOUT5_FREQ = 125000000
PARAMETER C_CLKOUT5_BUF = TRUE
PARAMETER C_CLKOUT5_PHASE = 0
PARAMETER C_CLKOUT5_GROUP = PLL0_ADJUST
PARAMETER C_CLKOUT6_FREQ = 133333333
PARAMETER C_CLKOUT6_BUF = TRUE
PARAMETER C_CLKOUT6_PHASE = 0
PARAMETER C_CLKOUT6_GROUP = PLL0_ADJUST
PORT CLKOUT0 = proc_clk_s
PORT CLKOUT1 = ppc440_0_CPMINTERCONNECTCLK
PORT CLKOUT2 = sys_clk_s
PORT CLKOUT3 = clk_200mhz_s
PORT CLKOUT4 = clk_200mhz_s90
PORT CLKOUT5 = temac_clk_s
PORT CLKOUT6 = fcm_clk_s
PORT CLKIN = dcm_clk_s
PORT LOCKED = Dcm_all_locked
PORT RST = net_gnd
END
BEGIN jtagppc_cntlr
PARAMETER INSTANCE = jtagppc_cntlr_0
PARAMETER HW_VER = 2.01.b
BUS_INTERFACE JTAGPPC0 = jtagppc_cntlr_0_0
END
BEGIN proc_sys_reset
PARAMETER INSTANCE = proc_sys_reset_0
PARAMETER HW_VER = 2.00.a
PARAMETER C_EXT_RESET_HIGH = 0
BUS_INTERFACE RESETPPC0 = ppc_reset_bus
PORT Slowest_sync_clk = sys_clk_s
PORT Dcm_locked = Dcm_all_locked
PORT Ext_Reset_In = sys_rst_s
PORT Bus_Struct_Reset = sys_bus_reset
PORT Peripheral_Reset = sys_periph_reset
END
BEGIN xps_intc
PARAMETER INSTANCE = xps_intc_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x81800000
PARAMETER C_HIGHADDR = 0x8180ffff
BUS_INTERFACE SPLB = plb_v46_0
PORT Irq = EICC440EXTIRQ
PORT Intr = ppc440_0_DMA0TXIRQ & ppc440_0_DMA0RXIRQ & RS232_Uart_1_IP2INTC_Irpt & Push_Buttons_5Bit_IP2INTC_Irpt & DIP_Switches_8Bit_IP2INTC_Irpt & Hard_Ethernet_MAC_TemacIntc0_Irpt & SysACE_CompactFlash_SysACE_IRQ & xps_timer_1_Interrupt & xps_timebase_wdt_1_Timebase_Interrupt & xps_timebase_wdt_1_WDT_Interrupt & fpga_0_Hard_Ethernet_MAC_PHY_MII_INT
END
^ permalink raw reply [flat|nested] 2+ messages in thread