DMA bus-master writes & CPU cache question

DMA bus-master writes & CPU cache question

[Alan Arolovitch]

Hi,

we're developing broadband NIC driver and I have the following
question: the hardware performs PCI bus-master DMA writes into 
the RAM and the driver is either throgh polling or interrupt
handling routine reads the DMA area.
Should CPU cache affect reading data from the DMA area, i.e.
may some buffering effect or data inconherence appear? If so, 
what are the options?
I've seen some mention to allocation of non-cacheable memory
in NDIS documentation, is it something I have to do in Linux
as well?

i'd appreciate responses via email, i don't regularly monitor
the list. and of course i'll summarize to the list..


rgds,
						--alan.

-- 
Alan Arolovitch, CTO		       Gravity Computing Solutions Ltd.	
email: alan@gravity-cs.com + tel.: +972-3-5474450 + fax: +972-3-5474451

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Re: DMA bus-master writes & CPU cache question

[Philip Blundell]

>Should CPU cache affect reading data from the DMA area, i.e.
>may some buffering effect or data inconherence appear? If so, 
>what are the options?

This depends on your architecture.  Intel platforms are fully DMA coherent; 
the chipset snoops on DMA cycles and flushes the cache as required to maintain 
a consistent view.  On some other machines this is not the case and you must 
deal with the caches by hand (see, for example, 
include/asm-arm/proc-armv/io.h).

p.



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