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From: Stephen Boyd <sboyd@kernel.org>
To: Krzysztof Kozlowski <krzk@kernel.org>,
	Michal Wilczynski <m.wilczynski@samsung.com>,
	airlied@gmail.com, aou@eecs.berkeley.edu, conor+dt@kernel.org,
	drew@pdp7.com, frank.binns@imgtec.com, guoren@kernel.org,
	jassisinghbrar@gmail.com, jszhang@kernel.org, krzk+dt@kernel.org,
	m.szyprowski@samsung.com, maarten.lankhorst@linux.intel.com,
	matt.coster@imgtec.com, mripard@kernel.org,
	mturquette@baylibre.com, palmer@dabbelt.com,
	paul.walmsley@sifive.com, robh@kernel.org, simona@ffwll.ch,
	tzimmermann@suse.de, ulf.hansson@linaro.org, wefu@redhat.com
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org
Subject: Re: [RFC PATCH v1 05/14] dt-bindings: clock: thead,th1520: Add support for Video Output subsystem
Date: Wed, 04 Dec 2024 12:21:11 -0800	[thread overview]
Message-ID: <1b05b11b2a8287c0ff4b6bdd079988c7.sboyd@kernel.org> (raw)
In-Reply-To: <07bfb02a-1df3-4a03-83bb-d7edc540739d@samsung.com>

Quoting Michal Wilczynski (2024-12-04 02:11:26)
> On 12/3/24 16:45, Krzysztof Kozlowski wrote:
> > On 03/12/2024 14:41, Michal Wilczynski wrote:
> 
> [1] - https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20Video%20Image%20Processing%20User%20Manual.pdf
> > 
> >> +      these registers reside in the same address space, access to
> >> +      them is coordinated through a shared syscon regmap provided by
> >> +      the specified syscon node.
> > 
> > Drop last sentence. syscon regmap is a Linux term, not hardware one.
> > 
> > Anyway, this needs to be constrained per variant.
> > 
> >> +
> >>    "#clock-cells":
> >>      const: 1
> >>      description:
> >> @@ -36,8 +51,6 @@ properties:
> >>  
> >>  required:
> >>    - compatible
> >> -  - reg
> > 
> > No, that's a clear NAK. You claim you have no address space but in the
> > same time you have address space via regmap.
> 
> I see your concern. The VOSYS subsystem's address space includes
> registers for various components, such as clock gates and reset
> controls, which are scattered throughout the address space as specified
> in the manual 4.4.1 [2]. Initially, I attempted to use a shared syscon
> regmap for access, but I realize this might not be the best approach.
> 
> To address this, I'll specify the 'reg' property in each node to define
> the address ranges explicitly fragmenting the address space for the VOSYS
> manually.
> 
> vosys_clk: clock-controller@ffef528050 {
>         compatible = "thead,th1520-clk-vo";
>         reg = <0xff 0xef528050 0x0 0x8>;
>         #clock-cells = <1>;
> };
> 
> pd: power-domain@ffef528000 {
>         compatible = "thead,th1520-pd";
>         reg = <0xff 0xef528000 0x0 0x8>;
>         #power-domain-cells = <1>;
> };

You should have one node:

    clock-controller@ffef528000 {
      compatible = "thead,th1520-vo";
      reg = <0xff 0xef528050 0x0 0x1a04>;
      #clock-cells = <1>;
      #power-domain-cells = <1>;
    };

WARNING: multiple messages have this Message-ID (diff)
From: Stephen Boyd <sboyd@kernel.org>
To: Krzysztof Kozlowski <krzk@kernel.org>,
	Michal Wilczynski <m.wilczynski@samsung.com>,
	airlied@gmail.com, aou@eecs.berkeley.edu, conor+dt@kernel.org,
	drew@pdp7.com, frank.binns@imgtec.com, guoren@kernel.org,
	jassisinghbrar@gmail.com, jszhang@kernel.org, krzk+dt@kernel.org,
	m.szyprowski@samsung.com, maarten.lankhorst@linux.intel.com,
	matt.coster@imgtec.com, mripard@kernel.org,
	mturquette@baylibre.com, palmer@dabbelt.com,
	paul.walmsley@sifive.com, robh@kernel.org, simona@ffwll.ch,
	tzimmermann@suse.de, ulf.hansson@linaro.org, wefu@redhat.com
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org
Subject: Re: [RFC PATCH v1 05/14] dt-bindings: clock: thead,th1520: Add support for Video Output subsystem
Date: Wed, 04 Dec 2024 12:21:11 -0800	[thread overview]
Message-ID: <1b05b11b2a8287c0ff4b6bdd079988c7.sboyd@kernel.org> (raw)
In-Reply-To: <07bfb02a-1df3-4a03-83bb-d7edc540739d@samsung.com>

Quoting Michal Wilczynski (2024-12-04 02:11:26)
> On 12/3/24 16:45, Krzysztof Kozlowski wrote:
> > On 03/12/2024 14:41, Michal Wilczynski wrote:
> 
> [1] - https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20Video%20Image%20Processing%20User%20Manual.pdf
> > 
> >> +      these registers reside in the same address space, access to
> >> +      them is coordinated through a shared syscon regmap provided by
> >> +      the specified syscon node.
> > 
> > Drop last sentence. syscon regmap is a Linux term, not hardware one.
> > 
> > Anyway, this needs to be constrained per variant.
> > 
> >> +
> >>    "#clock-cells":
> >>      const: 1
> >>      description:
> >> @@ -36,8 +51,6 @@ properties:
> >>  
> >>  required:
> >>    - compatible
> >> -  - reg
> > 
> > No, that's a clear NAK. You claim you have no address space but in the
> > same time you have address space via regmap.
> 
> I see your concern. The VOSYS subsystem's address space includes
> registers for various components, such as clock gates and reset
> controls, which are scattered throughout the address space as specified
> in the manual 4.4.1 [2]. Initially, I attempted to use a shared syscon
> regmap for access, but I realize this might not be the best approach.
> 
> To address this, I'll specify the 'reg' property in each node to define
> the address ranges explicitly fragmenting the address space for the VOSYS
> manually.
> 
> vosys_clk: clock-controller@ffef528050 {
>         compatible = "thead,th1520-clk-vo";
>         reg = <0xff 0xef528050 0x0 0x8>;
>         #clock-cells = <1>;
> };
> 
> pd: power-domain@ffef528000 {
>         compatible = "thead,th1520-pd";
>         reg = <0xff 0xef528000 0x0 0x8>;
>         #power-domain-cells = <1>;
> };

You should have one node:

    clock-controller@ffef528000 {
      compatible = "thead,th1520-vo";
      reg = <0xff 0xef528050 0x0 0x1a04>;
      #clock-cells = <1>;
      #power-domain-cells = <1>;
    };

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WARNING: multiple messages have this Message-ID (diff)
From: Stephen Boyd <sboyd@kernel.org>
To: Krzysztof Kozlowski <krzk@kernel.org>,
	Michal Wilczynski <m.wilczynski@samsung.com>,
	airlied@gmail.com, aou@eecs.berkeley.edu, conor+dt@kernel.org,
	drew@pdp7.com, frank.binns@imgtec.com, guoren@kernel.org,
	jassisinghbrar@gmail.com, jszhang@kernel.org, krzk+dt@kernel.org,
	m.szyprowski@samsung.com, maarten.lankhorst@linux.intel.com,
	matt.coster@imgtec.com, mripard@kernel.org,
	mturquette@baylibre.com, palmer@dabbelt.com,
	paul.walmsley@sifive.com, robh@kernel.org, simona@ffwll.ch,
	tzimmermann@suse.de, ulf.hansson@linaro.org, wefu@redhat.com
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org
Subject: Re: [RFC PATCH v1 05/14] dt-bindings: clock: thead, th1520: Add support for Video Output subsystem
Date: Wed, 04 Dec 2024 12:21:11 -0800	[thread overview]
Message-ID: <1b05b11b2a8287c0ff4b6bdd079988c7.sboyd@kernel.org> (raw)
In-Reply-To: <07bfb02a-1df3-4a03-83bb-d7edc540739d@samsung.com>

Quoting Michal Wilczynski (2024-12-04 02:11:26)
> On 12/3/24 16:45, Krzysztof Kozlowski wrote:
> > On 03/12/2024 14:41, Michal Wilczynski wrote:
> 
> [1] - https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20Video%20Image%20Processing%20User%20Manual.pdf
> > 
> >> +      these registers reside in the same address space, access to
> >> +      them is coordinated through a shared syscon regmap provided by
> >> +      the specified syscon node.
> > 
> > Drop last sentence. syscon regmap is a Linux term, not hardware one.
> > 
> > Anyway, this needs to be constrained per variant.
> > 
> >> +
> >>    "#clock-cells":
> >>      const: 1
> >>      description:
> >> @@ -36,8 +51,6 @@ properties:
> >>  
> >>  required:
> >>    - compatible
> >> -  - reg
> > 
> > No, that's a clear NAK. You claim you have no address space but in the
> > same time you have address space via regmap.
> 
> I see your concern. The VOSYS subsystem's address space includes
> registers for various components, such as clock gates and reset
> controls, which are scattered throughout the address space as specified
> in the manual 4.4.1 [2]. Initially, I attempted to use a shared syscon
> regmap for access, but I realize this might not be the best approach.
> 
> To address this, I'll specify the 'reg' property in each node to define
> the address ranges explicitly fragmenting the address space for the VOSYS
> manually.
> 
> vosys_clk: clock-controller@ffef528050 {
>         compatible = "thead,th1520-clk-vo";
>         reg = <0xff 0xef528050 0x0 0x8>;
>         #clock-cells = <1>;
> };
> 
> pd: power-domain@ffef528000 {
>         compatible = "thead,th1520-pd";
>         reg = <0xff 0xef528000 0x0 0x8>;
>         #power-domain-cells = <1>;
> };

You should have one node:

    clock-controller@ffef528000 {
      compatible = "thead,th1520-vo";
      reg = <0xff 0xef528050 0x0 0x1a04>;
      #clock-cells = <1>;
      #power-domain-cells = <1>;
    };

  reply	other threads:[~2024-12-04 20:21 UTC|newest]

Thread overview: 78+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20241203134148eucas1p1dd37e9cac92aada509d87f5178e337e8@eucas1p1.samsung.com>
2024-12-03 13:41 ` [RFC PATCH v1 00/14] Enable drm/imagination BXM-4-64 Support for LicheePi 4A Michal Wilczynski
2024-12-03 13:41   ` Michal Wilczynski
2024-12-03 13:41   ` [RFC PATCH v1 01/14] clk: thead: Refactor TH1520 clock driver to share common code Michal Wilczynski
2024-12-03 13:41     ` Michal Wilczynski
2024-12-03 19:56     ` Stephen Boyd
2024-12-03 19:56       ` Stephen Boyd
2024-12-04 13:54       ` Michal Wilczynski
2024-12-04 13:54         ` Michal Wilczynski
2024-12-05  7:31         ` Krzysztof Kozlowski
2024-12-05  7:31           ` Krzysztof Kozlowski
2024-12-03 13:41   ` [RFC PATCH v1 02/14] dt-bindings: clock: thead,th1520: Rename header file Michal Wilczynski
2024-12-03 13:41     ` Michal Wilczynski
2024-12-03 14:24     ` Rob Herring (Arm)
2024-12-03 14:24       ` Rob Herring (Arm)
2024-12-03 15:41     ` Krzysztof Kozlowski
2024-12-03 15:41       ` Krzysztof Kozlowski
2024-12-03 13:41   ` [RFC PATCH v1 03/14] clk: thead: Enable clock gates with regmaps Michal Wilczynski
2024-12-03 13:41     ` Michal Wilczynski
2024-12-03 13:41   ` [RFC PATCH v1 04/14] clk: thead: Add clock driver for TH1520 Video Output subsystem Michal Wilczynski
2024-12-03 13:41     ` Michal Wilczynski
2024-12-03 15:54     ` Krzysztof Kozlowski
2024-12-03 15:54       ` Krzysztof Kozlowski
2024-12-03 13:41   ` [RFC PATCH v1 05/14] dt-bindings: clock: thead,th1520: Add support for " Michal Wilczynski
2024-12-03 13:41     ` Michal Wilczynski
2024-12-03 14:24     ` Rob Herring (Arm)
2024-12-03 14:24       ` Rob Herring (Arm)
2024-12-03 15:45     ` Krzysztof Kozlowski
2024-12-03 15:45       ` Krzysztof Kozlowski
2024-12-04 10:11       ` Michal Wilczynski
2024-12-04 10:11         ` Michal Wilczynski
2024-12-04 20:21         ` Stephen Boyd [this message]
2024-12-04 20:21           ` [RFC PATCH v1 05/14] dt-bindings: clock: thead, th1520: " Stephen Boyd
2024-12-04 20:21           ` [RFC PATCH v1 05/14] dt-bindings: clock: thead,th1520: " Stephen Boyd
2024-12-04 20:22           ` Stephen Boyd
2024-12-04 20:22             ` [RFC PATCH v1 05/14] dt-bindings: clock: thead, th1520: " Stephen Boyd
2024-12-04 20:22             ` [RFC PATCH v1 05/14] dt-bindings: clock: thead,th1520: " Stephen Boyd
2024-12-05  7:28           ` Krzysztof Kozlowski
2024-12-05  7:28             ` Krzysztof Kozlowski
2024-12-05  7:27         ` Krzysztof Kozlowski
2024-12-05  7:27           ` Krzysztof Kozlowski
2024-12-03 13:41   ` [RFC PATCH v1 06/14] dt-bindings: clock: thead,th1520: Rename YAML schema file Michal Wilczynski
2024-12-03 13:41     ` Michal Wilczynski
2024-12-03 14:25     ` Rob Herring (Arm)
2024-12-03 14:25       ` Rob Herring (Arm)
2024-12-03 15:45     ` Krzysztof Kozlowski
2024-12-03 15:45       ` Krzysztof Kozlowski
2024-12-03 13:41   ` [RFC PATCH v1 07/14] soc: thead: power-domain: Add skeleton power-domain driver for TH1520 Michal Wilczynski
2024-12-03 13:41     ` Michal Wilczynski
2024-12-03 15:58     ` Krzysztof Kozlowski
2024-12-03 15:58       ` Krzysztof Kozlowski
2024-12-03 13:41   ` [RFC PATCH v1 08/14] dt-bindings: power: thead,th1520: Add support for power domains Michal Wilczynski
2024-12-03 13:41     ` Michal Wilczynski
2024-12-03 15:25     ` Rob Herring (Arm)
2024-12-03 15:25       ` Rob Herring (Arm)
2024-12-03 15:48     ` Krzysztof Kozlowski
2024-12-03 15:48       ` Krzysztof Kozlowski
2024-12-03 13:41   ` [RFC PATCH v1 09/14] riscv: Enable PM_GENERIC_DOMAINS for T-Head SoCs Michal Wilczynski
2024-12-03 13:41     ` Michal Wilczynski
2024-12-03 13:41   ` [RFC PATCH v1 10/14] drm/imagination: Add support for IMG BXM-4-64 GPU Michal Wilczynski
2024-12-03 13:41     ` Michal Wilczynski
2024-12-03 15:49     ` Krzysztof Kozlowski
2024-12-03 15:49       ` Krzysztof Kozlowski
2024-12-03 13:41   ` [RFC PATCH v1 11/14] drm/imagination: Enable PowerVR driver for RISC-V Michal Wilczynski
2024-12-03 13:41     ` Michal Wilczynski
2024-12-03 13:41   ` [RFC PATCH v1 12/14] riscv: dts: Add Video Output clock and syscon regmap nodes Michal Wilczynski
2024-12-03 13:41     ` Michal Wilczynski
2024-12-03 15:50     ` Krzysztof Kozlowski
2024-12-03 15:50       ` Krzysztof Kozlowski
2024-12-03 13:41   ` [RFC PATCH v1 13/14] riscv: dts: Introduce power domain node with simple-bus compatible Michal Wilczynski
2024-12-03 13:41     ` Michal Wilczynski
2024-12-03 15:52     ` Krzysztof Kozlowski
2024-12-03 15:52       ` Krzysztof Kozlowski
2024-12-04 10:34       ` Michal Wilczynski
2024-12-04 10:34         ` Michal Wilczynski
2024-12-03 13:41   ` [RFC PATCH v1 14/14] riscv: dts: Add GPU node to TH1520 device tree Michal Wilczynski
2024-12-03 13:41     ` Michal Wilczynski
2024-12-03 15:53     ` Krzysztof Kozlowski
2024-12-03 15:53       ` Krzysztof Kozlowski

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