From: Matthew Auld <matthew.auld@intel.com>
To: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>,
intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: paulo.r.zanoni@intel.com, jani.nikula@intel.com,
thomas.hellstrom@intel.com, daniel.vetter@intel.com,
christian.koenig@amd.com
Subject: Re: [Intel-gfx] [PATCH v4 12/17] drm/i915/vm_bind: Implement I915_GEM_EXECBUFFER3 ioctl
Date: Wed, 19 Oct 2022 16:20:49 +0100 [thread overview]
Message-ID: <1d48bd33-ea96-e753-eb82-12948baa4573@intel.com> (raw)
In-Reply-To: <20221018071630.3831-13-niranjana.vishwanathapura@intel.com>
On 18/10/2022 08:16, Niranjana Vishwanathapura wrote:
> Implement new execbuf3 ioctl (I915_GEM_EXECBUFFER3) which only
> works in vm_bind mode. The vm_bind mode only works with
> this new execbuf3 ioctl.
>
> The new execbuf3 ioctl will not have any list of objects to validate
> bind as all required objects binding would have been requested by the
> userspace before submitting the execbuf3.
>
> Legacy features like relocations etc are not supported by execbuf3.
>
> v2: Add more input validity checks.
> v3: batch_address is a VA (not an array) if num_batches=1,
> minor cleanup
> v4: replace vm->vm_bind_mode check with i915_gem_vm_is_vm_bind_mode()
>
> Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> .../gpu/drm/i915/gem/i915_gem_execbuffer3.c | 580 ++++++++++++++++++
> drivers/gpu/drm/i915/gem/i915_gem_ioctls.h | 2 +
> drivers/gpu/drm/i915/i915_driver.c | 1 +
> include/uapi/drm/i915_drm.h | 61 ++
> 5 files changed, 645 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 8d76bb888dc3..6a801684d569 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -150,6 +150,7 @@ gem-y += \
> gem/i915_gem_domain.o \
> gem/i915_gem_execbuffer_common.o \
> gem/i915_gem_execbuffer.o \
> + gem/i915_gem_execbuffer3.o \
> gem/i915_gem_internal.o \
> gem/i915_gem_object.o \
> gem/i915_gem_lmem.o \
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
> new file mode 100644
> index 000000000000..a9b4cc44bf66
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
> @@ -0,0 +1,580 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#include <linux/dma-resv.h>
> +#include <linux/uaccess.h>
> +
> +#include <drm/drm_syncobj.h>
> +
> +#include "gt/intel_context.h"
> +#include "gt/intel_gpu_commands.h"
> +#include "gt/intel_gt.h"
> +
> +#include "i915_drv.h"
> +#include "i915_gem_context.h"
> +#include "i915_gem_execbuffer_common.h"
> +#include "i915_gem_ioctls.h"
> +#include "i915_gem_vm_bind.h"
> +#include "i915_trace.h"
> +
> +#define __EXEC3_ENGINE_PINNED BIT_ULL(32)
> +#define __EXEC3_INTERNAL_FLAGS (~0ull << 32)
> +
> +/* Catch emission of unexpected errors for CI! */
> +#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
> +#undef EINVAL
> +#define EINVAL ({ \
> + DRM_DEBUG_DRIVER("EINVAL at %s:%d\n", __func__, __LINE__); \
> + 22; \
> +})
> +#endif
> +
> +/**
> + * DOC: User command execution with execbuf3 ioctl
> + *
> + * A VM in VM_BIND mode will not support older execbuf mode of binding.
> + * The execbuf ioctl handling in VM_BIND mode differs significantly from the
> + * older execbuf2 ioctl (See struct drm_i915_gem_execbuffer2).
> + * Hence, a new execbuf3 ioctl has been added to support VM_BIND mode. (See
> + * struct drm_i915_gem_execbuffer3). The execbuf3 ioctl will not accept any
> + * execlist. Hence, no support for implicit sync.
> + *
> + * The new execbuf3 ioctl only works in VM_BIND mode and the VM_BIND mode only
> + * works with execbuf3 ioctl for submission.
> + *
> + * The execbuf3 ioctl directly specifies the batch addresses instead of as
> + * object handles as in execbuf2 ioctl. The execbuf3 ioctl will also not
> + * support many of the older features like in/out/submit fences, fence array,
> + * default gem context etc. (See struct drm_i915_gem_execbuffer3).
> + *
> + * In VM_BIND mode, VA allocation is completely managed by the user instead of
> + * the i915 driver. Hence all VA assignment, eviction are not applicable in
> + * VM_BIND mode. Also, for determining object activeness, VM_BIND mode will not
> + * be using the i915_vma active reference tracking. It will instead check the
> + * dma-resv object's fence list for that.
> + *
> + * So, a lot of code supporting execbuf2 ioctl, like relocations, VA evictions,
> + * vma lookup table, implicit sync, vma active reference tracking etc., are not
> + * applicable for execbuf3 ioctl.
> + */
> +
> +/**
> + * struct i915_execbuffer - execbuf struct for execbuf3
> + * @i915: reference to the i915 instance we run on
> + * @file: drm file reference
> + * args: execbuf3 ioctl structure
> + * @gt: reference to the gt instance ioctl submitted for
> + * @context: logical state for the request
> + * @gem_context: callers context
> + * @requests: requests to be build
> + * @composite_fence: used for excl fence in dma_resv objects when > 1 BB submitted
> + * @ww: i915_gem_ww_ctx instance
> + * @num_batches: number of batches submitted
> + * @batch_addresses: addresses corresponds to the submitted batches
> + * @batches: references to the i915_vmas corresponding to the batches
> + */
Are we building/including the docs for this somewhere? Looks like we are
missing some stuff like @fences/@num_fences in the kernel-doc.
> +struct i915_execbuffer {
> + struct drm_i915_private *i915;
> + struct drm_file *file;
> + struct drm_i915_gem_execbuffer3 *args;
> +
> + struct intel_gt *gt;
> + struct intel_context *context;
> + struct i915_gem_context *gem_context;
> +
> + struct i915_request *requests[MAX_ENGINE_INSTANCE + 1];
> + struct dma_fence *composite_fence;
> +
> + struct i915_gem_ww_ctx ww;
> +
> + unsigned int num_batches;
> + u64 batch_addresses[MAX_ENGINE_INSTANCE + 1];
> + struct i915_vma *batches[MAX_ENGINE_INSTANCE + 1];
> +
> + struct eb_fence *fences;
> + u64 num_fences;
> +};
> +
> +static void eb_unpin_engine(struct i915_execbuffer *eb);
> +
> +static int eb_select_context(struct i915_execbuffer *eb)
> +{
> + struct i915_gem_context *ctx;
> +
> + ctx = i915_gem_context_lookup(eb->file->driver_priv, eb->args->ctx_id);
> + if (IS_ERR(ctx))
> + return PTR_ERR(ctx);
> +
> + if (!i915_gem_vm_is_vm_bind_mode(ctx->vm)) {
> + i915_gem_context_put(ctx);
> + return -EOPNOTSUPP;
> + }
It might be good to also ban recoverable context support somewhere for
eb3. It should be non-recoverable ctx or nothing for new stuff it seems
(VLK-40081).
WARNING: multiple messages have this Message-ID (diff)
From: Matthew Auld <matthew.auld@intel.com>
To: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>,
intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: matthew.brost@intel.com, paulo.r.zanoni@intel.com,
tvrtko.ursulin@intel.com, jani.nikula@intel.com,
lionel.g.landwerlin@intel.com, thomas.hellstrom@intel.com,
jason@jlekstrand.net, andi.shyti@linux.intel.com,
daniel.vetter@intel.com, christian.koenig@amd.com
Subject: Re: [PATCH v4 12/17] drm/i915/vm_bind: Implement I915_GEM_EXECBUFFER3 ioctl
Date: Wed, 19 Oct 2022 16:20:49 +0100 [thread overview]
Message-ID: <1d48bd33-ea96-e753-eb82-12948baa4573@intel.com> (raw)
In-Reply-To: <20221018071630.3831-13-niranjana.vishwanathapura@intel.com>
On 18/10/2022 08:16, Niranjana Vishwanathapura wrote:
> Implement new execbuf3 ioctl (I915_GEM_EXECBUFFER3) which only
> works in vm_bind mode. The vm_bind mode only works with
> this new execbuf3 ioctl.
>
> The new execbuf3 ioctl will not have any list of objects to validate
> bind as all required objects binding would have been requested by the
> userspace before submitting the execbuf3.
>
> Legacy features like relocations etc are not supported by execbuf3.
>
> v2: Add more input validity checks.
> v3: batch_address is a VA (not an array) if num_batches=1,
> minor cleanup
> v4: replace vm->vm_bind_mode check with i915_gem_vm_is_vm_bind_mode()
>
> Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> .../gpu/drm/i915/gem/i915_gem_execbuffer3.c | 580 ++++++++++++++++++
> drivers/gpu/drm/i915/gem/i915_gem_ioctls.h | 2 +
> drivers/gpu/drm/i915/i915_driver.c | 1 +
> include/uapi/drm/i915_drm.h | 61 ++
> 5 files changed, 645 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 8d76bb888dc3..6a801684d569 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -150,6 +150,7 @@ gem-y += \
> gem/i915_gem_domain.o \
> gem/i915_gem_execbuffer_common.o \
> gem/i915_gem_execbuffer.o \
> + gem/i915_gem_execbuffer3.o \
> gem/i915_gem_internal.o \
> gem/i915_gem_object.o \
> gem/i915_gem_lmem.o \
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
> new file mode 100644
> index 000000000000..a9b4cc44bf66
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
> @@ -0,0 +1,580 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#include <linux/dma-resv.h>
> +#include <linux/uaccess.h>
> +
> +#include <drm/drm_syncobj.h>
> +
> +#include "gt/intel_context.h"
> +#include "gt/intel_gpu_commands.h"
> +#include "gt/intel_gt.h"
> +
> +#include "i915_drv.h"
> +#include "i915_gem_context.h"
> +#include "i915_gem_execbuffer_common.h"
> +#include "i915_gem_ioctls.h"
> +#include "i915_gem_vm_bind.h"
> +#include "i915_trace.h"
> +
> +#define __EXEC3_ENGINE_PINNED BIT_ULL(32)
> +#define __EXEC3_INTERNAL_FLAGS (~0ull << 32)
> +
> +/* Catch emission of unexpected errors for CI! */
> +#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
> +#undef EINVAL
> +#define EINVAL ({ \
> + DRM_DEBUG_DRIVER("EINVAL at %s:%d\n", __func__, __LINE__); \
> + 22; \
> +})
> +#endif
> +
> +/**
> + * DOC: User command execution with execbuf3 ioctl
> + *
> + * A VM in VM_BIND mode will not support older execbuf mode of binding.
> + * The execbuf ioctl handling in VM_BIND mode differs significantly from the
> + * older execbuf2 ioctl (See struct drm_i915_gem_execbuffer2).
> + * Hence, a new execbuf3 ioctl has been added to support VM_BIND mode. (See
> + * struct drm_i915_gem_execbuffer3). The execbuf3 ioctl will not accept any
> + * execlist. Hence, no support for implicit sync.
> + *
> + * The new execbuf3 ioctl only works in VM_BIND mode and the VM_BIND mode only
> + * works with execbuf3 ioctl for submission.
> + *
> + * The execbuf3 ioctl directly specifies the batch addresses instead of as
> + * object handles as in execbuf2 ioctl. The execbuf3 ioctl will also not
> + * support many of the older features like in/out/submit fences, fence array,
> + * default gem context etc. (See struct drm_i915_gem_execbuffer3).
> + *
> + * In VM_BIND mode, VA allocation is completely managed by the user instead of
> + * the i915 driver. Hence all VA assignment, eviction are not applicable in
> + * VM_BIND mode. Also, for determining object activeness, VM_BIND mode will not
> + * be using the i915_vma active reference tracking. It will instead check the
> + * dma-resv object's fence list for that.
> + *
> + * So, a lot of code supporting execbuf2 ioctl, like relocations, VA evictions,
> + * vma lookup table, implicit sync, vma active reference tracking etc., are not
> + * applicable for execbuf3 ioctl.
> + */
> +
> +/**
> + * struct i915_execbuffer - execbuf struct for execbuf3
> + * @i915: reference to the i915 instance we run on
> + * @file: drm file reference
> + * args: execbuf3 ioctl structure
> + * @gt: reference to the gt instance ioctl submitted for
> + * @context: logical state for the request
> + * @gem_context: callers context
> + * @requests: requests to be build
> + * @composite_fence: used for excl fence in dma_resv objects when > 1 BB submitted
> + * @ww: i915_gem_ww_ctx instance
> + * @num_batches: number of batches submitted
> + * @batch_addresses: addresses corresponds to the submitted batches
> + * @batches: references to the i915_vmas corresponding to the batches
> + */
Are we building/including the docs for this somewhere? Looks like we are
missing some stuff like @fences/@num_fences in the kernel-doc.
> +struct i915_execbuffer {
> + struct drm_i915_private *i915;
> + struct drm_file *file;
> + struct drm_i915_gem_execbuffer3 *args;
> +
> + struct intel_gt *gt;
> + struct intel_context *context;
> + struct i915_gem_context *gem_context;
> +
> + struct i915_request *requests[MAX_ENGINE_INSTANCE + 1];
> + struct dma_fence *composite_fence;
> +
> + struct i915_gem_ww_ctx ww;
> +
> + unsigned int num_batches;
> + u64 batch_addresses[MAX_ENGINE_INSTANCE + 1];
> + struct i915_vma *batches[MAX_ENGINE_INSTANCE + 1];
> +
> + struct eb_fence *fences;
> + u64 num_fences;
> +};
> +
> +static void eb_unpin_engine(struct i915_execbuffer *eb);
> +
> +static int eb_select_context(struct i915_execbuffer *eb)
> +{
> + struct i915_gem_context *ctx;
> +
> + ctx = i915_gem_context_lookup(eb->file->driver_priv, eb->args->ctx_id);
> + if (IS_ERR(ctx))
> + return PTR_ERR(ctx);
> +
> + if (!i915_gem_vm_is_vm_bind_mode(ctx->vm)) {
> + i915_gem_context_put(ctx);
> + return -EOPNOTSUPP;
> + }
It might be good to also ban recoverable context support somewhere for
eb3. It should be non-recoverable ctx or nothing for new stuff it seems
(VLK-40081).
next prev parent reply other threads:[~2022-10-19 15:21 UTC|newest]
Thread overview: 92+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-18 7:16 [Intel-gfx] [PATCH v4 00/17] drm/i915/vm_bind: Add VM_BIND functionality Niranjana Vishwanathapura
2022-10-18 7:16 ` Niranjana Vishwanathapura
2022-10-18 7:16 ` [Intel-gfx] [PATCH v4 01/17] drm/i915/vm_bind: Expose vm lookup function Niranjana Vishwanathapura
2022-10-18 7:16 ` Niranjana Vishwanathapura
2022-10-18 7:16 ` [Intel-gfx] [PATCH v4 02/17] drm/i915/vm_bind: Add __i915_sw_fence_await_reservation() Niranjana Vishwanathapura
2022-10-18 7:16 ` Niranjana Vishwanathapura
2022-10-18 7:16 ` [Intel-gfx] [PATCH v4 03/17] drm/i915/vm_bind: Expose i915_gem_object_max_page_size() Niranjana Vishwanathapura
2022-10-18 7:16 ` Niranjana Vishwanathapura
2022-10-18 7:16 ` [Intel-gfx] [PATCH v4 04/17] drm/i915/vm_bind: Add support to create persistent vma Niranjana Vishwanathapura
2022-10-18 7:16 ` Niranjana Vishwanathapura
2022-10-18 7:16 ` [Intel-gfx] [PATCH v4 05/17] drm/i915/vm_bind: Implement bind and unbind of object Niranjana Vishwanathapura
2022-10-18 7:16 ` Niranjana Vishwanathapura
2022-10-18 7:16 ` [Intel-gfx] [PATCH v4 06/17] drm/i915/vm_bind: Support for VM private BOs Niranjana Vishwanathapura
2022-10-18 7:16 ` Niranjana Vishwanathapura
2022-10-18 7:16 ` [Intel-gfx] [PATCH v4 07/17] drm/i915/vm_bind: Add support to handle object evictions Niranjana Vishwanathapura
2022-10-18 7:16 ` Niranjana Vishwanathapura
2022-10-18 7:16 ` [Intel-gfx] [PATCH v4 08/17] drm/i915/vm_bind: Support persistent vma activeness tracking Niranjana Vishwanathapura
2022-10-18 7:16 ` Niranjana Vishwanathapura
2022-10-18 7:16 ` [Intel-gfx] [PATCH v4 09/17] drm/i915/vm_bind: Add out fence support Niranjana Vishwanathapura
2022-10-18 7:16 ` Niranjana Vishwanathapura
2022-10-18 15:28 ` [Intel-gfx] " Matthew Auld
2022-10-18 15:28 ` Matthew Auld
2022-10-19 2:43 ` [Intel-gfx] " Niranjana Vishwanathapura
2022-10-19 2:43 ` Niranjana Vishwanathapura
2022-10-19 14:24 ` [Intel-gfx] " Matthew Auld
2022-10-19 14:24 ` Matthew Auld
2022-10-18 7:16 ` [Intel-gfx] [PATCH v4 10/17] drm/i915/vm_bind: Abstract out common execbuf functions Niranjana Vishwanathapura
2022-10-18 7:16 ` Niranjana Vishwanathapura
2022-10-18 7:16 ` [Intel-gfx] [PATCH v4 11/17] drm/i915/vm_bind: Use common execbuf functions in execbuf path Niranjana Vishwanathapura
2022-10-18 7:16 ` Niranjana Vishwanathapura
2022-10-18 7:16 ` [Intel-gfx] [PATCH v4 12/17] drm/i915/vm_bind: Implement I915_GEM_EXECBUFFER3 ioctl Niranjana Vishwanathapura
2022-10-18 7:16 ` Niranjana Vishwanathapura
2022-10-18 17:30 ` [Intel-gfx] " Matthew Auld
2022-10-18 17:30 ` Matthew Auld
2022-10-19 4:10 ` [Intel-gfx] " Niranjana Vishwanathapura
2022-10-19 4:10 ` Niranjana Vishwanathapura
2022-10-19 15:20 ` Matthew Auld [this message]
2022-10-19 15:20 ` Matthew Auld
2022-10-19 19:03 ` [Intel-gfx] " Niranjana Vishwanathapura
2022-10-19 19:03 ` Niranjana Vishwanathapura
2022-10-18 7:16 ` [Intel-gfx] [PATCH v4 13/17] drm/i915/vm_bind: Update i915_vma_verify_bind_complete() Niranjana Vishwanathapura
2022-10-18 7:16 ` Niranjana Vishwanathapura
2022-10-19 16:07 ` [Intel-gfx] " Matthew Auld
2022-10-19 16:07 ` Matthew Auld
2022-10-19 18:28 ` [Intel-gfx] " Niranjana Vishwanathapura
2022-10-19 18:28 ` Niranjana Vishwanathapura
2022-10-20 9:16 ` [Intel-gfx] " Matthew Auld
2022-10-20 9:16 ` Matthew Auld
2022-10-20 16:51 ` [Intel-gfx] " Niranjana Vishwanathapura
2022-10-20 16:51 ` Niranjana Vishwanathapura
2022-10-20 17:06 ` [Intel-gfx] " Matthew Auld
2022-10-20 17:06 ` Matthew Auld
2022-10-18 7:16 ` [Intel-gfx] [PATCH v4 14/17] drm/i915/vm_bind: Expose i915_request_await_bind() Niranjana Vishwanathapura
2022-10-18 7:16 ` Niranjana Vishwanathapura
2022-10-19 16:09 ` [Intel-gfx] " Matthew Auld
2022-10-19 16:09 ` Matthew Auld
2022-10-19 18:04 ` [Intel-gfx] " Niranjana Vishwanathapura
2022-10-19 18:04 ` Niranjana Vishwanathapura
2022-10-18 7:16 ` [Intel-gfx] [PATCH v4 15/17] drm/i915/vm_bind: Handle persistent vmas in execbuf3 Niranjana Vishwanathapura
2022-10-18 7:16 ` Niranjana Vishwanathapura
2022-10-18 18:01 ` [Intel-gfx] " Matthew Auld
2022-10-18 18:01 ` Matthew Auld
2022-10-18 20:20 ` [Intel-gfx] " Niranjana Vishwanathapura
2022-10-18 20:20 ` Niranjana Vishwanathapura
2022-10-19 5:17 ` [Intel-gfx] " Niranjana Vishwanathapura
2022-10-20 16:33 ` Matthew Auld
2022-10-20 16:33 ` Matthew Auld
2022-10-20 16:39 ` [Intel-gfx] " Matthew Auld
2022-10-20 16:39 ` Matthew Auld
2022-10-20 17:06 ` [Intel-gfx] " Niranjana Vishwanathapura
2022-10-20 17:06 ` Niranjana Vishwanathapura
2022-10-18 7:16 ` [Intel-gfx] [PATCH v4 16/17] drm/i915/vm_bind: userptr dma-resv changes Niranjana Vishwanathapura
2022-10-18 7:16 ` Niranjana Vishwanathapura
2022-10-20 14:27 ` [Intel-gfx] " Andi Shyti
2022-10-20 14:27 ` Andi Shyti
2022-10-20 19:05 ` [Intel-gfx] " Niranjana Vishwanathapura
2022-10-20 19:05 ` Niranjana Vishwanathapura
2022-10-20 21:20 ` [Intel-gfx] " Niranjana Vishwanathapura
2022-10-20 16:29 ` Matthew Auld
2022-10-20 16:29 ` Matthew Auld
2022-10-20 16:39 ` [Intel-gfx] " Niranjana Vishwanathapura
2022-10-20 16:39 ` Niranjana Vishwanathapura
2022-10-18 7:16 ` [Intel-gfx] [PATCH v4 17/17] drm/i915/vm_bind: Add uapi for user to enable vm_bind_mode Niranjana Vishwanathapura
2022-10-18 7:16 ` Niranjana Vishwanathapura
2022-10-18 16:03 ` [Intel-gfx] " Matthew Auld
2022-10-18 16:03 ` Matthew Auld
2022-10-18 16:48 ` [Intel-gfx] " Niranjana Vishwanathapura
2022-10-18 16:48 ` Niranjana Vishwanathapura
2022-10-18 7:55 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/vm_bind: Add VM_BIND functionality (rev7) Patchwork
2022-10-18 7:55 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-10-18 8:06 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-10-19 1:25 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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