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From: Michael Walle <michael@walle.cc>
To: Jungseung Lee <js07.lee@samsung.com>
Cc: js07.lee@gmail.com, linux-mtd@lists.infradead.org,
	vigneshr@ti.com, Tudor.Ambarus@microchip.com
Subject: Re: [PATCH v3 2/3] mtd: spi-nor: add 4bit block protection support
Date: Wed, 19 Feb 2020 12:08:21 +0100	[thread overview]
Message-ID: <1dea94d182249f9640e2cfb2f7ef402a@walle.cc> (raw)
In-Reply-To: <ed9ae10ab3be4da90779cb6f8d6c6cf1e9fbc968.camel@samsung.com>

Am 2020-02-19 11:50, schrieb Jungseung Lee:
> Hi, Tudor and all
> 
> 2020-02-10 (Mon), 11:26 +0000, Tudor.Ambarus@microchip.com:
> We could also find a few flashes that does not following the overall
> logic. For example, "en25qh256" and "en25qh16" which was manufactured
> by EON. They are always following way (2) no matter what the number of
> slot is. It seems that it could be handled like below with custom hook
> later.

For these two flashes, BP3 is just the TB bit. So it should already work 
with the current logic.

-michael


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  reply	other threads:[~2020-02-19 11:08 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20200113055910epcas1p4f97dfeb465b00d66649d6321cffc7b5a@epcas1p4.samsung.com>
2020-01-13  5:59 ` [PATCH v3 1/3] mtd: spi-nor: introduce SR_BP_SHIFT define Jungseung Lee
2020-01-13  5:59   ` [PATCH v3 2/3] mtd: spi-nor: add 4bit block protection support Jungseung Lee
2020-01-14 10:49     ` Tudor.Ambarus
2020-01-17 15:06       ` Jungseung Lee
2020-01-22 11:42         ` Jungseung Lee
2020-01-22 14:31           ` Tudor.Ambarus
2020-01-22 17:14             ` Michael Walle
2020-01-23  3:59               ` Jungseung Lee
2020-01-23  8:15                 ` Michael Walle
2020-02-11  7:52         ` chenxiang (M)
2020-03-04  5:20           ` Jungseung Lee
2020-03-04  8:36             ` chenxiang (M)
2020-03-07  7:40               ` Jungseung Lee
2020-01-22 19:36     ` Michael Walle
2020-01-23  6:22       ` Jungseung Lee
2020-01-23  8:10         ` Michael Walle
2020-01-23  8:53           ` Jungseung Lee
2020-01-23  9:31             ` Michael Walle
2020-01-28 11:01               ` Jungseung Lee
2020-01-28 12:29                 ` [SPAM] " Michael Walle
2020-01-30  8:17                   ` Jungseung Lee
2020-01-30  8:36                     ` [SPAM] " Michael Walle
2020-01-30 10:07                       ` Jungseung Lee
2020-02-03 13:56                     ` Vignesh Raghavendra
2020-02-03 14:38                       ` [SPAM] " Michael Walle
2020-02-03 14:58                         ` Jungseung Lee
2020-02-03 17:31                         ` Vignesh Raghavendra
2020-02-07 12:17                       ` Tudor.Ambarus
2020-02-10  8:33                         ` Michael Walle
2020-02-10  9:47                           ` Tudor.Ambarus
2020-02-10  9:59                             ` Tudor.Ambarus
2020-02-10 10:40                               ` Michael Walle
2020-02-10 11:27                                 ` Tudor.Ambarus
2020-02-10 12:14                                   ` Michael Walle
2020-02-10 15:50                                     ` Tudor.Ambarus
2020-02-10 10:29                             ` Michael Walle
2020-02-10 11:26                               ` Tudor.Ambarus
2020-02-19 10:50                                 ` Jungseung Lee
2020-02-19 11:08                                   ` Michael Walle [this message]
2020-02-19 11:23                                     ` Jungseung Lee
2020-02-19 11:36                                       ` Michael Walle
2020-02-20 19:09                                   ` Michael Walle
2020-02-21  9:30                                     ` Tudor.Ambarus
2020-02-25  8:20                                       ` Tudor.Ambarus
2020-02-25  9:25                                         ` Jungseung Lee
2020-01-13  5:59   ` [PATCH v3 3/3] mtd: spi-nor: support lock/unlock for a few Micron chips Jungseung Lee
2020-01-13 12:30     ` John Garry
2020-01-13 12:40       ` Jungseung Lee
2020-01-13 12:45       ` Jungseung Lee
2020-01-13 13:00         ` John Garry
2020-02-17  0:18   ` [PATCH v3 1/3] mtd: spi-nor: introduce SR_BP_SHIFT define Tudor.Ambarus

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