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From: 潘庆霖 <panqinglin2020@iscas.ac.cn>
To: "Jisheng Zhang" <jszhang@kernel.org>
Cc: palmer@dabbelt.com, linux-riscv@lists.infradead.org,
	jeff@riscv.org,  xuyinan@ict.ac.cn
Subject: Re: Re: [PATCH v2 1/4] riscv, mm: detect svnapot cpu support at runtime
Date: Sat, 16 Jul 2022 21:42:26 +0800 (GMT+08:00)	[thread overview]
Message-ID: <1e77fd92.12c97.182073f0555.Coremail.panqinglin2020@iscas.ac.cn> (raw)
In-Reply-To: <YtKwjmbQmIMm4gEo@xhacker>

&gt; &gt;  
&gt; &gt; +config SVNAPOT
&gt; &gt; + bool "Svnapot support"
&gt; 
&gt; Do we add an config opition for each isa extension? That's not
&gt; necessary. I think we'd better remove this CONFIG option and keep
&gt; unified Image in mind.
&gt; 

I am also not very sure about necessity of this. Maybe we should allow user to disable
Svnapot support manually? As this support may introduce extra overhead in functions
like pte_pfn. So should such option be reserved for setting it off manually? If it should not,
I will remove it in a newer version.

&gt; &gt; diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
&gt; &gt; index 9e2888dbb5b1..84ad32075637 100644
&gt; &gt; --- a/arch/riscv/include/asm/errata_list.h
&gt; &gt; +++ b/arch/riscv/include/asm/errata_list.h
&gt; &gt; @@ -20,7 +20,8 @@
&gt; &gt;  #endif
&gt; &gt;  
&gt; &gt;  #define CPUFEATURE_SVPBMT 0
&gt; &gt; -#define CPUFEATURE_NUMBER 1
&gt; &gt; +#define CPUFEATURE_SVNAPOT 1
&gt; &gt; +#define CPUFEATURE_NUMBER 2
&gt; &gt;  
&gt; &gt;  #ifdef __ASSEMBLY__
&gt; &gt;  
&gt; &gt; @@ -93,6 +94,27 @@ asm volatile(ALTERNATIVE(      \
&gt; &gt;  #define ALT_THEAD_PMA(_val)
&gt; &gt;  #endif
&gt; &gt;  
&gt; &gt; +#define ALT_SVNAPOT(_val)      \
&gt; 
&gt; I believe SVNAPOT can be supported w/o ALTERNATIVE, static key mechanism
&gt; would be much simpler.
&gt;

Thanks for the hint, will implement it with static key mechanism in a newer version.

Thanks,
Qinglin

&gt; &gt; +asm(ALTERNATIVE("li %0, 0", "li %0, 1", 0,    \
&gt; &gt; +  CPUFEATURE_SVNAPOT, CONFIG_SVNAPOT)   \
&gt; &gt; +  : "=r"(_val) :)
&gt; &gt; +
&gt; &gt; +#define ALT_SVNAPOT_PTE_PFN(_val, _napot_shift, _pfn_mask, _pfn_shift) \
&gt; &gt; +asm(ALTERNATIVE("and %0, %1, %2\n\t"     \
&gt; &gt; +  "srli %0, %0, %3\n\t"     \
&gt; &gt; +  "nop\n\tnop\n\tnop",     \
&gt; &gt; +  "srli t3, %1, %4\n\t"     \
&gt; &gt; +  "and %0, %1, %2\n\t"     \
&gt; &gt; +  "srli %0, %0, %3\n\t"     \
&gt; &gt; +  "sub  t4, %0, t3\n\t"     \
&gt; &gt; +  "and  %0, %0, t4",     \
&gt; &gt; +  0, CPUFEATURE_SVNAPOT, CONFIG_SVNAPOT)   \
&gt; &gt; +  : "+r"(_val)      \
&gt; &gt; +  : "r"(_val),      \
&gt; &gt; +    "r"(_pfn_mask),     \
&gt; &gt; +    "i"(_pfn_shift),     \
&gt; &gt; +    "i"(_napot_shift))
&gt; &gt; +
&gt; &gt;  #endif /* __ASSEMBLY__ */
&gt; &gt;  
&gt; &gt;  #endif


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  parent reply	other threads:[~2022-07-16 13:42 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-16  8:56 [PATCH v2 0/4] riscv: mm: add Svnapot support panqinglin2020
2022-07-16  8:56 ` [PATCH v2 1/4] riscv, mm: detect svnapot cpu support at runtime panqinglin2020
2022-07-16 12:35   ` Jisheng Zhang
2022-07-16 13:33     ` Conor.Dooley
2022-07-16 13:41       ` 潘庆霖
2022-07-16 13:51         ` Conor.Dooley
2022-07-16 13:42     ` 潘庆霖 [this message]
2022-07-16  8:56 ` [PATCH v2 2/4] mm: support Svnapot in physical page linear-mapping panqinglin2020
2022-07-16  8:56 ` [PATCH v2 3/4] mm: support Svnapot in hugetlb page panqinglin2020
2022-07-16  8:56 ` [PATCH v2 4/4] mm: support Svnapot in huge vmap panqinglin2020

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