Re: [RFC PATCH] x86/intel: Add recent CPU models model-specific LBRs

[Jan Beulich <jbeulich@suse.com>]

On 26.03.2026 11:35, Tu Dinh wrote:
> On 26/03/2026 11:21, Teddy Astie wrote:
>> Add all CPU models that supports these MSR as they are defined in February 2026 SDM.
>> It uses the same list that span from Skylake to latest CPU models as a part of
>>
>>      MSRs in the 6th—13th generation Intel® Core™ processors,
>>      1st—5th generation Intel® Xeon® Scalable processor families,
>>      Intel® Core™ Ultra 7 processors, 8th generation Intel® Core™ i3
>>      processors, Intel® Xeon® E processors, Intel® Xeon® 6 P-Core
>>      processors, Intel® Xeon® 6 E-Core processors, and Intel® Series 2
>>      Core™ Ultra processors
>>
>> Signed-off-by: Teddy Astie <teddy.astie@vates.tech>
>> ---
>> Currently, none of these MSR are exposed on these CPUs, leading to BSOD [1]
>> in Windows when it is supposedly trying to debug some program.
>>
>> I guess [2] is also caused by these missing MSRs.
>>
>> [1] https://xcp-ng.org/forum/topic/12008/application-on-vm-causing-bsod
>> [2] https://lore.kernel.org/xen-devel/ced16fca-3b55-40a1-a7e2-ffadd9707394@vates.tech/
>>
>>   xen/arch/x86/hvm/vmx/vmx.c | 16 ++++++++++++++++
>>   1 file changed, 16 insertions(+)
>>
> 
> I don't think CPU models with architectural LBRs should be stuffed 
> together with the model-specific ones instead of having their own case.

I agree. We want to at least determine (or even enforce) how many LBRs
are accessible. After all we can't be sure the DEPTH field hasn't been
altered before we gained control.

Beyond that, because arch-LBR enabling is a significant effort, I guess
using the existing machinery for the time being might be okay.

> With that said, short of fully implementing arch LBR, it might make 
> sense to at least stub out the LER MSRs to allow Windows to read them 
> without crashing, as certain versions of Windows use LER MSR indexes 
> without checking the arch LBR CPUID bit.

This would be too Windows-centric for my taste.

Jan