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* [PATCH] ARM: dts: at91: sama7g5ek: Align the impedance of the QSPI0's HSIO and PCB lines
@ 2022-04-08  9:10 Tudor Ambarus
  2022-04-27  6:08 ` Eugen.Hristev
  0 siblings, 1 reply; 14+ messages in thread
From: Tudor Ambarus @ 2022-04-08  9:10 UTC (permalink / raw)
  To: Eugen.Hristev; +Cc: u-boot, Tudor Ambarus, Mihai Sain

The impedance of the QSPI PCB lines on the sama7g5ek is 50 Ohms.
Align the output impedance of the QSPI0 HSIOs by setting a medium drive
strength which corresponds to an impedance of 56 Ohms when VDD is in the
3.0V - 3.6V range. The high drive strength setting corresponds to an
output impedance of 42 Ohms on the QSPI0 HSIOs.
This is just a fine tunning. The memory that we have populated on sama7g5ek
works fine even with high drive strength, but it's better to adjust it and
use medium instead, in case some other flashes with higher frequencies are
tested.

Suggested-by: Mihai Sain <mihai.sain@microchip.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
 arch/arm/dts/at91-sama7g5ek.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/at91-sama7g5ek.dts b/arch/arm/dts/at91-sama7g5ek.dts
index 5313c6d160..ee46112b08 100644
--- a/arch/arm/dts/at91-sama7g5ek.dts
+++ b/arch/arm/dts/at91-sama7g5ek.dts
@@ -667,7 +667,7 @@
 			 <PIN_PB21__QSPI0_INT>;
 		bias-disable;
 		slew-rate = <0>;
-		atmel,drive-strength = <ATMEL_PIO_DRVSTR_HI>;
+		atmel,drive-strength = <ATMEL_PIO_DRVSTR_ME>;
 	};
 
 	pinctrl_sdmmc0_default: sdmmc0_default {
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 14+ messages in thread
* [PATCH] ARM: dts: at91: sama7g5ek: Align the impedance of the QSPI0's HSIO and PCB lines
@ 2022-04-06 13:05 ` Tudor Ambarus
  0 siblings, 0 replies; 14+ messages in thread
From: Tudor Ambarus @ 2022-04-06 13:05 UTC (permalink / raw)
  To: nicolas.ferre, claudiu.beznea
  Cc: alexandre.belloni, devicetree, linux-arm-kernel, linux-kernel,
	Tudor Ambarus, Mihai Sain

The impedance of the QSPI PCB lines on the sama7g5ek is 50 Ohms.
Align the output impedance of the QSPI0 HSIOs by setting a medium drive
strength which corresponds to an impedance of 56 Ohms when VDD is in the
3.0V - 3.6V range. The high drive strength setting corresponds to an
output impedance of 42 Ohms on the QSPI0 HSIOs.

Suggested-by: Mihai Sain <mihai.sain@microchip.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
 arch/arm/boot/dts/at91-sama7g5ek.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/at91-sama7g5ek.dts b/arch/arm/boot/dts/at91-sama7g5ek.dts
index 08685a10eda1..8f9643170ba3 100644
--- a/arch/arm/boot/dts/at91-sama7g5ek.dts
+++ b/arch/arm/boot/dts/at91-sama7g5ek.dts
@@ -655,7 +655,7 @@ pinctrl_qspi: qspi {
 			 <PIN_PB21__QSPI0_INT>;
 		bias-disable;
 		slew-rate = <0>;
-		atmel,drive-strength = <ATMEL_PIO_DRVSTR_HI>;
+		atmel,drive-strength = <ATMEL_PIO_DRVSTR_ME>;
 	};
 
 	pinctrl_sdmmc0_default: sdmmc0_default {
-- 
2.25.1


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^ permalink raw reply related	[flat|nested] 14+ messages in thread

end of thread, other threads:[~2022-04-27  6:08 UTC | newest]

Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-04-08  9:10 [PATCH] ARM: dts: at91: sama7g5ek: Align the impedance of the QSPI0's HSIO and PCB lines Tudor Ambarus
2022-04-27  6:08 ` Eugen.Hristev
  -- strict thread matches above, loose matches on Subject: below --
2022-04-06 13:05 Tudor Ambarus
2022-04-06 13:05 ` Tudor Ambarus
2022-04-07  6:26 ` Claudiu.Beznea
2022-04-07  6:26   ` Claudiu.Beznea
2022-04-07  7:51   ` Tudor.Ambarus
2022-04-07  7:51     ` Tudor.Ambarus
2022-04-07  8:24     ` Claudiu.Beznea
2022-04-07  8:24       ` Claudiu.Beznea
2022-04-13 12:40 ` Nicolas Ferre
2022-04-13 12:40   ` Nicolas Ferre
2022-04-13 12:43 ` Nicolas Ferre
2022-04-13 12:43   ` Nicolas Ferre

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