R5000SC

[Randall Craig <randall@suse.com>]

I think from the faq that the R5000SC is not supported:
---Snip----
Not supported are R4000MC and R4400MC CPUs (that is multiprocessor
systems) as well as R5000 systems with a CPU controlled second level
cache. This means where the cache is controlled by the R5000 itself in
contrast to some external external cache controller. The difference is
important because, unlike other systems, especially PCs, on MIPS the
cache is architecturally visible and needs to be controlled by
software.
---Snap---

The machine seems seems to have Secondary unified cache.  Could anyone
confirm that this machine is not supported.


Here is some more info, I do not have access to the machine.


     1 180 MHZ IP22 Processor
     FPU: MIPS R5000 Floating Point Coprocessor Revision: 1.0
     CPU: MIPS R5000 Processor Chip Revision: 2.1
     On-board serial ports: 2
     On-board bi-directional parallel port
     Data cache size: 32 Kbytes
     Instruction cache size: 32 Kbytes
     Secondary unified instruction/data cache size: 512 Kbytes on
     Processor 0


-- 
Randall H. Craig
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