R5000SC

R5000SC

[Randall Craig]

I think from the faq that the R5000SC is not supported:
---Snip----
Not supported are R4000MC and R4400MC CPUs (that is multiprocessor
systems) as well as R5000 systems with a CPU controlled second level
cache. This means where the cache is controlled by the R5000 itself in
contrast to some external external cache controller. The difference is
important because, unlike other systems, especially PCs, on MIPS the
cache is architecturally visible and needs to be controlled by
software.
---Snap---

The machine seems seems to have Secondary unified cache.  Could anyone
confirm that this machine is not supported.


Here is some more info, I do not have access to the machine.


     1 180 MHZ IP22 Processor
     FPU: MIPS R5000 Floating Point Coprocessor Revision: 1.0
     CPU: MIPS R5000 Processor Chip Revision: 2.1
     On-board serial ports: 2
     On-board bi-directional parallel port
     Data cache size: 32 Kbytes
     Instruction cache size: 32 Kbytes
     Secondary unified instruction/data cache size: 512 Kbytes on
     Processor 0


-- 
Randall H. Craig
SuSE Inc.,                 Tel:   +1-510-628-3380 (ext. 5004)
580 Second St., Suite 210  Fax:   +1-510-835-3381
Oakland CA 94607           Email: randall@suse.com
USA                        WWW:   http://www.suse.com

Re: R5000SC

[Florian Lohoff]

On Mon, Oct 23, 2000 at 09:35:30PM -0700, Randall Craig wrote:

> The machine seems seems to have Secondary unified cache.  Could anyone
> confirm that this machine is not supported.

Even without Secondary Cache there are problems with R5000.

>      1 180 MHZ IP22 Processor
>      FPU: MIPS R5000 Floating Point Coprocessor Revision: 1.0
>      CPU: MIPS R5000 Processor Chip Revision: 2.1

I got a 150Mhz IP22 (Indy) without secondary cache and i see
very strange things happen with 2.4.0-test9 (2.2.14 was reported
to work)

Flo
-- 
Florian Lohoff		flo@rfc822.org		      	+49-5201-669912
      "Write only memory - Oops. Time for my medication again ..."