Re: ieee754_csr is the problem (Re: lazy fpu switch irrelavant to no-fpu case?

[Kjeld Borch Egevang <kjelde@mips.com>]

In mips.test, you wrote:
>This is what I get for processing my mail in-order.
>I just got done writing a message asking if the
>ieee_754_csr issue might be at the root of your
>problem.
>
>Anyway, rather than create an array of the damned
>things, I would think that the "best" thing to do would
>be to merge the "abstract" IEEE CSR with the
>simulated MIPS CSR (by adding the "noq" and
>"nod" bits in otherwise unused/reserved bit positions),
>and using the thread-local CSR copy for all of the
>ieee_754_csr manipulations, much as I did for
>the FP registers.  That would be a bit more intrusive
>than your proposed hack, however, and only slightly
>more efficient.

I've been wondering: Why was the CSR copy made in the first place?

/Kjeld

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