Re: Re: watch exception only for kseg0 addresses..?

Re: Re: watch exception only for kseg0 addresses..?

[atul srivastava]

>
> > in change history of this file i am able to see  KSEG0 
>restriction
> > removed only for arch/mips64/lib/watch.S...
>
>The hw takes physical addresses, so using a a virtual address as 
>argument >for __watch_set seemed to be stupid anyway.  The hw 
>takes a physical address and the conversion is best done in C 
>anyway.

>The whole watch stuff in the the kernel is pretty much an ad-hoc 
>API
>which I did create to debug a stack overflow.  I'm sure if 
>you're
>going to use it you'll find problems.  For userspace for example 
>you'd
>have to switch the watch register when switching the MMU context 
>so
>each process gets it's own virtual watch register.
Beyond that there
>are at least two different formats of watch registers implemented 
>in
>actual silicon, the original R4000-style and the MIPS32/MIPS64 
>style
>watch registers and the kernel's watch code only know the R4000 
>style

my cpu manual ( IDT RC32334) talks about two watch registers 
CP0_IWATCH and CP0_DWATCH where it is required to just put desired 
VIRTUAL( bits 2--31) addresses to be watched , there is no mention 
of CP0_WATCHLO and CP0_WATCHHI .

additionally i guees for userspace virtual watch register problem, 
the hardware takes care of all , i just need to specify my virual 
address this is what i understand from my  manual.

and one more problem i face when i try to debug a mysterious page 
fault problem, that i get my watch exception but after page fault 
..hence I can't really debug , shouldn't the priority of watch 
exceptions should be higher than atleast instruction fetch 
exception.? or the scope of debugging by watch exception is 
limited by design.....

Re: Re: watch exception only for kseg0 addresses..?

[Ralf Baechle]

On Mon, Nov 25, 2002 at 10:01:52AM -0000, atul srivastava wrote:

> >The whole watch stuff in the the kernel is pretty much an ad-hoc 
> >API
> >which I did create to debug a stack overflow.  I'm sure if 
> >you're
> >going to use it you'll find problems.  For userspace for example 
> >you'd
> >have to switch the watch register when switching the MMU context 
> >so
> >each process gets it's own virtual watch register.
> Beyond that there
> >are at least two different formats of watch registers implemented 
> >in
> >actual silicon, the original R4000-style and the MIPS32/MIPS64 
> >style
> >watch registers and the kernel's watch code only know the R4000 
> >style

(It's horrible what mailprograms accounts do to mail formatting ...)

> my cpu manual ( IDT RC32334) talks about two watch registers 
> CP0_IWATCH and CP0_DWATCH where it is required to just put desired 
> VIRTUAL( bits 2--31) addresses to be watched , there is no mention 
> of CP0_WATCHLO and CP0_WATCHHI .
> 
> additionally i guees for userspace virtual watch register problem, 
> the hardware takes care of all , i just need to specify my virual 
> address this is what i understand from my  manual.
> 
> and one more problem i face when i try to debug a mysterious page 
> fault problem, that i get my watch exception but after page fault 
> ..hence I can't really debug , shouldn't the priority of watch 
> exceptions should be higher than atleast instruction fetch 
> exception.? or the scope of debugging by watch exception is 
> limited by design.....

No, the watch exception is one of the lowest priority exceptions.  In case
EXL/ERL are set it might even be defered making it the lowest priority
exception.

  Ralf

Re: Re: watch exception only for kseg0 addresses..?

[Kevin D. Kissell]

> > Beyond that there
> > are at least two different formats of watch registers implemented 
> > in actual silicon, the original R4000-style and the MIPS32/MIPS64 
> > style watch registers and the kernel's watch code only know the R4000 
> > style.
> 
> my cpu manual ( IDT RC32334) talks about two watch registers 
> CP0_IWATCH and CP0_DWATCH where it is required to just put desired 
> VIRTUAL( bits 2--31) addresses to be watched , there is no mention 
> of CP0_WATCHLO and CP0_WATCHHI .

Your CPU would appear to be neither MIPS32/MIPS64 compliant
nor R4000 backward-compatible.  The designers may have sought 
to simplify the use of watch registers in user space, apparently at the price 
of the restriction you are seeing.

> additionally i guees for userspace virtual watch register problem, 
> the hardware takes care of all , i just need to specify my virual 
> address this is what i understand from my  manual.
> 
> and one more problem i face when i try to debug a mysterious page 
> fault problem, that i get my watch exception but after page fault 
> ..hence I can't really debug , shouldn't the priority of watch 
> exceptions should be higher than atleast instruction fetch 
> exception.? or the scope of debugging by watch exception is 
> limited by design.....

Does your CPU implement EJTAG?

            Kevin K.

Re: Re: watch exception only for kseg0 addresses..?

[Kevin D. Kissell]

> > Beyond that there
> > are at least two different formats of watch registers implemented 
> > in actual silicon, the original R4000-style and the MIPS32/MIPS64 
> > style watch registers and the kernel's watch code only know the R4000 
> > style.
> 
> my cpu manual ( IDT RC32334) talks about two watch registers 
> CP0_IWATCH and CP0_DWATCH where it is required to just put desired 
> VIRTUAL( bits 2--31) addresses to be watched , there is no mention 
> of CP0_WATCHLO and CP0_WATCHHI .

Your CPU would appear to be neither MIPS32/MIPS64 compliant
nor R4000 backward-compatible.  The designers may have sought 
to simplify the use of watch registers in user space, apparently at the price 
of the restriction you are seeing.

> additionally i guees for userspace virtual watch register problem, 
> the hardware takes care of all , i just need to specify my virual 
> address this is what i understand from my  manual.
> 
> and one more problem i face when i try to debug a mysterious page 
> fault problem, that i get my watch exception but after page fault 
> ..hence I can't really debug , shouldn't the priority of watch 
> exceptions should be higher than atleast instruction fetch 
> exception.? or the scope of debugging by watch exception is 
> limited by design.....

Does your CPU implement EJTAG?

            Kevin K.