From: Dave Jones <davej@codemonkey.org.uk>
To: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
Cc: Andi Kleen <ak@muc.de>, linux-kernel@vger.kernel.org
Subject: Re: cacheline size detection code in 2.5.66
Date: Tue, 25 Mar 2003 16:43:25 +0000 [thread overview]
Message-ID: <20030325164317.GA4019@suse.de> (raw)
In-Reply-To: <20030325173937.A21821@jurassic.park.msu.ru>
On Tue, Mar 25, 2003 at 05:39:37PM +0300, Ivan Kokshaysky wrote:
> On Tue, Mar 25, 2003 at 02:35:25PM +0100, Andi Kleen wrote:
> > Ivan confused me. Either he read the application note wrong or it is wrong.
>
> Ok, it's available at
> http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/20734.pdf
For info, that is a reliable[*] way to detect XP/MP Athlons.
It's used in the kernel for SMP tainting, and x86info has also been
using it for some time.
Dave
[*] AMD screwed up one stepping of XPs and enabled the MP bit even though
they weren't actually MPs.
next prev parent reply other threads:[~2003-03-25 16:32 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-03-25 7:15 cacheline size detection code in 2.5.66 Andi Kleen
2003-03-25 11:33 ` Ivan Kokshaysky
2003-03-25 12:15 ` Andi Kleen
2003-03-25 12:43 ` Dave Jones
2003-03-25 13:35 ` Andi Kleen
2003-03-25 14:39 ` Ivan Kokshaysky
2003-03-25 16:43 ` Dave Jones [this message]
2003-03-25 11:52 ` Dave Jones
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