In r4k, where does PC point to?

In r4k, where does PC point to?

[karthikeyan natarajan]

Hi All,

    Basically, the PC points to the next instruction
to
be executed. But, in R4k, there are 8 instructions
getting executed in parallel. Where does the PC point
to? My understanding is that PC points to the next 
instruction that will be entered into the pipeline.
    Please correct me if i am wrong..

Thanks,
-karthi


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Re: In r4k, where does PC point to?

[Ralf Baechle]

On Mon, Jan 19, 2004 at 07:42:19AM +0000, karthikeyan natarajan wrote:

>     Basically, the PC points to the next instruction
> to
> be executed. But, in R4k, there are 8 instructions
> getting executed in parallel. Where does the PC point
> to? My understanding is that PC points to the next 
> instruction that will be entered into the pipeline.
>     Please correct me if i am wrong..

The fact that instructions are issued in a pipeline is not visible in
the EPC value.

  Ralf

Re: In r4k, where does PC point to?

[Dominic Sweetman]

> >     Basically, the PC points to the next instruction
> > to
> > be executed. But, in R4k, there are 8 instructions
> > getting executed in parallel. Where does the PC point
> > to? My understanding is that PC points to the next 
> > instruction that will be entered into the pipeline.
> >     Please correct me if i am wrong..

Ralf Baechle (ralf@linux-mips.org) writes:
 
> The fact that instructions are issued in a pipeline is not visible in
> the EPC value.

Which is true, but perhaps a bit cryptic given the question.

A MIPS CPU does not have a register called "PC".  In the MIPS
architecture, "PC" is just slang meaning "the address of this
instruction" - and only makes any sense if you're prepared to say
WHICH instruction you mean.

There IS a register called "EPC" (for "exception PC").  When you
take any kind of exception, it's the address of the first instruction
which didn't get run because the CPU took the exception instead.  So
EPC tells you where to jump back to after the exception handler runs.

Did any of that make any sense?

--
Dominic Sweetman
MIPS Technologies.

Re: In r4k, where does PC point to?

[karthikeyan natarajan]

Hi Dominic Sweetman,

> > >     Basically, the PC points to the next
> instruction
> > > to
> > > be executed. But, in R4k, there are 8
> instructions
> > > getting executed in parallel. Where does the PC
> point
> > > to? My understanding is that PC points to the
> next 
> > > instruction that will be entered into the
> pipeline.
> > >     Please correct me if i am wrong..
> 
> Ralf Baechle (ralf@linux-mips.org) writes:
>  
> > The fact that instructions are issued in a
> pipeline is not visible in
> > the EPC value.
> 
> Which is true, but perhaps a bit cryptic given the
> question.
> 
> A MIPS CPU does not have a register called "PC".  In

In the r4k user manual, it is mentioned that there is
a special register PC in the core CPU (other than the 
HI & LO special registers). Could you please let me 
know the purpose of this register?

Thanks,
-karthi

> the MIPS
> architecture, "PC" is just slang meaning "the
> address of this
> instruction" - and only makes any sense if you're
> prepared to say
> WHICH instruction you mean.
> 
> There IS a register called "EPC" (for "exception
> PC").  When you
> take any kind of exception, it's the address of the
> first instruction
> which didn't get run because the CPU took the
> exception instead.  So
> EPC tells you where to jump back to after the
> exception handler runs.
> 
> Did any of that make any sense?
> 
> --
> Dominic Sweetman
> MIPS Technologies.
> 
> 
> 
>  

=====
The expert at anything was once a beginner
                  ______________________________
                 /                              \
             O  /      Karthikeyan.N             \
           O   |       Chennai, India.            |
    `\|||/'     \    Mobile: +919884104346       /
     (o o)       \                              /
_ ooO (_) Ooo____________________________________
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Re: In r4k, where does PC point to?

[Ralf Baechle]

On Mon, Jan 19, 2004 at 03:14:03PM +0000, karthikeyan natarajan wrote:

> > Which is true, but perhaps a bit cryptic given the
> > question.
> > 
> > A MIPS CPU does not have a register called "PC".  In
> 
> In the r4k user manual, it is mentioned that there is
> a special register PC in the core CPU (other than the 
> HI & LO special registers). Could you please let me 
> know the purpose of this register?

Obviously the CPU needs to know where to fetch the next instruction from
or for computing the destination address of branch and jump instructions
or the value to put into the programmer visible EPC and ErrorEPC registers
etc.  The PC register is an internal register that isn't visible to the
programmer.

  Ralf

Re: In r4k, where does PC point to?

[karthikeyan natarajan]

Hi Ralf,

> > > Which is true, but perhaps a bit cryptic given
> the
> > > question.
> > > 
> > > A MIPS CPU does not have a register called "PC".
>  In
> > 
> > In the r4k user manual, it is mentioned that there
> is
> > a special register PC in the core CPU (other than
> the 
> > HI & LO special registers). Could you please let
> me 
> > know the purpose of this register?
> 
> Obviously the CPU needs to know where to fetch the
> next instruction from

So the PC points to the next instruction to be
fetched,
but it is not visible to the programmer..

> or for computing the destination address of branch
> and jump instructions
> or the value to put into the programmer visible EPC
> and ErrorEPC registers

Am curious to know, how the PC register can be used to

locate the instruction which caused the exception as 
the exception can happen at any one of the eight 
pipeline stages..

Thanks much,
-karthi


> etc.  The PC register is an internal register that
> isn't visible to the
> programmer.

So the bottom line here is PC is internal register and

the EPC is visible to the programmer.. 


Thanks,
-karthi
 
>   Ralf
>  

=====
The expert at anything was once a beginner
                  ______________________________
                 /                              \
             O  /      Karthikeyan.N             \
           O   |       Chennai, India.            |
    `\|||/'     \    Mobile: +919884104346       /
     (o o)       \                              /
_ ooO (_) Ooo____________________________________
_____|_____|_____|_____|_____|_____|_____|_____|_
__|_____|_____|_____|_____|_____|_____|_____|____
_____|_____|_____|_____|_____|_____|_____|_____|_

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Re: In r4k, where does PC point to?

[Dominic Sweetman]

Karthi,

One more try:

> > A MIPS CPU does not have a register called "PC".  In...
> 
> In the r4k user manual, it is mentioned that there is
> a special register PC in the core CPU (other than the 
> HI & LO special registers).

OK, by "register" I mean strictly something which is
software-visible - like "$2" or the coprocessor-zero register called
"EPC".

There is no PC register in my sense, and if you've found a manual
claiming that one exists, that manual is wrong - send me URL and
tell me how to find this text.

--
Dominic

Re: In r4k, where does PC point to?

[karthikeyan natarajan]

Hi Dominic,

    Thanks for your comment.. replies inline..

> One more try:
> 
> > > A MIPS CPU does not have a register called "PC".
>  In...
> > 
> > In the r4k user manual, it is mentioned that there
> is
> > a special register PC in the core CPU (other than
> the 
> > HI & LO special registers).
> 
> OK, by "register" I mean strictly something which is
> software-visible - like "$2" or the coprocessor-zero
> register called
> "EPC".
> 
> There is no PC register in my sense, and if you've
> found a manual
> claiming that one exists, that manual is wrong -
> send me URL and
> tell me how to find this text.

Here is the link..
http://www.cag.lcs.mit.edu/raw/documents/R4400_Uman_book_Ed2.pdf


    The documentation about the PC is present in the
chapter-1 under the section "CPU Register Overview".

    Please let me know whether this manual is correct.

Thanks much,
-karthi

> --
> Dominic
> 
> 
>  

=====
The expert at anything was once a beginner
                  ______________________________
                 /                              \
             O  /      Karthikeyan.N             \
           O   |       Chennai, India.            |
    `\|||/'     \    Mobile: +919884104346       /
     (o o)       \                              /
_ ooO (_) Ooo____________________________________
_____|_____|_____|_____|_____|_____|_____|_____|_
__|_____|_____|_____|_____|_____|_____|_____|____
_____|_____|_____|_____|_____|_____|_____|_____|_

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Re: In r4k, where does PC point to?

[Dominic Sweetman]

> Am curious to know, how the PC register can be used to
> locate the instruction which caused the exception as 
> the exception can happen at any one of the eight 
> pipeline stages..

You can't, of course, because there isn't a "PC register".  But now I
understand your question...

Most MIPS implementations actually respond to all exceptions at the
same pipe-stage.  (If you took exceptions when you first noticed them,
an early-stage event like a I-side TLBmiss might happen before a
D-side TLBmiss for an instruction which is earlier in the instruction
stream... and that would be bad.  We're pretending this is a
sequential processor).

So exception conditions detected early in the pipe set a flag which is
then carried down the pipeline and always looked at in the same stage.

The choice of which stage to do this is somewhat implementation
dependent; it wants to be the last stage where you can find out that
an exception is needed.  Generally that will be about the same time as
you'd access the D-cache (you may get exceptions when you're
translating the D-address).

So there needs to be a way to figure out the address where the
instruction currently at the "X" pipestage came from.  You need that
for exceptions; but you also need it (for example) when executing a
'jal' instruction and figuring out the return address.

A conceptually simple way to do this is to carry the instruction's
address along the pipeline with it, in case you need it.  But
sometimes CPU designers do something more complicated to save the
storage.

> Here is the link..
> http://www.cag.lcs.mit.edu/raw/documents/R4400_Uman_book_Ed2.pdf
> 
> The documentation about the PC is present in the chapter-1 under the
> section "CPU Register Overview".
> 
> Please let me know whether this manual is correct.

Ah, that book.  That picture is nonsense, really.  Sorry, that
happens!

--
Dominic Sweetman
MIPS Technologies.