From: Jun Sun <jsun@mvista.com>
To: G H <giles67@yahoo.com>
Cc: linux-mips@linux-mips.org, jsun@mvista.com
Subject: Re: do_ri failure in cache flushing routines
Date: Thu, 5 Aug 2004 11:11:33 -0700 [thread overview]
Message-ID: <20040805111133.B28337@mvista.com> (raw)
In-Reply-To: <20040805180427.59029.qmail@web50806.mail.yahoo.com>; from giles67@yahoo.com on Thu, Aug 05, 2004 at 11:04:27AM -0700
On Thu, Aug 05, 2004 at 11:04:27AM -0700, G H wrote:
> I've not had much response to this question so I would like to rephrase it :
>
> Can anyone think of any possible scenario where do_ri could occur in blast_icache32() ??
>
One possibility _could_ be the "instruction flushing itself" problem on
MIPS32. However, as far as I know au1x00 CPUs don't suffer from this problem.
Anybody knows for sure?
You could try to use the two phase cache flushing (such as the one used
by tx47xx and also see an earlier related discussion thread) and see if
the problem goes away.
Jun
next prev parent reply other threads:[~2004-08-05 18:11 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-08-05 18:04 do_ri failure in cache flushing routines G H
2004-08-05 18:09 ` Pete Popov
2004-08-05 18:13 ` Pete Popov
2004-08-05 20:16 ` G H
2004-08-05 22:31 ` Pete Popov
2004-08-05 18:11 ` Jun Sun [this message]
2004-08-05 20:25 ` G H
2004-08-05 20:25 ` G H
-- strict thread matches above, loose matches on Subject: below --
2004-08-03 16:19 G H
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