From: Ralf Baechle <ralf@linux-mips.org>
To: "Kapoor, Pankaj" <pkapoor@ti.com>
Cc: linux-mips@linux-mips.org
Subject: Re: Cache Question
Date: Wed, 24 Nov 2004 23:32:12 +0100 [thread overview]
Message-ID: <20041124223211.GB22439@linux-mips.org> (raw)
In-Reply-To: <C4D23DECD6CD714BBFB38B0AE8D25A3A24FF66@dlee2k03.ent.ti.com>
On Tue, Nov 23, 2004 at 12:19:21PM -0600, Kapoor, Pankaj wrote:
> Is there any specific reason why the cache invalidation routine is
> executed with interrupts disabled?
That interrupt disabling in some cache flushes dates back further than
CVS history. Seems once uppon a time there was some CPU which didn't
like cache flushes with interrupts enabled. This is rather bad for
latencies so unless somebody else on this list recalls a good reason
I'd like to remove this.
Ralf
next prev parent reply other threads:[~2004-11-24 22:32 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-11-23 18:19 Cache Question Kapoor, Pankaj
2004-11-23 18:19 ` Kapoor, Pankaj
2004-11-24 22:32 ` Ralf Baechle [this message]
2004-11-24 22:42 ` Maciej W. Rozycki
2004-11-24 22:54 ` Ralf Baechle
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