From: Ralf Baechle <ralf@linux-mips.org>
To: "Maciej W. Rozycki" <macro@linux-mips.org>
Cc: "Kapoor, Pankaj" <pkapoor@ti.com>, linux-mips@linux-mips.org
Subject: Re: Cache Question
Date: Wed, 24 Nov 2004 23:54:37 +0100 [thread overview]
Message-ID: <20041124225437.GE22439@linux-mips.org> (raw)
In-Reply-To: <Pine.LNX.4.58L.0411242241130.843@blysk.ds.pg.gda.pl>
On Wed, Nov 24, 2004 at 10:42:45PM +0000, Maciej W. Rozycki wrote:
> > That interrupt disabling in some cache flushes dates back further than
> > CVS history. Seems once uppon a time there was some CPU which didn't
> > like cache flushes with interrupts enabled. This is rather bad for
> > latencies so unless somebody else on this list recalls a good reason
> > I'd like to remove this.
>
> Some R4600 (v1.1?) errata workaround? Or was it elsewhere?
V1.7 you mean - it identifies as 1.0 in c0_prid though. I don't have
my erratas for this one anymore. I've checked erratum #3 of V2.0 with
one of the R4600 designers already a while ago and he said disabling
interrupts isn't necessary.
The ancient Linux code I was refering to used to disable interrupts
for all CPUs. Supported CPUs back then were R4000, R4400, R4600 only,
so it must have been one of those.
Ralf
prev parent reply other threads:[~2004-11-24 22:55 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-11-23 18:19 Cache Question Kapoor, Pankaj
2004-11-23 18:19 ` Kapoor, Pankaj
2004-11-24 22:32 ` Ralf Baechle
2004-11-24 22:42 ` Maciej W. Rozycki
2004-11-24 22:54 ` Ralf Baechle [this message]
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