Cache Question

Cache Question

[Kapoor, Pankaj]

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Hi,

Is there any specific reason why the cache invalidation routine is
executed with interrupts disabled? 

Example: 

static void
mips32_dma_cache_inv_pc(unsigned long addr, unsigned long size)
{
	unsigned long end, a;
	unsigned int flags;

	if (size >= dcache_size) {
		flush_cache_all();
	} else {
	        __save_and_cli(flags);
		a = addr & ~(dc_lsize - 1);
		end = (addr + size) & ~(dc_lsize - 1);
		while (1) {
			flush_dcache_line(a); /* Hit_Writeback_Inv_D */
			if (a == end) break;
			a += dc_lsize;
		}
		__restore_flags(flags);
	}

	bc_inv(addr, size);
}

Thanks.
- Pankaj

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Cache Question

[Kapoor, Pankaj]

[-- Attachment #1: Type: text/plain, Size: 619 bytes --]

Hi,

Is there any specific reason why the cache invalidation routine is
executed with interrupts disabled? 

Example: 

static void
mips32_dma_cache_inv_pc(unsigned long addr, unsigned long size)
{
	unsigned long end, a;
	unsigned int flags;

	if (size >= dcache_size) {
		flush_cache_all();
	} else {
	        __save_and_cli(flags);
		a = addr & ~(dc_lsize - 1);
		end = (addr + size) & ~(dc_lsize - 1);
		while (1) {
			flush_dcache_line(a); /* Hit_Writeback_Inv_D */
			if (a == end) break;
			a += dc_lsize;
		}
		__restore_flags(flags);
	}

	bc_inv(addr, size);
}

Thanks.
- Pankaj

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Re: Cache Question

[Ralf Baechle]

On Tue, Nov 23, 2004 at 12:19:21PM -0600, Kapoor, Pankaj wrote:

> Is there any specific reason why the cache invalidation routine is
> executed with interrupts disabled? 

That interrupt disabling in some cache flushes dates back further than
CVS history.  Seems once uppon a time there was some CPU which didn't
like cache flushes with interrupts enabled.  This is rather bad for
latencies so unless somebody else on this list recalls a good reason
I'd like to remove this.

  Ralf

Re: Cache Question

[Maciej W. Rozycki]

On Wed, 24 Nov 2004, Ralf Baechle wrote:

> That interrupt disabling in some cache flushes dates back further than
> CVS history.  Seems once uppon a time there was some CPU which didn't
> like cache flushes with interrupts enabled.  This is rather bad for
> latencies so unless somebody else on this list recalls a good reason
> I'd like to remove this.

 Some R4600 (v1.1?) errata workaround?  Or was it elsewhere?

  Maciej

Re: Cache Question

[Ralf Baechle]

On Wed, Nov 24, 2004 at 10:42:45PM +0000, Maciej W. Rozycki wrote:

> > That interrupt disabling in some cache flushes dates back further than
> > CVS history.  Seems once uppon a time there was some CPU which didn't
> > like cache flushes with interrupts enabled.  This is rather bad for
> > latencies so unless somebody else on this list recalls a good reason
> > I'd like to remove this.
> 
>  Some R4600 (v1.1?) errata workaround?  Or was it elsewhere?

V1.7 you mean - it identifies as 1.0 in c0_prid though.  I don't have
my erratas for this one anymore.  I've checked erratum #3 of V2.0 with
one of the R4600 designers already a while ago and he said disabling
interrupts isn't necessary.

The ancient Linux code I was refering to used to disable interrupts
for all CPUs.  Supported CPUs back then were R4000, R4400, R4600 only,
so it must have been one of those.

  Ralf