From: Randolph Chung <randolph@tausq.org>
To: Grant Grundler <grundler@parisc-linux.org>
Cc: parisc-linux@lists.parisc-linux.org
Subject: Re: [parisc-linux] DIFF use 6-regs in copy_user_page_asm
Date: Mon, 3 Jan 2005 22:13:42 -0800 [thread overview]
Message-ID: <20050104061342.GE18497@tausq.org> (raw)
In-Reply-To: <20050103061910.GJ15061@colo.lackof.org>
> This patch adds one more cycle between the load and store of a
> given register by using three pairs of registers instead of two.
> I had previously quoted one of the PA-8xxx papers that indicated
> L1 cache was 2 cycles latency.
> With this diff, the unrolled part of the loop now meets that.
> The prolog and epilogue obviously cannot.
>
> If anyone can show me a workload that improves with this diff,
> I'll apply it. Otherwise it's just an academic excercise.
i'd like to see numbers too, but i doubt you will see any. it appears
that at least newer PA cpus do a sufficient amount of internal
instruction reordering that you don't see a difference as long as there
are enough pending instructions to keep the pipeline busy.
randolph
--
Randolph Chung
Debian GNU/Linux Developer, hppa/ia64 ports
http://www.tausq.org/
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next prev parent reply other threads:[~2005-01-04 6:13 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-01-03 6:19 [parisc-linux] DIFF use 6-regs in copy_user_page_asm Grant Grundler
2005-01-04 6:13 ` Randolph Chung [this message]
2005-01-04 8:23 ` Ryan Bradetich
2005-01-04 8:29 ` Randolph Chung
2005-01-04 13:12 ` Joel Soete
2005-01-04 14:51 ` Michael S. Zick
2005-01-04 16:02 ` Grant Grundler
[not found] ` <200501041142.44400.mszick@wolfbutter.com>
2005-01-04 20:09 ` Grant Grundler
2005-01-04 23:39 ` Grant Grundler
2005-01-05 0:00 ` John David Anglin
2005-01-05 22:01 ` Michael S. Zick
2005-01-06 22:55 ` Grant Grundler
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