[PATCH 3/6] intelfb: Workaround for 830M

[PATCH 3/6] intelfb: Workaround for 830M

[Antonino A. Daplas]

  This is a work around for the 830M with intelfb.  Relative to 2.6.10.
  Without this patch, updates to the DSPACNTR register will be ignored.

  On the 830M, the display plane needs to be enabled before writing
  to any of the other bits in the DSPACNTR register.
  
  This patch detects the specific case, temporarily enables the plane,
  updates the register, and then disables the plane.  It also appears
  to require some settling time, but not an entire frame's time.
  
  Without this change, the pixel format fields in DSPACNTR won't get
  written on the 830M.

Signed-off-by: Andrew Pfiffer <andrewx.k.pfiffer@intel.com>
Signed-off-by: Antonino Daplas <adaplas@pol.net>
---

 intelfbhw.c |   16 ++++++++++++++++
 1 files changed, 16 insertions(+)

diff -Nru a/drivers/video/intelfb/intelfbhw.c b/drivers/video/intelfb/intelfbhw.c
--- a/drivers/video/intelfb/intelfbhw.c	2004-11-17 18:29:40 +08:00
+++ b/drivers/video/intelfb/intelfbhw.c	2005-01-15 08:18:07 +08:00
@@ -1207,6 +1207,22 @@
 	OUTREG(ADPA, tmp);
 
 	/* setup display plane */
+	if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) {
+		/*
+		 *      i830M errata: the display plane must be enabled
+		 *      to allow writes to the other bits in the plane
+		 *      control register.
+		 */
+		tmp = INREG(DSPACNTR);
+		if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) {
+			tmp |= DISPPLANE_PLANE_ENABLE;
+			OUTREG(DSPACNTR, tmp);
+			OUTREG(DSPACNTR, 
+			       hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE);
+			mdelay(1);
+              }
+	}
+
 	OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);
 	OUTREG(DSPASTRIDE, hw->disp_a_stride);
 	OUTREG(DSPABASE, hw->disp_a_base);




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