From: Ingo Molnar <mingo@elte.hu>
To: Todd Poynor <tpoynor@mvista.com>
Cc: cpufreq@lists.linux.org.uk, linux-pm@lists.osdl.org,
linux-kernel@vger.kernel.org
Subject: Re: PowerOP 2/3: Intel Centrino support
Date: Tue, 9 Aug 2005 09:59:19 +0200 [thread overview]
Message-ID: <20050809075919.GA18309@elte.hu> (raw)
In-Reply-To: <20050809025419.GC25064@slurryseal.ddns.mvista.com>
* Todd Poynor <tpoynor@mvista.com> wrote:
> +static int
> +powerop_centrino_get_point(struct powerop_point *point)
> +{
> + unsigned l, h;
> + unsigned cpu_freq;
> +
> + rdmsr(MSR_IA32_PERF_STATUS, l, h);
> + if (unlikely((cpu_freq = ((l >> 8) & 0xff) * 100) == 0)) {
> + /*
> + * On some CPUs, we can see transient MSR values (which are
> + * not present in _PSS), while CPU is doing some automatic
> + * P-state transition (like TM2). Get the last freq set
> + * in PERF_CTL.
> + */
> + rdmsr(MSR_IA32_PERF_CTL, l, h);
> + cpu_freq = ((l >> 8) & 0xff) * 100;
> + }
> +
> + point->param[POWEROP_CPU + smp_processor_id()] = cpu_freq;
> + point->param[POWEROP_V + smp_processor_id()] = ((l & 0xff) * 16) + 700;
> + return 0;
> +}
doesnt seem to be SMP-safe, nor PREEMPT-safe. You probably want to do
the locking in the highlevel functions.
Ingo
WARNING: multiple messages have this Message-ID (diff)
From: Ingo Molnar <mingo@elte.hu>
To: Todd Poynor <tpoynor@mvista.com>
Cc: linux-kernel@vger.kernel.org, linux-pm@lists.osdl.org,
cpufreq@lists.linux.org.uk
Subject: Re: PowerOP 2/3: Intel Centrino support
Date: Tue, 9 Aug 2005 09:59:19 +0200 [thread overview]
Message-ID: <20050809075919.GA18309@elte.hu> (raw)
In-Reply-To: <20050809025419.GC25064@slurryseal.ddns.mvista.com>
* Todd Poynor <tpoynor@mvista.com> wrote:
> +static int
> +powerop_centrino_get_point(struct powerop_point *point)
> +{
> + unsigned l, h;
> + unsigned cpu_freq;
> +
> + rdmsr(MSR_IA32_PERF_STATUS, l, h);
> + if (unlikely((cpu_freq = ((l >> 8) & 0xff) * 100) == 0)) {
> + /*
> + * On some CPUs, we can see transient MSR values (which are
> + * not present in _PSS), while CPU is doing some automatic
> + * P-state transition (like TM2). Get the last freq set
> + * in PERF_CTL.
> + */
> + rdmsr(MSR_IA32_PERF_CTL, l, h);
> + cpu_freq = ((l >> 8) & 0xff) * 100;
> + }
> +
> + point->param[POWEROP_CPU + smp_processor_id()] = cpu_freq;
> + point->param[POWEROP_V + smp_processor_id()] = ((l & 0xff) * 16) + 700;
> + return 0;
> +}
doesnt seem to be SMP-safe, nor PREEMPT-safe. You probably want to do
the locking in the highlevel functions.
Ingo
next prev parent reply other threads:[~2005-08-09 7:59 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-08-09 2:54 PowerOP 2/3: Intel Centrino support Todd Poynor
2005-08-09 7:59 ` Ingo Molnar [this message]
2005-08-09 7:59 ` Ingo Molnar
2005-08-10 10:01 ` Pavel Machek
2005-08-10 10:01 ` Pavel Machek
2005-08-10 12:58 ` Bruno Ducrot
2005-08-10 12:58 ` Bruno Ducrot
2005-08-10 18:44 ` Dave Jones
2005-08-10 18:44 ` [linux-pm] " Dave Jones
2005-08-10 23:37 ` Todd Poynor
2005-08-10 23:37 ` [linux-pm] " Todd Poynor
2005-08-11 15:06 ` Jordan Crouse
2005-08-11 15:06 ` Jordan Crouse
2005-08-12 23:13 ` Todd Poynor
2005-08-12 23:13 ` Todd Poynor
2005-08-12 12:38 ` [linux-pm] " Nikolay Pelov
2005-08-12 12:38 ` Nikolay Pelov
2005-08-10 22:53 ` Todd Poynor
2005-08-10 22:53 ` Todd Poynor
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