From: Andi Kleen <ak@suse.de>
To: Tejun Heo <htejun@gmail.com>
Cc: lkml <linux-kernel@vger.kernel.org>, discuss@x86-64.org
Subject: Re: Question regarding x86_64 __PHYSICAL_MASK_SHIFT
Date: Tue, 4 Oct 2005 21:27:20 +0200 [thread overview]
Message-ID: <200510042127.21238.ak@suse.de> (raw)
In-Reply-To: <4342D5A5.2080902@gmail.com>
On Tuesday 04 October 2005 21:19, Tejun Heo wrote:
> Hmmm.. but, currently
>
> * PHYSICAL_PAGE_MASK == (~(PAGE_SIZE-1)&(__PHYSICAL_MASK << PAGE_SHIFT)
> == (0xffffffff_fffff000 & (0x00003fff_ffffffff << 12)
> == 0x03ffffff_fffff000
> while it actually should be 0x00003fff_fffff000
Right. Fixed now
> * PTE_FILE_MAX_BITS == __PHYSICAL_MASK_SHIFT == 46, but only 40bits are
> available in page table entries.
The non linear mapping format is independent from the MMU, the number
is pretty much arbitary, but it is consistent to make it the same as
other ptes for easier sanity checking.
-Andi
next prev parent reply other threads:[~2005-10-04 19:27 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-10-04 11:59 Question regarding x86_64 __PHYSICAL_MASK_SHIFT Tejun Heo
2005-10-04 12:02 ` Tejun Heo
2005-10-04 17:24 ` Andi Kleen
2005-10-04 18:52 ` Tejun Heo
2005-10-04 19:01 ` Andi Kleen
2005-10-04 19:19 ` Tejun Heo
2005-10-04 19:27 ` Andi Kleen [this message]
2005-10-05 4:01 ` Tejun Heo
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