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From: Tejun Heo <htejun@gmail.com>
To: Andi Kleen <ak@suse.de>
Cc: lkml <linux-kernel@vger.kernel.org>
Subject: Question regarding x86_64 __PHYSICAL_MASK_SHIFT
Date: Tue, 04 Oct 2005 20:59:48 +0900	[thread overview]
Message-ID: <43426EB4.6080703@gmail.com> (raw)


  Hello, Andi.

  In include/asm-x86_64/page.h, __VIRTUAL_MASK_SHIFT is defined as 48 
bits which is the size of virtual address space on current x86_64 
machines as used as such.  OTOH, __PHYSICAL_MASK_SHIFT is defined as 46 
and used as mask shift for physical page address (i.e. physaddr >> 12).

  In addition to being a bit confusing due to similar names but 
different meanings, this means that we assume processors can physically 
address 58 (46 + 12) bits, but both amd64 and IA-32e manuals say that 
current architectural limit is 52 bits and bits 52-62 are reserved in 
all page table entries.  This currently (and in foreseeable future) 
doesn't cause any problem but it's still a bit weird.

  Am I missing something?

  Thanks.

-- 
tejun

             reply	other threads:[~2005-10-04 11:59 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2005-10-04 11:59 Tejun Heo [this message]
2005-10-04 12:02 ` Question regarding x86_64 __PHYSICAL_MASK_SHIFT Tejun Heo
2005-10-04 17:24 ` Andi Kleen
2005-10-04 18:52   ` Tejun Heo
2005-10-04 19:01     ` Andi Kleen
2005-10-04 19:19       ` Tejun Heo
2005-10-04 19:27         ` Andi Kleen
2005-10-05  4:01           ` Tejun Heo

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