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From: Ralf Baechle <ralf@linux-mips.org>
To: Sergei Shtylylov <sshtylyov@ru.mvista.com>
Cc: Atsushi Nemoto <anemo@mba.ocn.ne.jp>, linux-mips@linux-mips.org
Subject: Re: [PATCH] TX49 MFC0 bug workaround
Date: Thu, 2 Feb 2006 22:11:32 +0000	[thread overview]
Message-ID: <20060202221132.GA8799@linux-mips.org> (raw)
In-Reply-To: <43E25381.4060309@ru.mvista.com>

On Thu, Feb 02, 2006 at 09:46:25PM +0300, Sergei Shtylylov wrote:

> Atsushi Nemoto wrote:
> >If mfc0 $12 follows store and the mfc0 is last instruction of a
> >page and fetching the next instruction causes TLB miss, the result
> >of the mfc0 might wrongly contain EXL bit.
> 
>    Hmm, a TLB miss in fetching from KSEG0?!

It'll hit loadable modules which run in the mapped KSEG2/3 spaces.

  Ralf

  reply	other threads:[~2006-02-03 13:17 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2006-02-02 16:34 [PATCH] TX49 MFC0 bug workaround Atsushi Nemoto
2006-02-02 16:38 ` Maciej W. Rozycki
2006-02-02 16:56   ` Ralf Baechle
2006-02-02 17:04     ` Atsushi Nemoto
2006-02-02 17:21       ` Atsushi Nemoto
2006-02-02 17:24       ` Ralf Baechle
2006-02-03  2:10         ` Atsushi Nemoto
2006-02-03 10:17           ` Maciej W. Rozycki
2006-02-03 14:44           ` Ralf Baechle
2006-02-06  9:36             ` Atsushi Nemoto
2006-02-06 23:22               ` Ralf Baechle
2006-02-03  2:26     ` Sergei Shtylylov
2006-02-03  2:50       ` Atsushi Nemoto
2006-02-02 16:46 ` Ralf Baechle
2006-02-02 18:46 ` Sergei Shtylylov
2006-02-02 22:11   ` Ralf Baechle [this message]
2006-02-03  1:17   ` Atsushi Nemoto
2006-02-03  2:12     ` Sergei Shtylylov
2006-02-03  2:22       ` Atsushi Nemoto
2006-02-07 15:32         ` Sergei Shtylylov
2006-02-07 15:32           ` Sergei Shtylylov

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