From: Sergei Shtylylov <sshtylyov@ru.mvista.com>
To: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Cc: linux-mips@linux-mips.org, ralf@linux-mips.org
Subject: Re: [PATCH] TX49 MFC0 bug workaround
Date: Thu, 02 Feb 2006 21:46:25 +0300 [thread overview]
Message-ID: <43E25381.4060309@ru.mvista.com> (raw)
In-Reply-To: <20060203.013401.41198517.anemo@mba.ocn.ne.jp>
Hello.
Atsushi Nemoto wrote:
> If mfc0 $12 follows store and the mfc0 is last instruction of a
> page and fetching the next instruction causes TLB miss, the result
> of the mfc0 might wrongly contain EXL bit.
Hmm, a TLB miss in fetching from KSEG0?!
> ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008
>
> Workaround: mask EXL bit of the result or place a nop before mfc0.
Is this workaround really needed?
> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
WBR, Sergei
next prev parent reply other threads:[~2006-02-02 18:38 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-02-02 16:34 [PATCH] TX49 MFC0 bug workaround Atsushi Nemoto
2006-02-02 16:38 ` Maciej W. Rozycki
2006-02-02 16:56 ` Ralf Baechle
2006-02-02 17:04 ` Atsushi Nemoto
2006-02-02 17:21 ` Atsushi Nemoto
2006-02-02 17:24 ` Ralf Baechle
2006-02-03 2:10 ` Atsushi Nemoto
2006-02-03 10:17 ` Maciej W. Rozycki
2006-02-03 14:44 ` Ralf Baechle
2006-02-06 9:36 ` Atsushi Nemoto
2006-02-06 23:22 ` Ralf Baechle
2006-02-03 2:26 ` Sergei Shtylylov
2006-02-03 2:50 ` Atsushi Nemoto
2006-02-02 16:46 ` Ralf Baechle
2006-02-02 18:46 ` Sergei Shtylylov [this message]
2006-02-02 22:11 ` Ralf Baechle
2006-02-03 1:17 ` Atsushi Nemoto
2006-02-03 2:12 ` Sergei Shtylylov
2006-02-03 2:22 ` Atsushi Nemoto
2006-02-07 15:32 ` Sergei Shtylylov
2006-02-07 15:32 ` Sergei Shtylylov
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