[PATCH 1/4] Use pci_generic_prep_mwi on ia64

[PATCH 1/4] Use pci_generic_prep_mwi on ia64

[Matthew Wilcox]

From: linux-ia64@vger.kernel.org

The pci_generic_prep_mwi() code does everything that pcibios_prep_mwi()
does on ia64.  All we need to do is be sure that pci_cache_line_size
is set appropriately, and we can delete pcibios_prep_mwi().

Using SMP_CACHE_BYTES as the default was wrong on uniprocessor machines
as it is only 8 bytes.  The default in the generic code of L1_CACHE_BYTES
is at least as good.

Signed-off-by: Matthew Wilcox <matthew@wil.cx>
---
 arch/ia64/pci/pci.c    |   71 ++++++++++++++----------------------------------
 include/asm-ia64/pci.h |   21 +++++++-------
 2 files changed, 30 insertions(+), 62 deletions(-)

diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c
index b30be7c..4f77472 100644
--- a/arch/ia64/pci/pci.c
+++ b/arch/ia64/pci/pci.c
@@ -738,75 +738,44 @@ int ia64_pci_legacy_write(struct pci_bus
 	return ret;
 }
 
+/* It's defined in drivers/pci/pci.c */
+extern u8 pci_cache_line_size;
+
 /**
- * pci_cacheline_size - determine cacheline size for PCI devices
- * @dev: void
+ * set_pci_cacheline_size - determine cacheline size for PCI devices
  *
  * We want to use the line-size of the outer-most cache.  We assume
  * that this line-size is the same for all CPUs.
  *
  * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
- *
- * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
  */
-static unsigned long
-pci_cacheline_size (void)
+static void __init set_pci_cacheline_size(void)
 {
 	u64 levels, unique_caches;
 	s64 status;
 	pal_cache_config_info_t cci;
-	static u8 cacheline_size;
-
-	if (cacheline_size)
-		return cacheline_size;
 
 	status = ia64_pal_cache_summary(&levels, &unique_caches);
 	if (status != 0) {
-		printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
-		       __FUNCTION__, status);
-		return SMP_CACHE_BYTES;
+		printk(KERN_ERR "%s: ia64_pal_cache_summary() failed "
+			"(status=%ld)\n", __FUNCTION__, status);
+		return;
 	}
 
-	status = ia64_pal_cache_config_info(levels - 1, /* cache_type (data_or_unified)= */ 2,
-					    &cci);
+	status = ia64_pal_cache_config_info(levels - 1,
+				/* cache_type (data_or_unified)= */ 2, &cci);
 	if (status != 0) {
-		printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed (status=%ld)\n",
-		       __FUNCTION__, status);
-		return SMP_CACHE_BYTES;
+		printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed "
+			"(status=%ld)\n", __FUNCTION__, status);
+		return;
 	}
-	cacheline_size = 1 << cci.pcci_line_size;
-	return cacheline_size;
+	pci_cache_line_size = (1 << cci.pcci_line_size) / 4;
 }
 
-/**
- * pcibios_prep_mwi - helper function for drivers/pci/pci.c:pci_set_mwi()
- * @dev: the PCI device for which MWI is enabled
- *
- * For ia64, we can get the cacheline sizes from PAL.
- *
- * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
- */
-int
-pcibios_prep_mwi (struct pci_dev *dev)
-{
-	unsigned long desired_linesize, current_linesize;
-	int rc = 0;
-	u8 pci_linesize;
-
-	desired_linesize = pci_cacheline_size();
-
-	pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &pci_linesize);
-	current_linesize = 4 * pci_linesize;
-	if (desired_linesize != current_linesize) {
-		printk(KERN_WARNING "PCI: slot %s has incorrect PCI cache line size of %lu bytes,",
-		       pci_name(dev), current_linesize);
-		if (current_linesize > desired_linesize) {
-			printk(" expected %lu bytes instead\n", desired_linesize);
-			rc = -EINVAL;
-		} else {
-			printk(" correcting to %lu\n", desired_linesize);
-			pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, desired_linesize / 4);
-		}
-	}
-	return rc;
+static int __init pcibios_init(void)
+{
+	set_pci_cacheline_size();
+	return 0;
 }
+
+subsys_initcall(pcibios_init);
diff --git a/include/asm-ia64/pci.h b/include/asm-ia64/pci.h
index ef616fd..825eb7d 100644
--- a/include/asm-ia64/pci.h
+++ b/include/asm-ia64/pci.h
@@ -26,16 +26,18 @@ void pcibios_config_init(void);
 struct pci_dev;
 
 /*
- * PCI_DMA_BUS_IS_PHYS should be set to 1 if there is _necessarily_ a direct correspondence
- * between device bus addresses and CPU physical addresses.  Platforms with a hardware I/O
- * MMU _must_ turn this off to suppress the bounce buffer handling code in the block and
- * network device layers.  Platforms with separate bus address spaces _must_ turn this off
- * and provide a device DMA mapping implementation that takes care of the necessary
+ * PCI_DMA_BUS_IS_PHYS should be set to 1 if there is _necessarily_ a direct
+ * correspondence between device bus addresses and CPU physical addresses.
+ * Platforms with a hardware I/O MMU _must_ turn this off to suppress the
+ * bounce buffer handling code in the block and network device layers.
+ * Platforms with separate bus address spaces _must_ turn this off and provide
+ * a device DMA mapping implementation that takes care of the necessary
  * address translation.
  *
- * For now, the ia64 platforms which may have separate/multiple bus address spaces all
- * have I/O MMUs which support the merging of physically discontiguous buffers, so we can
- * use that as the sole factor to determine the setting of PCI_DMA_BUS_IS_PHYS.
+ * For now, the ia64 platforms which may have separate/multiple bus address
+ * spaces all have I/O MMUs which support the merging of physically
+ * discontiguous buffers, so we can use that as the sole factor to determine
+ * the setting of PCI_DMA_BUS_IS_PHYS.
  */
 extern unsigned long ia64_max_iommu_merge_mask;
 #define PCI_DMA_BUS_IS_PHYS	(ia64_max_iommu_merge_mask = ~0UL)
@@ -52,9 +54,6 @@ pcibios_penalize_isa_irq (int irq, int a
 	/* We don't do dynamic PCI IRQ allocation */
 }
 
-#define HAVE_ARCH_PCI_MWI 1
-extern int pcibios_prep_mwi (struct pci_dev *);
-
 #include <asm-generic/pci-dma-compat.h>
 
 /* pci_unmap_{single,page} is not a nop, thus... */
-- 
1.4.1.1

Re: [PATCH 3/4] [PATCH] Replace HAVE_ARCH_PCI_MWI with PCI_DISABLE_MWI

[Matthew Wilcox]

More get-send-email brokenness.  I've fixed that in my local copy and
sent the patch to the git mailing list now, so this shouldn't happen
again.

On Tue, Oct 10, 2006 at 08:01:21AM -0600, Matthew Wilcox wrote:
> From: Paul Mackerras <paulus@samba.org>, linuxppc-dev@ozlabs.org
> 
> pSeries is the only architecture left using HAVE_ARCH_PCI_MWI and it's
> really inappropriate for its needs.  It really wants to disable MWI
> altogether.  So here are a pair of stub implementations for pci_set_mwi
> and pci_clear_mwi.
> 
> Also rename pci_generic_prep_mwi to pci_set_cacheline_size since that
> better reflects what it does.
> 
> Signed-off-by: Matthew Wilcox <matthew@wil.cx>
> ---
>  drivers/pci/pci.c         |   31 ++++++++++++++++++-------------
>  include/asm-powerpc/pci.h |   20 +++++++-------------
>  2 files changed, 25 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index 2b93aaf..fc97b91 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -831,7 +831,17 @@ pci_set_master(struct pci_dev *dev)
>  	pcibios_set_master(dev);
>  }
>  
> -#ifndef HAVE_ARCH_PCI_MWI
> +#ifdef PCI_DISABLE_MWI
> +int pci_set_mwi(struct pci_dev *dev)
> +{
> +	return 0;
> +}
> +
> +void pci_clear_mwi(struct pci_dev *dev)
> +{
> +}
> +
> +#else
>  
>  #ifndef PCI_CACHE_LINE_BYTES
>  #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
> @@ -842,17 +852,17 @@ #endif
>  u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4;
>  
>  /**
> - * pci_generic_prep_mwi - helper function for pci_set_mwi
> - * @dev: the PCI device for which MWI is enabled
> + * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
> + * @dev: the PCI device for which MWI is to be enabled
>   *
> - * Helper function for generic implementation of pcibios_prep_mwi
> - * function.  Originally copied from drivers/net/acenic.c.
> + * Helper function for pci_set_mwi.
> + * Originally copied from drivers/net/acenic.c.
>   * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
>   *
>   * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
>   */
>  static int
> -pci_generic_prep_mwi(struct pci_dev *dev)
> +pci_set_cacheline_size(struct pci_dev *dev)
>  {
>  	u8 cacheline_size;
>  
> @@ -878,7 +888,6 @@ pci_generic_prep_mwi(struct pci_dev *dev
>  
>  	return -EINVAL;
>  }
> -#endif /* !HAVE_ARCH_PCI_MWI */
>  
>  /**
>   * pci_set_mwi - enables memory-write-invalidate PCI transaction
> @@ -896,12 +905,7 @@ pci_set_mwi(struct pci_dev *dev)
>  	int rc;
>  	u16 cmd;
>  
> -#ifdef HAVE_ARCH_PCI_MWI
> -	rc = pcibios_prep_mwi(dev);
> -#else
> -	rc = pci_generic_prep_mwi(dev);
> -#endif
> -
> +	rc = pci_set_cacheline_size(dev);
>  	if (rc)
>  		return rc;
>  
> @@ -932,6 +936,7 @@ pci_clear_mwi(struct pci_dev *dev)
>  		pci_write_config_word(dev, PCI_COMMAND, cmd);
>  	}
>  }
> +#endif /* ! PCI_DISABLE_MWI */
>  
>  /**
>   * pci_intx - enables/disables PCI INTx for device dev
> diff --git a/include/asm-powerpc/pci.h b/include/asm-powerpc/pci.h
> index 46afd29..721c97f 100644
> --- a/include/asm-powerpc/pci.h
> +++ b/include/asm-powerpc/pci.h
> @@ -62,19 +62,13 @@ static inline int pci_get_legacy_ide_irq
>  }
>  
>  #ifdef CONFIG_PPC64
> -#define HAVE_ARCH_PCI_MWI 1
> -static inline int pcibios_prep_mwi(struct pci_dev *dev)
> -{
> -	/*
> -	 * We would like to avoid touching the cacheline size or MWI bit
> -	 * but we cant do that with the current pcibios_prep_mwi 
> -	 * interface. pSeries firmware sets the cacheline size (which is not
> -	 * the cpu cacheline size in all cases) and hardware treats MWI 
> -	 * the same as memory write. So we dont touch the cacheline size
> -	 * here and allow the generic code to set the MWI bit.
> -	 */
> -	return 0;
> -}
> +
> +/*
> + * We want to avoid touching the cacheline size or MWI bit.
> + * pSeries firmware sets the cacheline size (which is not the cpu cacheline
> + * size in all cases) and hardware treats MWI the same as memory write.
> + */
> +#define PCI_DISABLE_MWI
>  
>  extern struct dma_mapping_ops pci_dma_ops;
>  
> -- 
> 1.4.1.1