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From: Gary Hade <garyhade@us.ibm.com>
To: Gary Hade <garyhade@us.ibm.com>
Cc: cpufreq@lists.linux.org.uk, davej@redhat.com
Subject: Re: [PATCH] speedstep-centrino should ignore upper performance control bits
Date: Tue, 7 Nov 2006 10:57:13 -0800	[thread overview]
Message-ID: <20061107185713.GC11620@us.ibm.com> (raw)
In-Reply-To: <20061106233923.GA15063@us.ibm.com>

On Mon, Nov 06, 2006 at 03:39:23PM -0800, Gary Hade wrote:
> 
> On some systems such as the IBM x3650 there are bits set in the 
> upper half of the control values provided by the _PSS object.  
> These bits are only relevant for cpufreq drivers that use IO ports 
> which are not currently supported by the speedstep-centrino driver.  
> The current MSR oriented code assumes that upper bits are not set 
> and thus fails to work correctly when they are.  e.g. the control 
> and status value equality check fails even though the ACPI spec 
> allows the inequality.
> 
> Signed-off-by: Gary Hade <garyh@us.ibm.com>

Sorry, incorrect email address.  This should be
  Signed-off-by: Gary Hade <garyhade@us.ibm.com>

Gary

-- 
Gary Hade
IBM Linux Technology Center
503-578-4503  IBM T/L: 775-4503
garyhade@us.ibm.com
http://www.ibm.com/linux/ltc

      parent reply	other threads:[~2006-11-07 18:57 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2006-11-06 23:39 [PATCH] speedstep-centrino should ignore upper performance control bits Gary Hade
2006-11-07  2:14 ` Dominik Brodowski
2006-11-07  7:09   ` Len Brown
2006-11-07 18:49     ` Gary Hade
2006-11-08 23:21       ` Gary Hade
2006-11-08 23:29         ` Dave Jones
2006-11-09  0:00           ` Gary Hade
2006-11-09  0:22             ` Dave Jones
2006-11-10 19:20               ` Gary Hade
2006-11-07 18:57 ` Gary Hade [this message]

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