From: Thiemo Seufer <ths@networkno.de>
To: Blue Swirl <blauwirbel@gmail.com>
Cc: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH, RFC] Fix softfloat NaN handling
Date: Wed, 9 May 2007 16:26:02 +0100 [thread overview]
Message-ID: <20070509152602.GB29867@networkno.de> (raw)
In-Reply-To: <f43fc5580705090817j30e9c289v4ee7c90968f0c36e@mail.gmail.com>
Blue Swirl wrote:
> On 5/9/07, Thiemo Seufer <ths@networkno.de> wrote:
> >Hello All,
> >
> >The relevant IEEE standards don't define if a set or a clear bit is
> >used to distinguish between QNaN and SNaN. MIPS, and apparently
> >PA RISC, made a different choice than the rest of the industry.
>
> On Sparc, the rule is as follows:
>
> SNaN: sign undefined, exponent 255, mantissa 0xxx...and at least one
> bit must be nonzero
> QNaN: sign undefined, exponent 255, mantissa 1xxx...
>
> Is this the same as MIPS?
For MIPS, and allegedly HPPA, the meaning of the highest bit in the
mantissa is inverted. IOW, 0xxx... is a QNaN, 1xxx... is a SNaN.
The rest is the same, and AFAIK mandated by the standard.
Thiemo
prev parent reply other threads:[~2007-05-09 15:38 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-05-09 13:20 [Qemu-devel] [PATCH, RFC] Fix softfloat NaN handling Thiemo Seufer
2007-05-09 15:17 ` Blue Swirl
2007-05-09 15:26 ` Thiemo Seufer [this message]
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