From: Thiemo Seufer <ths@networkno.de>
To: Aurelien Jarno <aurelien@aurel32.net>
Cc: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH, MIPS64] Fix Status_rw_bitmask values
Date: Fri, 8 Jun 2007 15:00:22 +0100 [thread overview]
Message-ID: <20070608140022.GE26587@networkno.de> (raw)
In-Reply-To: <4669291F.2050603@aurel32.net>
Aurelien Jarno wrote:
[snip]
> >> - 64-bit is implemented, the PX bit should be writable.
> >
> > The current version is correct, R4000 and 5K don't implement PX, the
> > 20Kc and later CPUs do.
>
> I don't know about R4000, but the 5K manual (from www.mips.com) clearly
> says that this bit is implemented. Also this bit is marked as "required"
> in the MIPS64 PRA manual (for both R1 and R2), and the 5K CPU is
> presented as a MIPS64R1 CPU.
Agreed for the 5K, I used too old Documentation to check this.
Thiemo
prev parent reply other threads:[~2007-06-08 14:00 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-06-04 21:37 [Qemu-devel] [PATCH, MIPS64] Fix Status_rw_bitmask values Aurelien Jarno
2007-06-05 13:50 ` Thiemo Seufer
2007-06-08 10:02 ` Aurelien Jarno
2007-06-08 14:00 ` Thiemo Seufer [this message]
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