From: Ralf Baechle <ralf@linux-mips.org>
To: sknauert@wesleyan.edu
Cc: Linux MIPS List <linux-mips@linux-mips.org>
Subject: Re: O2 RM7000 Issues
Date: Wed, 4 Jul 2007 20:22:08 +0100 [thread overview]
Message-ID: <20070704192208.GA7873@linux-mips.org> (raw)
In-Reply-To: <20070704152729.GA2925@linux-mips.org>
On Wed, Jul 04, 2007 at 04:27:29PM +0100, Ralf Baechle wrote:
> R5000, RM5200 and RM7000 are all MIPS IV processors so have the same
> instruction set. That leaves the usual suspects - pipeline hazards,
> cache problems and CPU bugs to research.
Big loud bell began ringing. The RM7000 fetches and decodes multiple
instructions in one go. And just like the E9000 cores it does
throw an exception if it doesn't like one of the opcodes even if that
doesn't actually get executed. The kernel has a workaround for this
PMC-Sierra peculiarity (I call it a bug) but it's only being activated
for E9000 platforms.
Ralf
next prev parent reply other threads:[~2007-07-04 19:22 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-07-01 16:57 O2 RM7000 Issues Kumba
2007-07-01 22:07 ` freshy98
2007-07-02 13:08 ` sknauert
2007-07-02 13:08 ` sknauert
2007-07-04 15:27 ` Ralf Baechle
2007-07-04 19:22 ` Ralf Baechle [this message]
2007-07-16 11:53 ` Sergey Rogozhkin
2007-07-16 12:33 ` Ralf Baechle
2007-07-16 17:38 ` Andrew Sharp
2007-07-17 14:01 ` Kumba
2007-07-19 18:58 ` Andrew Sharp
2007-07-19 22:26 ` Shane McDonald
2007-07-17 7:54 ` Gleb O. Raiko
2007-07-17 9:04 ` Sergey Rogozhkin
2007-07-17 10:14 ` Ralf Baechle
2007-07-17 12:27 ` Ralf Baechle
2007-09-17 23:04 ` Steve Graham
2007-09-18 8:52 ` Ralf Baechle
2007-09-17 23:20 ` David Daney
2007-09-18 8:47 ` Ralf Baechle
2007-07-02 14:34 ` Maciej W. Rozycki
2007-09-21 6:27 ` Sagar Borikar
2007-09-21 13:47 ` Ralf Baechle
2007-09-22 3:20 ` Steve Graham
2007-09-24 11:58 ` Ralf Baechle
2007-09-26 17:06 ` Steve Graham
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