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From: Andi Kleen <andi@firstfloor.org>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Andi Kleen <andi@firstfloor.org>,
	Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com>,
	linux-kernel@vger.kernel.org
Subject: Re: Fwd: x86_64 and AMD with C1E
Date: Mon, 1 Oct 2007 17:21:53 +0200	[thread overview]
Message-ID: <20071001152153.GB19797@one.firstfloor.org> (raw)
In-Reply-To: <alpine.LRH.0.999.0710011652470.7353@www.tglx.de>


> So if the
> number of hpet channels is greater/equal to the number of possible
> CPUs it's perfectly fine and does not need IPI at all.

That is only a stop gap then. I don't see this being
generally true in the future. e.g. Intel announced SMT will be soon 
back so even a standard dual core would exceed it with
current southbridges.

Also I'm not sure but I suspect non Intel HPETs have less than
three timers. Certainly they generally miss the 64bitness.

-Andi

  reply	other threads:[~2007-10-01 15:22 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2007-10-01  6:15 x86_64 and AMD with C1E Mikhail Kshevetskiy
2007-10-01  9:33 ` Andi Kleen
     [not found]   ` <b70f2f960710010546k4658aa1ay466f243ac707c989@mail.gmail.com>
2007-10-01 12:50     ` Fwd: " Mikhail Kshevetskiy
2007-10-01 14:14       ` Thomas Gleixner
2007-10-01 14:32         ` Andi Kleen
2007-10-01 14:59           ` Thomas Gleixner
2007-10-01 15:21             ` Andi Kleen [this message]
2007-10-01 16:44               ` Thomas Gleixner
2007-10-01 17:56               ` Chuck Ebbert
2007-10-01 14:33         ` Mikhail Kshevetskiy
2007-10-01 13:09     ` Andi Kleen
2007-10-01 14:06       ` Arjan van de Ven
2007-10-01 14:40       ` Mikhail Kshevetskiy
2007-10-19 16:39 ` Chuck Ebbert
2007-10-24 21:26   ` Mikhail Kshevetskiy
2007-10-24 21:41     ` Chuck Ebbert
2007-10-24 22:12       ` Thomas Gleixner
2007-10-24 22:42       ` Mikhail Kshevetskiy
2007-12-15 11:06       ` Thomas Gleixner

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